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1. 发明申请

US20060215677A1 Flexible control block format for frame description and management 失效
标题翻译：灵活的控制块格式，用于帧描述和管理
公开(公告)号：US20060215677A1
公开(公告)日：2006-09-28
申请号：US11091245
申请日：2005-03-28
申请人： Claude Basso , Jean Calvignac , Chih-jen Chang , Philippe Damon , Joseph Logan , Fabrice Verplanken
发明人： Claude Basso , Jean Calvignac , Chih-jen Chang , Philippe Damon , Joseph Logan , Fabrice Verplanken
IPC分类号： H04L12/26 , H04L12/56
CPC分类号： H04L12/5601 , H04L49/90 , H04L2012/5642 , H04L2012/5652 , H04L2012/5658 , H04L2012/5681
摘要： A communication network used to link information handling systems together utilizes a switching network to transmit data among senders and receivers. Each individual packet of data is described and controlled by an FCB. The bandwidth associated with the storing and distribution of data is optimized by chaining the data packets in different types of queues, or operating without chaining outside a queue. When a frame is in an output queue, the third word contains an RFCBA for egress of the frame to a line port, and an MCID for ingress from an output queue to a switch port. The RFCBA and the MCID have multicast capabilities. The format does not require a third word when a frame is in an input queue.
摘要翻译：用于将信息处理系统链接在一起的通信网络利用交换网络在发送者和接收者之间传送数据。每个单独的数据包由FCB描述和控制。与存储和分发数据相关联的带宽通过将数据分组链接在不同类型的队列中进行优化，或者在不在队列外链接的情况下运行。当帧位于输出队列中时，第三个字包含用于将帧从线路端口排出的RFCBA，以及用于从输出队列进入交换机端口的MCID。 RFCBA和MCID具有多播功能。当帧在输入队列中时，格式不需要第三个字。

2. 发明申请

US20070011223A1 Method and system for flexible network processor scheduler and data flow 失效
标题翻译：灵活的网络处理器调度器和数据流的方法和系统
公开(公告)号：US20070011223A1
公开(公告)日：2007-01-11
申请号：US11133477
申请日：2005-05-18
申请人： Jean Calvignac , Chih-jen Chang , Joseph Logan , Fabrice Verplanken , Daniel Wind
发明人： Jean Calvignac , Chih-jen Chang , Joseph Logan , Fabrice Verplanken , Daniel Wind
IPC分类号： G06F15/16
CPC分类号： H04L47/527 , H04L47/50 , H04L47/522 , H04L47/568 , H04L47/58
摘要： A network processor dataflow chip and method for flexible dataflow are provided. The dataflow chip comprises a plurality of on-chip data transmission and scheduling circuit structures. The data transmission and scheduling circuit structures are selected responsive to indicators. Data transmission circuit structures may comprise selectable frame processing and data transmission functions. Selectable frame processing may comprise cut and paste, full dispatch and store and dispatch frame processing. Scheduling functions include full internal scheduling, calendar scheduling in communication with an external scheduler, and external calendar scheduling. In another aspect of the present invention, data transmission functions may comprise low latency and normal latency external processor interfaces for selectively providing privileged access to dataflow chip resources.
摘要翻译：提供了一种用于灵活数据流的网络处理器数据流芯片和方法。数据流芯片包括多个片上数据传输和调度电路结构。响应于指标选择数据传输和调度电路结构。数据传输电路结构可以包括可选择的帧处理和数据传输功能。可选择的帧处理可以包括剪切和粘贴，完全调度和存储和调度帧处理。调度功能包括完整的内部调度，与外部调度器进行通信的日历调度以及外部日历调度。在本发明的另一方面，数据传输功能可以包括用于选择性地提供对数据流芯片资源的特权访问的低延迟和正常等待时间的外部处理器接口。

3. 发明申请

US20060209827A1 Systems and methods for implementing counters in a network processor with cost effective memory 失效
标题翻译：在具有成本效益的存储器的网络处理器中实现计数器的系统和方法
公开(公告)号：US20060209827A1
公开(公告)日：2006-09-21
申请号：US11070060
申请日：2005-03-02
申请人： Jean Calvignac , Chih-jen Chang , Joseph Logan , Fabrice Verplanken
发明人： Jean Calvignac , Chih-jen Chang , Joseph Logan , Fabrice Verplanken
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： H04L49/901 , H04L49/90
摘要： Systems and methods for implementing counters in a network processor with cost effective memory are disclosed. Embodiments include systems and methods for implementing counters in a network processor using less expensive memory such as DRAM. A network processor receives packets and implements accounting functions including counting packets in each of a plurality of flow queues. Embodiments include a counter controller that may increment counter values more than once during a R-M-W cycle. Each time a counter controller receives a request to update a counter during a R-M-W cycle that has been initiated for the counter, the counter controller increments the counter value received from memory. The incremented value is written to memory during the write cycle of the R-M-W cycle. A write disable unit disables writes that would otherwise occur during R-M-W cycles initiated for the counter during the earlier initiated R-M-W cycle.
摘要翻译：公开了在具有成本效益的存储器的网络处理器中实现计数器的系统和方法。实施例包括用于在使用诸如DRAM的廉价存储器的网络处理器中实现计数器的系统和方法。网络处理器接收分组并实现计费功能，包括在多个流队列中的每一个中计数分组。实施例包括可以在R-M-W周期期间多次增加计数器值的计数器控制器。每当计数器控制器在已经为计数器启动的R-M-W周期期间接收到更新计数器的请求时，计数器控制器增加从存储器接收的计数器值。在R-M-W周期的写周期期间，递增的值被写入存储器。写禁止单元禁用在较早启动的R-M-W周期期间为计数器启动的R-M-W周期期间将发生的写入。

4. 发明申请

US20060222002A1 Configurable ports for a host Ethernet adapter 失效
标题翻译：适用于主机以太网适配器的可配置端口
公开(公告)号：US20060222002A1
公开(公告)日：2006-10-05
申请号：US11097652
申请日：2005-04-01
申请人： Claude Basso , Jean Calvignac , Chih-Jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin Verrilli
发明人： Claude Basso , Jean Calvignac , Chih-Jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin Verrilli
IPC分类号： H04J3/22 , H04J3/16
CPC分类号： H04L12/40032 , H04L12/413 , H04L49/90 , H04L69/12 , H04L69/16 , H04L69/161 , H04L69/18 , H04L69/323 , H04L69/324
摘要： A system and method in accordance with the present invention allows for an adapter to be utilized in a server environment that can accommodate both a 10 G and a 1 G source utilizing the same pins. This is accomplished through the use of a high speed serializer/deserializer (high speed serdes) which can accommodate both data sources. The high speed serdes allows for the use of a relatively low reference clock speed on the NIC to provide the proper clocking of the data sources and also allows for different modes to be set to accommodate the different data sources. Finally the system allows for the adapter to use the same pins for multiple data sources.
摘要翻译：根据本发明的系统和方法允许在可以使用相同引脚容纳10G和1G源的服务器环境中使用适配器。这是通过使用可以容纳两个数据源的高速串行器/解串器（高速serdes）来实现的。高速serdes允许在NIC上使用相对较低的参考时钟速度来提供数据源的适当时钟，并且还允许设置不同的模式以适应不同的数据源。最后，该系统允许适配器为多个数据源使用相同的引脚。

5. 发明申请

US20060221969A1 System and method for computing a blind checksum in a host ethernet adapter (HEA) 失效
公开(公告)号：US20060221969A1
公开(公告)日：2006-10-05
申请号：US11097430
申请日：2005-04-01
申请人： Claude Basso , Jean Calvignac , Chih-jen Chang , Philippe Damon , Ronald Fuhs , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin Verrilli , Scott Willenborg
发明人： Claude Basso , Jean Calvignac , Chih-jen Chang , Philippe Damon , Ronald Fuhs , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin Verrilli , Scott Willenborg
IPC分类号： H04L12/28
CPC分类号： H04L69/16 , H04L69/161
摘要： A system and method for computing a blind checksum includes a host Ethernet adapter (HEA) with a system for receiving a packet. The system determines whether or not the packet is in Internet protocol version four (IPv4). If the packet is not in IPv4, the system computes the checksum of the packet. If the packet is in IPv4, the system determines whether the packet is in transmission control protocol (TCP) or user datagram protocol (UDP). If the packet is not in either of TCP or UDP the system attaches a pseudo-header to the packet and computes the checksum of the packet based on the pseudo-header and the IPv4 standard.

6. 发明申请

US20060221961A1 Network communications for operating system partitions 有权
标题翻译：操作系统分区的网络通信
公开(公告)号：US20060221961A1
公开(公告)日：2006-10-05
申请号：US11097051
申请日：2005-04-01
申请人： Claude Basso , Jean Calvignac , Chih-Jen Chang , Philippe Damon , Ronald Fuhs , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin Verrilli , Scott Willenborg
发明人： Claude Basso , Jean Calvignac , Chih-Jen Chang , Philippe Damon , Ronald Fuhs , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin Verrilli , Scott Willenborg
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： H04L29/06 , H04L49/90 , H04L69/32
摘要： Providing communications between operating system partitions and a computer network. In one aspect, an apparatus for distributing network communications among multiple operating system partitions includes a physical port allowing communications between the network and the computer system, and logical ports associated with the physical port, where each logical port is associated with one of the operating system partitions. Each of the logical ports enables communication between a physical port and the associated operating system partition and allows configurability of network resources of the system. Other aspects include a logical switch for logical and physical ports, and packet queues for each connection and for each logical port.
摘要翻译：提供操作系统分区与计算机网络之间的通信。一方面，一种用于在多个操作系统分区之间分配网络通信的装置包括允许网络和计算机系统之间的通信的物理端口以及与物理端口相关联的逻辑端口，其中每个逻辑端口与操作系统之一相关联分区。每个逻辑端口实现物理端口与相关联的操作系统分区之间的通信，并允许系统的网络资源的可配置性。其他方面包括用于逻辑和物理端口的逻辑交换机，以及每个连接和每个逻辑端口的分组队列。

7. 发明申请

US20060221952A1 System and method for parsing, filtering, and computing the checksum in a host ethernet adapter (HEA) 有权
标题翻译：在主机以太网适配器（HEA）中解析，过滤和计算校验和的系统和方法
公开(公告)号：US20060221952A1
公开(公告)日：2006-10-05
申请号：US11096365
申请日：2005-04-01
申请人： Claude Basso , Jean Calvignac , Chih-Jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin Verrilli
发明人： Claude Basso , Jean Calvignac , Chih-Jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin Verrilli
IPC分类号： H04J3/24 , H04L12/56 , H04L12/28
CPC分类号： H04L1/0052 , H04L1/0061
摘要： A system and method for parsing, filtering, and computing the checksum in a host Ethernet adapter (HEA) that is coupled to a host. The method includes receiving a part of a frame, wherein a plurality of parts of a frame constitute a entire frame. Next, parse the part of a frame before receiving the entire frame. The HEA computes a checksum of the part of a frame. The HEA filters the part of a frame based on a logical, port-specific policy and transmits the checksum to the host.
摘要翻译：用于在耦合到主机的主机以太网适配器（HEA）中解析，过滤和计算校验和的系统和方法。该方法包括接收帧的一部分，其中帧的多个部分构成整个帧。接下来，在接收整个帧之前解析帧的一部分。 HEA计算帧的一部分的校验和。 HEA基于逻辑，端口特定策略过滤帧的一部分，并将校验和传送到主机。

8. 发明申请

US20060206684A1 Systems and methods for multi-frame control blocks 有权
公开(公告)号：US20060206684A1
公开(公告)日：2006-09-14
申请号：US11076218
申请日：2005-03-09
申请人： Claude Basso , Jean Calvignac , Chih-jen Chang , Fabrice Verplanken
发明人： Claude Basso , Jean Calvignac , Chih-jen Chang , Fabrice Verplanken
IPC分类号： G06F12/00 , G06F9/34
CPC分类号： H04L49/901 , H04L49/252 , H04L49/30 , H04L49/90 , H04L69/12 , H04L69/22
摘要： Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives packets of data, the network processor forms a frame control block for each packet. The frame control block contains a pointer to a memory location where the packet data is stored, and is thereby associated with the packet. The network processor associates a plurality of frame control blocks together in a table control block that is stored in a control store. Each table control block comprises a pointer to a memory location of a next table control block in a chain of table control blocks. Because frame control blocks are stored and accessed in table control blocks, less frequent memory accesses may be needed to keep up with the frame rate of packet transmission.

9. 发明申请

US20060200615A1 Systems and methods for adaptively mapping an instruction cache 失效
标题翻译：用于自适应地映射指令高速缓存的系统和方法
公开(公告)号：US20060200615A1
公开(公告)日：2006-09-07
申请号：US11070758
申请日：2005-03-02
申请人： Claude Basso , Jean Calvignac , Chih-jen Chang , Harm Hofstee , Jens Leenstra , Hans-Werner Tast , Fabrice Verplanken , Colin Verrilli
发明人： Claude Basso , Jean Calvignac , Chih-jen Chang , Harm Hofstee , Jens Leenstra , Hans-Werner Tast , Fabrice Verplanken , Colin Verrilli
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0864
摘要： Systems and methods for adaptively mapping system memory address bits into an instruction tag and an index into the cache are disclosed. More particularly, hardware and software are disclosed for observing collisions that occur for a given mapping of system memory bits into a tag and an index. Based on the observations, an optimal mapping may be determined that minimizes collisions.
摘要翻译：公开了用于将系统存储器地址位自适应地映射到指令标签和到高速缓存中的索引的系统和方法。更具体地，公开了用于观察对于系统存储器位给定到标签和索引的映射而出现的冲突的硬件和软件。基于观察结果，可以确定最小化碰撞的最佳映射。

10. 发明申请

US20060039376A1 Method and structure for enqueuing data packets for processing 失效
标题翻译：排队处理数据包的方法和结构
公开(公告)号：US20060039376A1
公开(公告)日：2006-02-23
申请号：US10868725
申请日：2004-06-15
申请人： Claude Basso , Jean Calvignac , Chih-jen Chang , Gordon Davis , Fabrice Verplanken
发明人： Claude Basso , Jean Calvignac , Chih-jen Chang , Gordon Davis , Fabrice Verplanken
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： H04L49/90 , H04L49/9042 , H04L49/9073 , H04L69/22
摘要： A method and structure is provided for buffering data packets having a header and a remainder in a network processor system. The network processor system has a processor on a chip and at least one buffer on the chip. Each buffer on the chip is configured to buffer the header of the packets in a preselected order before execution in the processor, and the remainder of the packet is stored in an external buffer apart from the chip. The method comprises utilizing the header information to identify the location and extent of the remainder of the packet. The entire selected packet is stored in the external buffer when the buffer of the stored header of the given packet is full, and moving only the header of a selected packet stored in the external buffer to the buffer on the chip when the buffer on the chip has space therefor.
摘要翻译：提供了一种在网络处理器系统中缓冲具有报头和余数的数据分组的方法和结构。网络处理器系统在芯片上具有处理器和芯片上的至少一个缓冲器。芯片上的每个缓冲器被配置为在处理器中执行之前以预先选择的顺序缓冲数据包的报头，并且数据包的剩余部分存储在与芯片分离的外部缓冲器中。该方法包括利用报头信息来识别分组的其余部分的位置和范围。当给定分组的存储报头的缓冲器已满时，整个所选分组被存储在外部缓冲器中，并且当芯片上的缓冲器仅将存储在外部缓冲器中的选定分组的报头移动到芯片上的缓冲器时有空间。

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