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51. 发明申请

US20080315317A1 SEMICONDUCTOR SYSTEM HAVING COMPLEMENTARY STRAINED CHANNELS 审中-公开
标题翻译：具有补充应变通道的半导体系统
公开(公告)号：US20080315317A1
公开(公告)日：2008-12-25
申请号：US11767449
申请日：2007-06-22
申请人： Chung Woh Lai , Yong Meng Lee , Wenhe Lin , Khee Yong Lim , Young Way Teh , Wee Leng Tan , Hui Peng Koh , John Sudijono , Liang-Choo Hsia
发明人： Chung Woh Lai , Yong Meng Lee , Wenhe Lin , Khee Yong Lim , Young Way Teh , Wee Leng Tan , Hui Peng Koh , John Sudijono , Liang-Choo Hsia
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/31155 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/66606 , H01L29/7843
摘要： A semiconductor system is provided including providing a semiconductor substrate; forming PMOS and NMOS transistors in and on the semiconductor substrate; forming a tensile strained layer on the semiconductor substrate; and relaxing the tensile strained layer around the PMOS transistor.
摘要翻译：提供一种半导体系统，包括提供半导体衬底; 在半导体衬底中形成PMOS和NMOS晶体管; 在半导体衬底上形成拉伸应变层; 并放宽PMOS晶体管周围的拉伸应变层。

52. 发明授权

US07421676B2 System and method for phase shift assignment 有权
标题翻译：用于相移分配的系统和方法
公开(公告)号：US07421676B2
公开(公告)日：2008-09-02
申请号：US10942689
申请日：2004-09-15
申请人： Sia Kim Tan , Qunying Lin , Liang-Choo Hsia
发明人： Sia Kim Tan , Qunying Lin , Liang-Choo Hsia
IPC分类号： G06F17/50
CPC分类号： G03F1/30
摘要： A semiconductor design is provided having at least one feature at one of a line end and a line junction, and phase regions. At least one cut line is added to at least one of such features at line ends and such features at line junctions. Phases are assigned to the phase regions. The manufacturing of a photomask with the assigned phase regions is directed.
摘要翻译：提供半导体设计，其具有线端和线结中的一个以及相位区域中的至少一个特征。至少一条切割线被添加到线端的这些特征中的至少一个并且线结处的这些特征。阶段分配给相位区域。指定具有指定相位区域的光掩模的制造。

53. 发明授权

US07384714B2 Anti-reflective sidewall coated alternating phase shift mask and fabrication method 有权
标题翻译：抗反射侧壁涂层交替相移掩模及其制作方法
公开(公告)号：US07384714B2
公开(公告)日：2008-06-10
申请号：US10973526
申请日：2004-10-25
申请人： Sia Kim Tan , Qunying Lin , Liang-Choo Hsia
发明人： Sia Kim Tan , Qunying Lin , Liang-Choo Hsia
IPC分类号： G03F1/00
CPC分类号： G03F1/30
摘要： A method for fabricating a phase shift mask is provided. A trenched phase shift mask having portions of a light-blocking layer thereon is formed. A layer of anti-reflective material is then formed on the trenched phase shift mask and the portions of the light-blocking layer. The anti-reflective material is then removed on horizontal surfaces of the trenched phase shift mask and of the portions of the light-blocking layer.
摘要翻译：提供了制造相移掩模的方法。形成其上具有遮光层的部分的沟槽相移掩模。然后在沟槽相移掩模和遮光层的部分上形成一层抗反射材料。然后在沟槽相移掩模的水平表面和遮光层的部分上去除抗反射材料。

54. 发明申请

US20080087958A1 SEMICONDUCTOR DEVICE WITH DOPED TRANSISTOR 审中-公开
标题翻译：带有DOPED晶体管的半导体器件
公开(公告)号：US20080087958A1
公开(公告)日：2008-04-17
申请号：US11951833
申请日：2007-12-06
申请人： Purakh Verma , Liang-Choo Hsia , Dong Kyun Sohn , Guowei Zhang , Chew Hoe Ang , Yun Ling Tan , Zhao Lun , Jae Gon Lee , Yung Fu Chong
发明人： Purakh Verma , Liang-Choo Hsia , Dong Kyun Sohn , Guowei Zhang , Chew Hoe Ang , Yun Ling Tan , Zhao Lun , Jae Gon Lee , Yung Fu Chong
IPC分类号： H01L27/088
CPC分类号： H01L21/82385 , H01L21/823814 , H01L21/823857 , H01L27/11 , H01L29/66545 , H01L29/7833
摘要： A semiconductor device provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is formed in the second region. A second region gate is formed on the second region gate dielectric. A second region source/drain is formed in the second region. A sacrificial layer is formed over the sacrificial first gate, the source/drain, the first region, and the second region. The sacrificial first gate is exposed. A gate space is formed by removing the sacrificial first gate. A first region gate dielectric is formed in the gate space. A first region gate is formed on the first region gate dielectric. The sacrificial layer is removed.
摘要翻译：半导体器件提供具有第一区域和第二区域的衬底。牺牲第一栅极形成在第一区域中。源极/漏极形成在第一区域中。第二区域栅极电介质形成在第二区域中。第二区域栅极形成在第二区域栅极电介质上。在第二区域中形成第二区域源极/漏极。在牺牲第一栅极，源极/漏极，第一区域和第二区域上形成牺牲层。牺牲的第一个门被暴露。通过去除牺牲第一栅极形成栅极空间。在栅极空间中形成第一区域栅极电介质。第一区栅极形成在第一区栅极电介质上。牺牲层被去除。

55. 发明授权

US07253097B2 Integrated circuit system using dual damascene process 有权
标题翻译：集成电路系统采用双镶嵌工艺
公开(公告)号：US07253097B2
公开(公告)日：2007-08-07
申请号：US11160624
申请日：2005-06-30
申请人： Yeow Kheng Lim , Chim Seng Seet , Tae Jong Lee , Liang-Choo Hsia , Kin Leong Pey
发明人： Yeow Kheng Lim , Chim Seng Seet , Tae Jong Lee , Liang-Choo Hsia , Kin Leong Pey
IPC分类号： H01L21/4763
CPC分类号： H01L21/76831 , H01L21/76814 , H01L21/76844 , H01L21/76846
摘要： An integrated circuit system includes providing a semiconductor substrate having a semiconductor device provided thereon. A first dielectric layer is formed over the semiconductor substrate, and a first conductor core is formed in the first dielectric layer. A stop layer is formed over the first conductor core. A second dielectric layer is formed over the stop layer. A channel and a via are formed in the second dielectric layer. The channel and the via in the second dielectric layer are wet cleaned. A barrier metal layer is deposited to line the channel and the via in the second dielectric layer. The barrier metal layer is selectively etched from the bottom of the via in the dielectric layer, and a second conductor core is formed over the barrier metal layer to fill the second channel and the via to connect the second conductor core to the first conductor core.
摘要翻译：集成电路系统包括提供其上设置有半导体器件的半导体衬底。第一电介质层形成在半导体衬底之上，并且第一导体芯形成在第一电介质层中。在第一导体芯上形成停止层。在停止层上形成第二电介质层。在第二电介质层中形成沟道和通孔。第二介质层中的通道和通孔被湿清洗。沉积阻挡金属层以在第二介电层中对通道和通孔进行排列。从电介质层中的通孔的底部选择性地蚀刻阻挡金属层，并且在阻挡金属层上方形成第二导体芯以填充第二通道和通孔，以将第二导体芯连接到第一导体芯。

56. 发明申请

US20070090484A1 INTEGRATED CIRCUIT STRESS CONTROL SYSTEM 审中-公开
标题翻译：集成电路应力控制系统
公开(公告)号：US20070090484A1
公开(公告)日：2007-04-26
申请号：US11162027
申请日：2005-08-25
申请人： Jae Gon Lee , Cher Sian Chua , Chew Hoe Ang , Liang-Choo Hsia
发明人： Jae Gon Lee , Cher Sian Chua , Chew Hoe Ang , Liang-Choo Hsia
IPC分类号： H01L29/00
CPC分类号： H01L21/823807 , H01L21/823878 , H01L29/7842
摘要： An integrated circuit stress control system is provided. A gate is formed on a substrate and a channel is formed in the substrate. A source/drain is formed around the gate. A shallow trench isolation is formed in the substrate, the shallow trench isolation producing strain on the channel. A stress suppressing feature is formed in the substrate.
摘要翻译：提供集成电路应力控制系统。栅极形成在衬底上，并且沟道形成在衬底中。源极/漏极围绕栅极形成。在衬底中形成浅沟槽隔离，通道上的浅沟槽隔离产生应变。在基板上形成应力抑制特征。

57. 发明申请

US20070001303A1 INTEGRATED CIRCUIT SYSTEM USING DUAL DAMASCENE PROCESS 有权
标题翻译：集成电路系统使用双重DAMASCENE过程
公开(公告)号：US20070001303A1
公开(公告)日：2007-01-04
申请号：US11160624
申请日：2005-06-30
申请人： Yeow Kheng Lim , Chim Seng Seet , Tae Jong Lee , Liang-Choo Hsia , Kin Leong Pey
发明人： Yeow Kheng Lim , Chim Seng Seet , Tae Jong Lee , Liang-Choo Hsia , Kin Leong Pey
IPC分类号： H01L23/52
CPC分类号： H01L21/76831 , H01L21/76814 , H01L21/76844 , H01L21/76846
摘要： An integrated circuit system includes providing a semiconductor substrate having a semiconductor device provided thereon. A first dielectric layer is formed over the semiconductor substrate, and a first conductor core is formed in the first dielectric layer. A stop layer is formed over the first conductor core. A second dielectric layer is formed over the stop layer. A channel and a via are formed in the second dielectric layer. The channel and the via in the second dielectric layer are wet cleaned. A barrier metal layer is deposited to line the channel and the via in the second dielectric layer. The barrier metal layer is selectively etched from the bottom of the via in the dielectric layer, and a second conductor core is formed over the barrier metal layer to fill the second channel and the via to connect the second conductor core to the first conductor core.
摘要翻译：集成电路系统包括提供其上设置有半导体器件的半导体衬底。第一电介质层形成在半导体衬底之上，并且第一导体芯形成在第一电介质层中。在第一导体芯上形成停止层。在停止层上形成第二电介质层。在第二电介质层中形成沟道和通孔。第二介质层中的通道和通孔被湿清洗。沉积阻挡金属层以在第二介电层中对通道和通孔进行排列。从电介质层中的通孔的底部选择性地蚀刻阻挡金属层，并且在阻挡金属层上方形成第二导体芯以填充第二通道和通孔，以将第二导体芯连接到第一导体芯。

58. 发明申请

US20060252188A1 SEMICONDUCTOR DEVICE AND FABRICATION METHOD 有权
标题翻译：半导体器件和制造方法
公开(公告)号：US20060252188A1
公开(公告)日：2006-11-09
申请号：US10908328
申请日：2005-05-06
申请人： Purakh Verma , Liang-Choo Hsia , Dong Kyun Sohn , Guowei Zhang , Chew Hoe Ang , Yun Ling Tan , Zhao Lun , Jae Gon Lee , Yung Fu Chong
发明人： Purakh Verma , Liang-Choo Hsia , Dong Kyun Sohn , Guowei Zhang , Chew Hoe Ang , Yun Ling Tan , Zhao Lun , Jae Gon Lee , Yung Fu Chong
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： H01L21/82385 , H01L21/823814 , H01L21/823857 , H01L27/11 , H01L29/66545 , H01L29/7833
摘要： A method and apparatus for manufacturing a semiconductor device is provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is formed in the second region. A second region gate is formed on the second region gate dielectric. A second region source/drain is formed in the second region. A sacrificial layer is formed over the sacrificial first gate, the source/drain, the first region, and the second region. The sacrificial first gate is exposed. A gate space is formed by removing the sacrificial first gate. A first region gate dielectric is formed in the gate space. A first region gate is formed on the first region gate dielectric. The sacrificial layer is removed.
摘要翻译：用于制造半导体器件的方法和设备提供具有第一区域和第二区域的衬底。牺牲第一栅极形成在第一区域中。源极/漏极形成在第一区域中。第二区域栅极电介质形成在第二区域中。第二区域栅极形成在第二区域栅极电介质上。在第二区域中形成第二区域源极/漏极。在牺牲第一栅极，源极/漏极，第一区域和第二区域上形成牺牲层。牺牲的第一个门被暴露。通过去除牺牲第一栅极形成栅极空间。在栅极空间中形成第一区域栅极电介质。第一区栅极形成在第一区栅极电介质上。牺牲层被去除。

59. 发明申请

US20060099518A1 Method to resolve line end distortion for alternating phase shift mask 有权
标题翻译：解决交变相移掩模线路失真的方法
公开(公告)号：US20060099518A1
公开(公告)日：2006-05-11
申请号：US10985263
申请日：2004-11-10
申请人： Sia Tan , Qunying Lin , Liang-Choo Hsia
发明人： Sia Tan , Qunying Lin , Liang-Choo Hsia
IPC分类号： G06F17/50 , G03F1/00
CPC分类号： G03F1/30
摘要： A embodiment method for forming a layout for a phase shift mask. A embodiment comprises providing a layout comprising a first feature, a first shifter region and a second shifter region. The first feature preferably has a L-shape portion with an elbow region. The first shifter region is on the outside of the L-shaped portion and the second shifter region is on the inside of the L-shaped portion. The elbow region has an outside corner away from the second shifter region. We identify a phase conflict region caused by the L-shaped portion of the first feature, the first shifter region and the second shifter region. We resolve the phase conflict by modifying the elbow region by moving the outside corner of the elbow region away from the first shifter region and the phase conflict region. The modification of the elbow region further comprises forming a jog region in the line end section of the first feature.
摘要翻译：一种用于形成相移掩模布局的实施例方法。实施例包括提供包括第一特征，第一移位区和第二移位区的布局。第一特征优选具有肘部区域的L形部分。第一移位区域位于L形部分的外侧，第二移位区域位于L形部分的内侧。肘部区域具有远离第二移位区域的外角。我们识别由第一特征的L形部分，第一移位区域和第二移位区域引起的相位冲突区域。我们通过移动肘部区域的外角远离第一移位区域和相位冲突区域来修改肘部区域来解决相位冲突。肘部区域的修改还包括在第一特征的线端部中形成点动区域。

60. 发明申请

US20060088771A1 Anti-reflective sidewall coated alternating phase shift mask and fabrication method 有权
标题翻译：抗反射侧壁涂层交替相移掩模及其制作方法
公开(公告)号：US20060088771A1
公开(公告)日：2006-04-27
申请号：US10973526
申请日：2004-10-25
申请人： Sia Tan , Qunying Lin , Liang-Choo Hsia
发明人： Sia Tan , Qunying Lin , Liang-Choo Hsia
IPC分类号： G03C5/00 , G03F1/00
CPC分类号： G03F1/30
摘要： A method for fabricating a phase shift mask is provided. A trenched phase shift mask having portions of a light-blocking layer thereon is formed. A layer of anti-reflective material is then formed on the trenched phase shift mask and the portions of the light-blocking layer. The anti-reflective material is then removed on horizontal surfaces of the trenched phase shift mask and of the portions of the light-blocking layer.
摘要翻译：提供了制造相移掩模的方法。形成其上具有遮光层的部分的沟槽相移掩模。然后在沟槽相移掩模和遮光层的部分上形成一层抗反射材料。然后在沟槽相移掩模的水平表面和遮光层的部分上去除抗反射材料。

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