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51. 发明授权

US07190620B2 Method for operating a memory device 有权
标题翻译：操作存储器件的方法
公开(公告)号：US07190620B2
公开(公告)日：2007-03-13
申请号：US11029380
申请日：2005-01-06
申请人： Eduardo Maayan , Boaz Eitan
发明人： Eduardo Maayan , Boaz Eitan
IPC分类号： G11C16/04
CPC分类号： G11C29/028 , G11C16/04 , G11C16/0475 , G11C16/10 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C29/02 , G11C29/021 , G11C29/50 , G11C29/50004
摘要： A method and a system for operating bits of memory cells in a memory array, the method including applying a first operating pulse to a terminal of a first cell, the first operating pulse is intended to place the first cell into a predefined state; and applying a second operating pulse to a terminal of a second cell in the set, the second operating pulse is intended to place the second cell to the predefined state, and the pulse characteristics of the second operating pulse are a function of the response of the first cell to the first operating pulse.
摘要翻译：一种用于操作存储器阵列中的存储器单元的位的方法和系统，所述方法包括将第一操作脉冲施加到第一单元的端子，所述第一操作脉冲旨在将所述第一单元放置在预定状态; 以及将第二操作脉冲施加到所述组中的第二小区的终端，所述第二操作脉冲旨在将所述第二小区置于所述预定状态，并且所述第二操作脉冲的脉冲特性是所述第二操作脉冲的响应的函数第一个电池到第一个工作脉冲。

52. 发明申请

US20070032016A1 Protective layer in memory device and method therefor 审中-公开
标题翻译：存储器件中的保护层及其方法
公开(公告)号：US20070032016A1
公开(公告)日：2007-02-08
申请号：US11490483
申请日：2006-07-20
申请人： Ilan Bloom , Boaz Eitan
发明人： Ilan Bloom , Boaz Eitan
IPC分类号： H01L21/336
CPC分类号： H01L21/28194 , H01L21/28202 , H01L27/115 , H01L27/11568 , H01L29/513 , H01L29/518 , H01L29/66833 , H01L29/792 , Y10S438/954
摘要： A method protecting a non-volatile memory device, the method including forming a non-volatile memory device including a polycide structure formed over a non-conducting charge trapping layer, and forming a protective layer over at least a portion of the polycide structure, die protective layer being adapted to absorb electromagnetic wave energy having a wavelength shorter than visible light. A device constructed in accordance with the method is also disclosed.
摘要翻译：一种保护非易失性存储器件的方法，所述方法包括形成非易失性存储器件，该非易失性存储器件包括在非导电电荷俘获层上形成的多晶硅结构，以及在该多晶硅结构的至少一部分上形成保护层保护层适于吸收波长短于可见光的电磁波能量。还公开了根据该方法构造的装置。

53. 发明申请

US20060262598A1 Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping 有权
公开(公告)号：US20060262598A1
公开(公告)日：2006-11-23
申请号：US11497078
申请日：2006-08-01
申请人： Boaz Eitan
发明人： Boaz Eitan
IPC分类号： G11C16/04
CPC分类号： H01L29/7887 , G11C11/5671 , G11C16/0475 , G11C16/10 , G11C16/14 , G11C16/26 , H01L21/28282 , H01L29/7885 , H01L29/7923
摘要： A non-volatile electrically erasable programmable read only memory (EEPROM) capable of storing two bit of information having a nonconducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the two bit EEPROM device. The nonconducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. A left and a right bit are stored in physically different areas of the charge trapping layer, near left and right regions of the memory cell, respectively. Each bit of the memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and to either the left or the right region while the other region is grounded. Hot electrons are accelerated sufficiently to be injected into the region of the trapping dielectric layer near where the programming voltages were applied to. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate and to either the right or the left region while the other region is grounded. Two bits are able to be programmed and read due to a combination of relatively low gate voltages with reading in the reverse direction. This greatly reduces the potential across the trapped charge region. This permits much shorter programming times by amplifying the effect of the charge trapped in the localized trapping region associated with each of the bits. In addition, both bits of the memory cell can be individually erased by applying suitable erase voltages to the gate and either left or right regions so as to cause electrons to be removed from the corresponding charge trapping region of the nitride layer.

54. 发明申请

US20060152975A1 Multiple use memory chip 有权
公开(公告)号：US20060152975A1
公开(公告)日：2006-07-13
申请号：US11246193
申请日：2005-10-11
申请人： Eduardo Maayan , Boaz Eitan
发明人： Eduardo Maayan , Boaz Eitan
IPC分类号： G11C16/04
CPC分类号： G11C11/005 , G11C16/0475
摘要： A die for a memory array may store Flash and EEPROM bits in at least one Nitride Read Only Memory (NROM) array. Each array may store Flash, EEPROM or both types of bits.

55. 发明申请

US20060018153A1 Operating array cells with matched reference cells 有权
公开(公告)号：US20060018153A1
公开(公告)日：2006-01-26
申请号：US11194394
申请日：2005-08-01
申请人： Eli Lusky , Boaz Eitan , Guy Cohen
发明人： Eli Lusky , Boaz Eitan , Guy Cohen
IPC分类号： G11C16/04
CPC分类号： G11C16/3436 , G11C11/5671 , G11C16/0466 , G11C16/28 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , G11C2211/5634
摘要： A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving an improved sensing accuracy together with improved read disturb immunity.

56. 发明授权

US06917544B2 Multiple use memory chip 有权
公开(公告)号：US06917544B2
公开(公告)日：2005-07-12
申请号：US10191451
申请日：2002-07-10
申请人： Eduardo Maayan , Boaz Eitan
发明人： Eduardo Maayan , Boaz Eitan
IPC分类号： G11C17/00 , G11C11/00 , G11C16/04 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C11/005 , G11C16/0475
摘要： A die for a memory array may store Flash and EEPROM bits in at least one Nitride Read Only Memory (NROM) array. Each array may store Flash, EEPROM or both types of bits.

57. 发明申请

US20050117444A1 Multiple use memory chip 有权
标题翻译：多用内存芯片
公开(公告)号：US20050117444A1
公开(公告)日：2005-06-02
申请号：US11024750
申请日：2004-12-30
申请人： Eduardo Maayan , Boaz Eitan
发明人： Eduardo Maayan , Boaz Eitan
IPC分类号： G11C17/00 , G11C11/00 , G11C16/04 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , G11C8/02
CPC分类号： G11C11/005 , G11C16/0475
摘要： A die for a memory array may store Flash and EEPROM bits in at least one Nitride Read Only Memory (NROM) array. Each array may store Flash, EEPROM or both types of bits.
摘要翻译：用于存储器阵列的管芯可以将闪存和EEPROM位存储在至少一个氮化物只读存储器（NROM）阵列中。每个阵列可以存储闪存，EEPROM或两种类型的位。

58. 发明授权

US06829172B2 Programming of nonvolatile memory cells 有权
标题翻译：非易失性存储单元的编程
公开(公告)号：US06829172B2
公开(公告)日：2004-12-07
申请号：US10155217
申请日：2002-05-28
申请人： Ilan Bloom , Boaz Eitan , Zeev Cohen , David Finzi , Eduardo Maayan
发明人： Ilan Bloom , Boaz Eitan , Zeev Cohen , David Finzi , Eduardo Maayan
IPC分类号： G11C1606
CPC分类号： G11C16/3481 , G11C11/5671 , G11C16/0475 , G11C16/3454 , G11C16/3468
摘要： A method for programming an NROM cell which includes the steps of applying a drain, a source and a gate voltage to the cell and verifying a programmed or a non-programmed state of the cell. If the cell is in the non-programmed state, the method includes the steps of increasing the drain voltage and maintaining the gate voltage at a constant level during at least a part of the step of increasing. The steps of applying, verifying, increasing and maintaining are repeated until the cell reaches the programmed state.
摘要翻译：一种用于对NROM单元进行编程的方法，其包括将漏极，源极和栅极电压施加到所述单元并验证所述单元的编程或非编程状态的步骤。如果电池处于非编程状态，则该方法包括以下步骤：在增加的步骤的至少一部分期间增加漏极电压并将栅极电压保持在恒定水平。重复应用，验证，增加和维护的步骤，直到单元达到编程状态。

59. 发明授权

US06664588B2 NROM cell with self-aligned programming and erasure areas 有权
标题翻译：具有自校正编程和擦除区域的NROM单元
公开(公告)号：US06664588B2
公开(公告)日：2003-12-16
申请号：US09879915
申请日：2001-06-14
申请人： Boaz Eitan
发明人： Boaz Eitan
IPC分类号： H01L29788
CPC分类号： H01L27/11568 , G11C11/5671 , G11C16/0475 , H01L21/26586 , H01L27/115 , H01L29/66825 , H01L29/66833 , H01L29/792 , H01L29/7923
摘要： A memory cell has two diffusion areas in a substrate with a channel therebetween. The memory cell also includes a trapping dielectric layer at least over the channel, a gate at least above the trapping dielectric layer, and an implant in the substrate adapted to provide maximal band-to-band tunneling during erasure of charge stored in the trapping dielectric layer.
摘要翻译：存储单元在衬底中具有两个扩散区域，其间具有通道。存储单元还包括至少在通道上方的捕获电介质层，至少在捕获电介质层上方的栅极，以及衬底中的注入，其适于在擦除存储在捕获电介质中的电荷期间提供最大带 - 带隧穿层。

60. 发明授权

US06643181B2 Method for erasing a memory cell 有权
标题翻译：擦除存储单元的方法
公开(公告)号：US06643181B2
公开(公告)日：2003-11-04
申请号：US09983510
申请日：2001-10-24
申请人： Yair Sofer , Boaz Eitan
发明人： Yair Sofer , Boaz Eitan
IPC分类号： G11C1606
CPC分类号： G11C16/3445 , G11C16/14
摘要： A method for erasing a non-volatile memory cell array, the method including applying an erase pulse to at least one bit of at least one memory cell of the array, erase verifying the at least one bit with a first erase verify level, and if the bit has passed the first erase verify level, applying at least one more erase pulse to the at least one bit.
摘要翻译：一种用于擦除非易失性存储单元阵列的方法，所述方法包括将擦除脉冲施加到所述阵列的至少一个存储单元的至少一个位，以第一擦除验证电平擦除所述至少一个位的验证，以及如果该位已经经过第一擦除验证电平，至少将一个擦除脉冲施加至少一个位。

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