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1. 发明授权

US06829172B2 Programming of nonvolatile memory cells 有权
标题翻译：非易失性存储单元的编程
公开(公告)号：US06829172B2
公开(公告)日：2004-12-07
申请号：US10155217
申请日：2002-05-28
申请人： Ilan Bloom , Boaz Eitan , Zeev Cohen , David Finzi , Eduardo Maayan
发明人： Ilan Bloom , Boaz Eitan , Zeev Cohen , David Finzi , Eduardo Maayan
IPC分类号： G11C1606
CPC分类号： G11C16/3481 , G11C11/5671 , G11C16/0475 , G11C16/3454 , G11C16/3468
摘要： A method for programming an NROM cell which includes the steps of applying a drain, a source and a gate voltage to the cell and verifying a programmed or a non-programmed state of the cell. If the cell is in the non-programmed state, the method includes the steps of increasing the drain voltage and maintaining the gate voltage at a constant level during at least a part of the step of increasing. The steps of applying, verifying, increasing and maintaining are repeated until the cell reaches the programmed state.
摘要翻译：一种用于对NROM单元进行编程的方法，其包括将漏极，源极和栅极电压施加到所述单元并验证所述单元的编程或非编程状态的步骤。如果电池处于非编程状态，则该方法包括以下步骤：在增加的步骤的至少一部分期间增加漏极电压并将栅极电压保持在恒定水平。重复应用，验证，增加和维护的步骤，直到单元达到编程状态。

2. 发明授权

US06396741B1 Programming of nonvolatile memory cells 有权
标题翻译：非易失性存储单元的编程
公开(公告)号：US06396741B1
公开(公告)日：2002-05-28
申请号：US09563923
申请日：2000-05-04
申请人： Ilan Bloom , Boaz Eitan , Zeev Cohen , David Finzi , Eduardo Maayan
发明人： Ilan Bloom , Boaz Eitan , Zeev Cohen , David Finzi , Eduardo Maayan
IPC分类号： G11C1606
CPC分类号： G11C16/3481 , G11C11/5671 , G11C16/0475 , G11C16/3454 , G11C16/3468
摘要： A method for programming an NROM cell which includes the steps of applying a drain, a source and a gate voltage to the cell and verifying a programmed of a non-programmed state of the cell. If the cell is in the non-programmed state, the method includes the steps of increasing the drain voltage and maintaining the gate voltage at a constant level during at least a part of the step of increasing. The steeps of applying, verifying, increasing and maintaining are repeated until the cell reaches the programmed state.
摘要翻译：一种用于对NROM单元进行编程的方法，其包括以下步骤：向所述单元施加漏极，源极和栅极电压，并验证编程的所述单元的非编程状态。如果电池处于非编程状态，则该方法包括以下步骤：在增加的步骤的至少一部分期间增加漏极电压并将栅极电压保持在恒定水平。重复施加，验证，增加和维护的陡峭度，直到单元达到编程状态。

3. 发明授权

US06490204B2 Programming and erasing methods for a reference cell of an NROM array 失效
标题翻译： NROM阵列的参考单元的编程和擦除方法
公开(公告)号：US06490204B2
公开(公告)日：2002-12-03
申请号：US09827596
申请日：2001-04-05
申请人： Ilan Bloom , Eduardo Maayan , Boaz Eitan
发明人： Ilan Bloom , Eduardo Maayan , Boaz Eitan
IPC分类号： G11C1604
CPC分类号： G11C11/5671 , G11C16/0475 , G11C16/10 , G11C16/14 , G11C16/28 , G11C16/3468 , G11C16/3481 , G11C2211/5634
摘要： A method for programming a reference cell of a memory array includes the steps of programming the reference cell with large programming steps until a threshold voltage level of the reference cell is above an interim target level and programming said reference cell with small programming steps until the threshold voltage level is above a final target level.
摘要翻译：用于对存储器阵列的参考单元进行编程的方法包括以下步骤：用大的编程步骤对参考单元进行编程，直到参考单元的阈值电压高于临时目标电平，并以小编程步骤对所述参考单元进行编程，直到阈值电压水平高于最终目标水平。

4. 发明授权

US06614692B2 EEPROM array and method for operation thereof 有权
标题翻译： EEPROM阵列及其操作方法
公开(公告)号：US06614692B2
公开(公告)日：2003-09-02
申请号：US09761818
申请日：2001-01-18
申请人： Ron Eliyahu , Eduardo Maayan , Ilan Bloom , Boaz Eitan
发明人： Ron Eliyahu , Eduardo Maayan , Ilan Bloom , Boaz Eitan
IPC分类号： G11C1604
CPC分类号： G11C16/3427 , G11C11/5671 , G11C16/0475 , G11C16/10 , G11C16/14 , G11C16/3418
摘要： A method for operating an electrically erasable programmable read only memory (EEPROM) array includes providing an array including a multiplicity of memory cells, wherein each memory cell is connected to a word line and to two bit lines, selecting one of the memory cells, and erasing a bit of thief selected memory cell while applying an inhibit word line voltage to a gate of an unselected memory cell. An EEPROM array is also described, the array including a multiplicity of NROM memory cells, wherein each memory cell is connected to a word line and to two bit lines, and wherein each NROM cell is individually erasable and individually programmable without significantly disturbing unselected cells.
摘要翻译：一种用于操作电可擦除可编程只读存储器（EEPROM）阵列的方法，包括提供包括多个存储器单元的阵列，其中每个存储器单元连接到字线和两个位线，选择存储单元之一，以及在对未选择的存储单元的门施加禁止字线电压的同时，擦除所选择的小偷选择的存储单元。还描述了一种EEPROM阵列，该阵列包括多个NROM存储器单元，其中每个存储器单元连接到字线和两个位线，并且其中每个NROM单元可单独地擦除并单独编程，而不显着地干扰未选择的单元。

5. 发明授权

US06292394B1 Method for programming of a semiconductor memory cell 有权
标题翻译：半导体存储单元编程方法
公开(公告)号：US06292394B1
公开(公告)日：2001-09-18
申请号：US09606205
申请日：2000-06-29
申请人： Zeev Cohen , Boaz Eitan , Eduardo Maayan
发明人： Zeev Cohen , Boaz Eitan , Eduardo Maayan
IPC分类号： G11C1604
CPC分类号： G11C16/3445 , G11C16/3436 , G11C16/3459
摘要： A method for programming an array having a multiplicity of memory cells. The method includes, per cell to be programmed, verifying a programmed or non-programmed state of the cell and flagging those of the cells that verify as non-programmed during one of the verify steps after having previously verified as programmed. A programming pulse having a programming level is applied to the non-programmed cells which are not flagged cells. The steps of verifying, flagging and applying are then repeated until all of the cells verify as programmed at least once. Subsequently, a boost pulse having a boost programming level lower than the programming level is applied to the flagged cells.
摘要翻译：一种用于编程具有多个存储器单元的阵列的方法。该方法包括每个待编程的单元，验证单元的编程或非编程状态，并且在先前已经被编程的验证之后，在验证步骤之一期间验证被验证为非编程的单元的那些单元。具有编程电平的编程脉冲被施加到非标记单元的非编程单元。然后重复验证，标记和应用的步骤，直到所有小区至少一次被编程为验证。随后，将具有低于编程电平的升压编程电平的升压脉冲施加到标记的单元。

6. 发明授权

US07400529B2 Non-volatile memory cell and non-volatile memory device using said cell 有权
公开(公告)号：US07400529B2
公开(公告)日：2008-07-15
申请号：US11785285
申请日：2007-04-17
申请人： Boaz Eitan , Eduardo Maayan
发明人： Boaz Eitan , Eduardo Maayan
IPC分类号： G11C16/04
CPC分类号： H01L29/7887 , G11C11/5671 , G11C16/0475 , G11C16/10 , G11C16/14 , G11C16/26 , H01L21/28282 , H01L29/7885 , H01L29/7923
摘要： A non-volatile electrically erasable programmable read only memory (EEPROM) capable of storing two bit of information having a non-conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the two bit EEPROM device. The non-conducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. A left and a right bit are stored in physically different areas of the charge trapping layer, near left and right regions of the memory cell, respectively. Each bit of the memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and to either the left or the right region while the other region is grounded. Hot electrons are accelerated sufficiently to be injected into the region of the trapping dielectric layer near where the programming voltages were applied to. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate and to either the right or the left region while the other region is grounded. Two bits are able to be programmed and read due to a combination of relatively low gate voltages with reading in the reverse direction. This greatly reduces the potential across the trapped charge region. This permits much shorter programming times by amplifying the effect of the charge trapped in the localized trapping region associated with each of the bits. In addition, both bits of the memory cell can be individually erased by applying suitable erase voltages to the gate and either left or right regions so as to cause electrons to be removed from the corresponding charge trapping region of the nitride layer.

7. 发明申请

US20070206415A1 Non-volatile memory cell and non-volatile memory device using said cell 有权
标题翻译：使用所述单元的非易失性存储单元和非易失性存储器件
公开(公告)号：US20070206415A1
公开(公告)日：2007-09-06
申请号：US11785285
申请日：2007-04-17
申请人： Boaz Eitan , Eduardo Maayan
发明人： Boaz Eitan , Eduardo Maayan
IPC分类号： G11C16/04
CPC分类号： H01L29/7887 , G11C11/5671 , G11C16/0475 , G11C16/10 , G11C16/14 , G11C16/26 , H01L21/28282 , H01L29/7885 , H01L29/7923
摘要： A non-volatile electrically erasable programmable read only memory (EEPROM) capable of storing two bit of information having a non-conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the two bit EEPROM device. The non-conducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. A left and a right bit are stored in physically different areas of the charge trapping layer, near left and right regions of the memory cell, respectively. Each bit of the memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and to either the left or the right region while the other region is grounded. Hot electrons are accelerated sufficiently to be injected into the region of the trapping dielectric layer near where the programming voltages were applied to. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate and to either the right or the left region while the other region is grounded. Two bits are able to be programmed and read due to a combination of relatively low gate voltages with reading in the reverse direction. This greatly reduces the potential across the trapped charge region. This permits much shorter programming times by amplifying the effect of the charge trapped in the localized trapping region associated with each of the bits. In addition, both bits of the memory cell can be individually erased by applying suitable erase voltages to the gate and either left or right regions so as to cause electrons to be removed from the corresponding charge trapping region of the nitride layer.
摘要翻译：公开了一种非易失性电可擦除可编程只读存储器（EEPROM），其能够存储夹在作为电绝缘体的两个二氧化硅层之间的具有非导电电荷捕获电介质（例如氮化硅）的两位信息。本发明包括一种编程，读取和擦除两位EEPROM器件的方法。非导电介电层用作电荷捕获介质。导电栅极层放置在上部二氧化硅层上。左和右位分别存储在电荷俘获层的物理上不同的区域中，分别位于存储器单元的左侧和右侧区域附近。使用热电子编程，通过将编程电压施加到栅极以及向左或右区域施加编程电压，而另一区域接地，存储器件的每一位都被编程。热电子被充分加速以注入到施加编程电压附近的捕获介电层的区域中。然而，器件以与其写入的相反方向读取，意味着电压被施加到栅极以及右侧区域或左侧区域，而另一个区域被接地。由于相对低的栅极电压和反向读取的组合，两位能够被编程和读取。这大大降低了被捕获的电荷区域的电位。这允许通过放大捕获在与每个位相关联的局部捕获区域中的电荷的影响来缩短编程时间。此外，可以通过向栅极和左或右区域施加合适的擦除电压来单独擦除存储单元的两个位，以使电子从氮化物层的相应的电荷俘获区域移除。

8. 发明授权

US07257025B2 Method for reading non-volatile memory cells 有权
标题翻译：读取非易失性存储单元的方法
公开(公告)号：US07257025B2
公开(公告)日：2007-08-14
申请号：US11007332
申请日：2004-12-09
申请人： Eduardo Maayan , Guy Cohen , Boaz Eitan
发明人： Eduardo Maayan , Guy Cohen , Boaz Eitan
IPC分类号： G11C16/04
CPC分类号： G11C29/28 , G11C16/04 , G11C16/0475 , G11C29/02 , G11C29/021 , G11C29/026 , G11C29/50 , G11C29/50004
摘要： A method includes changing a read reference level for reading a group of memory cells as a function of changes in a threshold voltage distribution of a different group of memory cells. The changing step includes determining a history read reference level for correct reading of at least one history cell, selecting a memory read reference level according to the first read reference level, and reading non-volatile memory array cells associated with the at least one history cell using the memory read reference level.
摘要翻译：一种方法包括根据不同组存储器单元的阈值电压分布的变化来改变用于读取一组存储器单元的读取参考电平。改变步骤包括确定用于正确读取至少一个历史单元的历史读取参考电平，根据第一读取参考电平选择存储器读取参考电平，以及读取与至少一个历史单元相关联的非易失性存储器阵列单元使用内存读取参考级别。

9. 发明授权

US06633499B1 Method for reducing voltage drops in symmetric array architectures 有权
标题翻译：降低对称阵列结构中电压降的方法
公开(公告)号：US06633499B1
公开(公告)日：2003-10-14
申请号：US09536125
申请日：2000-03-28
申请人： Boaz Eitan , Eduardo Maayan
发明人： Boaz Eitan , Eduardo Maayan
IPC分类号： G11C1604
CPC分类号： G11C7/18 , G11C11/5671 , G11C16/0475 , G11C16/0491 , G11C16/24 , H01L27/115
摘要： A symmetric segmented array has select transistors and column select transistors. At least one of the select and/or column select transistors is a low threshold voltage device. Alternatively, at least one select transistor and/or column select transistor of the array has a channel length shorter than a standard channel length of a process.
摘要翻译：对称分段阵列具有选择晶体管和列选择晶体管。选择和/或列选择晶体管中的至少一个是低阈值电压器件。或者，阵列的至少一个选择晶体管和/或列选择晶体管的沟道长度短于工艺的标准沟道长度。

10. 发明授权

US07864612B2 Reading array cell with matched reference cell 有权
标题翻译：读取具有匹配参考单元格的阵列单元
公开(公告)号：US07864612B2
公开(公告)日：2011-01-04
申请号：US12292654
申请日：2008-11-24
申请人： Eli Lusky , Boaz Eitan , Guy Cohen , Eduardo Maayan
发明人： Eli Lusky , Boaz Eitan , Guy Cohen , Eduardo Maayan
IPC分类号： G11C7/00
CPC分类号： G11C16/3436 , G11C11/5671 , G11C16/0466 , G11C16/28 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , G11C2211/5634
摘要： A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving an improved sensing accuracy together with improved read disturb immunity.
摘要翻译：一种用于读取非易失性存储器（NVM）单元阵列中的存储器单元的位的方法，所述方法包括提供包括要读取的位和至少一个其他不被读取的位的存储单元，并读取位相对于多位参考单元读取，参考单元包括处于第一非地编程状态的第一位和处于第二非地编程状态的第二位。与现有技术相比，本发明可以实现改进的感测精度以及改进的读取干扰抗扰度。

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