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1. 发明授权

US07864612B2 Reading array cell with matched reference cell 有权
标题翻译：读取具有匹配参考单元格的阵列单元
公开(公告)号：US07864612B2
公开(公告)日：2011-01-04
申请号：US12292654
申请日：2008-11-24
申请人： Eli Lusky , Boaz Eitan , Guy Cohen , Eduardo Maayan
发明人： Eli Lusky , Boaz Eitan , Guy Cohen , Eduardo Maayan
IPC分类号： G11C7/00
CPC分类号： G11C16/3436 , G11C11/5671 , G11C16/0466 , G11C16/28 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , G11C2211/5634
摘要： A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving an improved sensing accuracy together with improved read disturb immunity.
摘要翻译：一种用于读取非易失性存储器（NVM）单元阵列中的存储器单元的位的方法，所述方法包括提供包括要读取的位和至少一个其他不被读取的位的存储单元，并读取位相对于多位参考单元读取，参考单元包括处于第一非地编程状态的第一位和处于第二非地编程状态的第二位。与现有技术相比，本发明可以实现改进的感测精度以及改进的读取干扰抗扰度。

2. 发明授权

US07123532B2 Operating array cells with matched reference cells 有权
标题翻译：具有匹配参考单元的操作阵列单元
公开(公告)号：US07123532B2
公开(公告)日：2006-10-17
申请号：US11194394
申请日：2005-08-01
申请人： Eli Lusky , Boaz Eitan , Guy Cohen
发明人： Eli Lusky , Boaz Eitan , Guy Cohen
IPC分类号： G11C7/02
CPC分类号： G11C16/3436 , G11C11/5671 , G11C16/0466 , G11C16/28 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , G11C2211/5634
摘要： A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving an improved sensing accuracy together with improved read disturb immunity.
摘要翻译：一种用于读取非易失性存储器（NVM）单元阵列中的存储器单元的位的方法，所述方法包括提供包括要读取的位和至少一个其他不被读取的位的存储单元，并读取位相对于多位参考单元读取，参考单元包括处于第一非地编程状态的第一位和处于第二非地编程状态的第二位。与现有技术相比，本发明可以实现改进的感测精度以及改进的读取干扰抗扰度。

3. 发明授权

US07457183B2 Operating array cells with matched reference cells 有权
标题翻译：具有匹配参考单元的操作阵列单元
公开(公告)号：US07457183B2
公开(公告)日：2008-11-25
申请号：US11580995
申请日：2006-10-16
申请人： Eli Lusky , Boaz Eitan , Guy Cohen , Eduardo Maayan
发明人： Eli Lusky , Boaz Eitan , Guy Cohen , Eduardo Maayan
IPC分类号： G11C7/02
CPC分类号： G11C16/3436 , G11C11/5671 , G11C16/0466 , G11C16/28 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , G11C2211/5634
摘要： A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving an improved sensing accuracy together with improved read disturb immunity.
摘要翻译：一种用于读取非易失性存储器（NVM）单元阵列中的存储器单元的位的方法，所述方法包括提供包括要读取的位和至少一个其他不被读取的位的存储单元，并读取位相对于多位参考单元读取，参考单元包括处于第一非地编程状态的第一位和处于第二非地编程状态的第二位。与现有技术相比，本发明可以实现改进的感测精度以及改进的读取干扰抗扰度。

4. 发明申请

US20060018153A1 Operating array cells with matched reference cells 有权
公开(公告)号：US20060018153A1
公开(公告)日：2006-01-26
申请号：US11194394
申请日：2005-08-01
申请人： Eli Lusky , Boaz Eitan , Guy Cohen
发明人： Eli Lusky , Boaz Eitan , Guy Cohen
IPC分类号： G11C16/04
CPC分类号： G11C16/3436 , G11C11/5671 , G11C16/0466 , G11C16/28 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , G11C2211/5634
摘要： A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving an improved sensing accuracy together with improved read disturb immunity.

5. 发明申请

US20090231915A1 Reading array cell with matched reference cell 有权
标题翻译：读取具有匹配参考单元格的阵列单元
公开(公告)号：US20090231915A1
公开(公告)日：2009-09-17
申请号：US12292654
申请日：2008-11-24
申请人： Eli Lusky , Boaz Eitan , Guy Cohen , Eduardo Maayan
发明人： Eli Lusky , Boaz Eitan , Guy Cohen , Eduardo Maayan
IPC分类号： G11C16/04 , G11C7/02 , G11C16/06 , H01L21/336
CPC分类号： G11C16/3436 , G11C11/5671 , G11C16/0466 , G11C16/28 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , G11C2211/5634
摘要： A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving an improved sensing accuracy together with improved read disturb immunity.
摘要翻译：一种用于读取非易失性存储器（NVM）单元阵列中的存储器单元的位的方法，所述方法包括提供包括要读取的位和至少一个其他不被读取的位的存储单元，并读取位相对于多位参考单元读取，参考单元包括处于第一非地编程状态的第一位和处于第二非地编程状态的第二位。与现有技术相比，本发明可以实现改进的感测精度以及改进的读取干扰抗扰度。

6. 发明申请

US20070133276A1 Operating array cells with matched reference cells 有权
标题翻译：具有匹配参考单元的操作阵列单元
公开(公告)号：US20070133276A1
公开(公告)日：2007-06-14
申请号：US11580995
申请日：2006-10-16
申请人： Eli Lusky , Boaz Eitan , Guy Cohen
发明人： Eli Lusky , Boaz Eitan , Guy Cohen
IPC分类号： G11C16/04
CPC分类号： G11C16/3436 , G11C11/5671 , G11C16/0466 , G11C16/28 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , G11C2211/5634
摘要： A method for reading a bit of a memory cell in a non-volatile memory (NVM) cell array, the method comprising providing a memory cell comprising a bit to be read and at least one other bit not to be read, and reading the bit to be read with respect to a multi-bit reference cell, the reference cell comprising a first bit at a first non-ground programmed state and a second bit at a second non-ground programmed state. Compared with the prior art, the present invention may enable achieving an improved sensing accuracy together with improved read disturb immunity.
摘要翻译：一种用于读取非易失性存储器（NVM）单元阵列中的存储器单元的位的方法，所述方法包括提供包括待读取的位和至少一个其他不被读取的位的存储单元，以及读取所述位相对于多位参考单元读取，参考单元包括处于第一非地编程状态的第一位和处于第二非地编程状态的第二位。与现有技术相比，本发明可以实现改进的感测精度以及改进的读取干扰抗扰度。

7. 发明授权

US07964459B2 Non-volatile memory structure and method of fabrication 有权
标题翻译：非易失性存储器结构和制造方法
公开(公告)号：US07964459B2
公开(公告)日：2011-06-21
申请号：US12654092
申请日：2009-12-10
申请人： Eli Lusky , Assaf Shappir , Rustom Irani , Boaz Eitan
发明人： Eli Lusky , Assaf Shappir , Rustom Irani , Boaz Eitan
IPC分类号： H01L21/8238
CPC分类号： H01L27/115 , H01L21/28282 , H01L21/32139 , H01L27/11568 , H01L29/66833
摘要： A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least between the increased-width polysilicon columns and depositing oxide at least between the polysilicon columns.
摘要翻译：一种用于创建非易失性存储器阵列的方法包括至少在给定宽度的掩模列之间以及至少穿过覆盖衬底的ONO层之间的衬底中注入口袋植入物，从掩模柱产生增加宽度的多晶硅柱，产生位至少在增宽宽度的多晶硅柱之间并且至少在多晶硅柱之间沉积氧化物的衬底中的线。

8. 发明授权

US07317633B2 Protection of NROM devices from charge damage 有权
标题翻译：保护NROM设备免受充电损坏
公开(公告)号：US07317633B2
公开(公告)日：2008-01-08
申请号：US11175801
申请日：2005-07-05
申请人： Eli Lusky , Ilan Bloom , Assaf Shappir , Boaz Eitan
发明人： Eli Lusky , Ilan Bloom , Assaf Shappir , Boaz Eitan
IPC分类号： G11C16/22 , H01L23/62
CPC分类号： H01L27/105 , G11C16/22 , H01L27/0266 , H01L27/11568
摘要： A method for protecting NROM devices from charge damage during process steps, the method including providing X-decoder structure for word line connections, wherein each word line is connected to a pair of transistors, a PMOS transistor and an NMOS transistor the PMOS transistors sharing a common deep N well and the NMOS transistors connected to a P well, wherein during negative charging, the NMOS transistors shunt leakage current to ground, and during positive charging, the PMOS transistors shunt leakage current to ground, providing an N+ tap connected to the N well and connecting the N+ tap to a positive voltage clamping device, and connecting all the P wells together to a common P+ tap and connecting the P+ tap to a negative voltage clamping device, wherein during process steps, the negative and positive voltage clamping devices direct leakage current to ground.
摘要翻译：一种用于在处理步骤期间保护NROM器件免受电荷损伤的方法，所述方法包括提供用于字线连接的X解码器结构，其中每个字线连接到一对晶体管，PMOS晶体管和NMOS晶体管，PMOS晶体管共享公共深N阱和连接到P阱的NMOS晶体管，其中在负电荷期间，NMOS晶体管将泄漏电流分流到地，并且在正充电期间，PMOS晶体管将泄漏电流分流到地，提供连接到N的N +抽头并且将N +抽头连接到正电压钳位装置，并将所有P阱连接到一个公共P +抽头，并将P +抽头连接到负电压钳位装置，其中在处理步骤期间，负和正电压钳位装置直接漏电流到地。

9. 发明申请

US20060007612A1 Protection of NROM devices from charge damage 有权
标题翻译：保护NROM设备免受充电损坏
公开(公告)号：US20060007612A1
公开(公告)日：2006-01-12
申请号：US11175801
申请日：2005-07-05
申请人： Eli Lusky , Ilan Bloom , Assaf Shappir , Boaz Eitan
发明人： Eli Lusky , Ilan Bloom , Assaf Shappir , Boaz Eitan
IPC分类号： H02H9/00
CPC分类号： H01L27/105 , G11C16/22 , H01L27/0266 , H01L27/11568
摘要： A method for protecting NROM devices from charge damage during process steps, the method including providing X-decoder structure for word line connections, wherein each word line is connected to a pair of transistors, a PMOS transistor T1 and an NMOS transistor T2, the PMOS transistors T1 sharing a common deep N well and the NMOS transistors T2 connected to a P well, wherein during negative charging, the NMOS transistors T2 shunt leakage current to ground, and during positive charging, the PMOS transistors T1 shunt leakage current to ground, providing an N+ tap connected to the N well and connecting the N+ tap to a positive voltage clamping device, and connecting all the P wells together to a common P+ tap and connecting the P+ tap to a negative voltage clamping device, wherein during process steps, the negative and positive voltage clamping devices direct leakage current to ground.
摘要翻译：一种用于在处理步骤期间保护NROM器件免受电荷损伤的方法，所述方法包括提供用于字线连接的X解码器结构，其中每个字线连接到一对晶体管，PMOS晶体管T1和NMOS晶体管T2，PMOS 晶体管T1共享共同的深N阱和连接到P阱的NMOS晶体管T2，其中在负电荷期间，NMOS晶体管T2将漏电流分配到地，并且在正充电期间，PMOS晶体管T1将漏电流分流到地，提供 N +抽头连接到N阱并将N +抽头连接到正电压钳位装置，并将所有P阱连接到一个公共P +抽头，并将P +抽头连接到负电压钳位装置，其中在处理步骤期间，负和正电压钳位器件将漏电流直接接地。

10. 发明授权

US07668017B2 Method of erasing non-volatile memory cells 有权
标题翻译：擦除非易失性存储单元的方法
公开(公告)号：US07668017B2
公开(公告)日：2010-02-23
申请号：US11205716
申请日：2005-08-17
申请人： Eli Lusky , Boaz Eitan
发明人： Eli Lusky , Boaz Eitan
IPC分类号： G11C16/06
CPC分类号： G11C16/16 , G11C16/344 , G11C16/3445
摘要： A method includes determining groups of rows to erase together in order to minimize the margin loss associated with bake after a large number of program and erasure cycles. The method alternatively includes determining groups of rows to erase together to minimize the width of a resultant erase threshold voltage distribution, erasing the groups together, stopping erasure of a group when the group is erase verified and performing the step of erasing on those groups which were not previously erase verified.
摘要翻译：一种方法包括确定要一起擦除的行组，以便在大量程序和擦除循环之后最小化与烘烤相关的裕度损失。该方法或者包括确定一组行以擦除在一起以最小化所得到的擦除阈值电压分布的宽度，将这些组擦除在一起，当组被擦除验证时停止擦除组，并且执行擦除步骤以前没有擦除验证。

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