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1. 发明授权

US07652930B2 Method, circuit and system for erasing one or more non-volatile memory cells 有权
标题翻译：用于擦除一个或多个非易失性存储单元的方法，电路和系统
公开(公告)号：US07652930B2
公开(公告)日：2010-01-26
申请号：US10537857
申请日：2005-04-03
申请人： Assaf Shappir , Ilan Bloom , Boaz Eitan
发明人： Assaf Shappir , Ilan Bloom , Boaz Eitan
IPC分类号： G11C11/34
CPC分类号： G11C16/14 , G11C16/16
摘要： The present invention is a method circuit and system for erasing one or more non-volatile memory (“NVM”) cells in an NVM array. One or more NVM cells of a memory array may be erased using an erase pulse produced by a controller and/or erase pulse source adapted to induce and/or invoke a substantially stable channel current in the one or more NVM cells during an erasure procedure. The voltage profile of an erase pulse may be predefined or the voltage profile of the erase pulse may be dynamically adjusted based on feedback from a current sensor during an erase procedure.
摘要翻译：本发明是用于擦除NVM阵列中的一个或多个非易失性存储器（“NVM”）单元的方法电路和系统。可以使用由控制器产生的擦除脉冲和/或擦除脉冲源来擦除存储器阵列中的一个或多个NVM单元，该擦除脉冲适于在擦除过程期间诱导和/或调用一个或多个NVM单元中的基本上稳定的通道电流。可以预定义擦除脉冲的电压分布，或者可以在擦除过程期间基于来自电流传感器的反馈动态地调整擦除脉冲的电压分布。

2. 发明授权

US07638835B2 Double density NROM with nitride strips (DDNS) 有权
标题翻译：双重密度NROM与氮化物条（DDNS）
公开(公告)号：US07638835B2
公开(公告)日：2009-12-29
申请号：US11646430
申请日：2006-12-28
申请人： Rustom Irani , Boaz Eitan , Ilan Bloom , Assaf Shappir
发明人： Rustom Irani , Boaz Eitan , Ilan Bloom , Assaf Shappir
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/105 , H01L27/11573
摘要： An NVM cell such as an NROM cell is formed using a portion of one ONO stack and an adjacent portion of a neighboring NROM stack. A gate structure is formed between (and atop) the two ONO portions, or “strips” (or “stripes”). This provides having two physically separated charge storage regions (nitride “strips”, or “stripes”) in each memory cell.
摘要翻译：使用一个ONO堆栈的一部分和相邻NROM堆栈的相邻部分来形成诸如NROM单元的NVM单元。在（和顶部）两个ONO部分或“条带”（或“条纹”）之间形成栅极结构。这提供了在每个存储单元中具有两个物理分离的电荷存储区域（氮化物“条带”或“条纹”）。

3. 发明授权

US06337502B1 Method and circuit for minimizing the charging effect during manufacture of semiconductor devices 有权
标题翻译：用于在半导体器件制造期间最小化充电效应的方法和电路
公开(公告)号：US06337502B1
公开(公告)日：2002-01-08
申请号：US09336666
申请日：1999-06-18
申请人： Boaz Eitan , Ilan Bloom
发明人： Boaz Eitan , Ilan Bloom
IPC分类号： H01L2362
CPC分类号： H01L27/0266 , H01L21/3065 , H01L21/31116 , H01L27/0251
摘要： A protection device which is active during the manufacturing process of a semiconductor chip includes a protection transistor and an antenna. The protection transistor is connected between a metal line having devices to be protected electrically connected thereto and a ground supply, where the metal line is connected to devices to be protected. The antenna is formed of the same metal layer as the metal line and controls the operation of the protection transistor during the manufacturing process. The antenna is connected to a gate of the protection transistor. Optionally, there is a metal ring around the antenna which is connected to a drain of the protection transistor via the same metal layer as the metal line. During normal operation of the chip, the protection transistor is either active for other purposes or is turned off. Turning off is provided either by a line formed of a second metal layer that is connected between the antenna and ground, or by a reversed biased diode and a parallel capacitor that are connected between the gate of the protection transistor and ground. The present invention includes the method of manufacturing the protection device.
摘要翻译：在半导体芯片的制造过程中有效的保护装置包括保护晶体管和天线。保护晶体管连接在具有被保护电气连接的器件的金属线和接地电源之间，其中金属线连接到待保护的器件。天线由与金属线相同的金属层形成，并且在制造过程中控制保护晶体管的操作。天线连接到保护晶体管的栅极。可选地，在天线周围有金属环，其通过与金属线相同的金属层连接到保护晶体管的漏极。在芯片的正常操作期间，保护晶体管对于其它目的而言是活动的或被关闭。通过由连接在天线和地之间的第二金属层形成的线或由连接在保护晶体管的栅极和地之间的反向偏置二极管和并联电容器来提供关断。本发明包括制造保护装置的方法。

4. 发明授权

US07317633B2 Protection of NROM devices from charge damage 有权
标题翻译：保护NROM设备免受充电损坏
公开(公告)号：US07317633B2
公开(公告)日：2008-01-08
申请号：US11175801
申请日：2005-07-05
申请人： Eli Lusky , Ilan Bloom , Assaf Shappir , Boaz Eitan
发明人： Eli Lusky , Ilan Bloom , Assaf Shappir , Boaz Eitan
IPC分类号： G11C16/22 , H01L23/62
CPC分类号： H01L27/105 , G11C16/22 , H01L27/0266 , H01L27/11568
摘要： A method for protecting NROM devices from charge damage during process steps, the method including providing X-decoder structure for word line connections, wherein each word line is connected to a pair of transistors, a PMOS transistor and an NMOS transistor the PMOS transistors sharing a common deep N well and the NMOS transistors connected to a P well, wherein during negative charging, the NMOS transistors shunt leakage current to ground, and during positive charging, the PMOS transistors shunt leakage current to ground, providing an N+ tap connected to the N well and connecting the N+ tap to a positive voltage clamping device, and connecting all the P wells together to a common P+ tap and connecting the P+ tap to a negative voltage clamping device, wherein during process steps, the negative and positive voltage clamping devices direct leakage current to ground.
摘要翻译：一种用于在处理步骤期间保护NROM器件免受电荷损伤的方法，所述方法包括提供用于字线连接的X解码器结构，其中每个字线连接到一对晶体管，PMOS晶体管和NMOS晶体管，PMOS晶体管共享公共深N阱和连接到P阱的NMOS晶体管，其中在负电荷期间，NMOS晶体管将泄漏电流分流到地，并且在正充电期间，PMOS晶体管将泄漏电流分流到地，提供连接到N的N +抽头并且将N +抽头连接到正电压钳位装置，并将所有P阱连接到一个公共P +抽头，并将P +抽头连接到负电压钳位装置，其中在处理步骤期间，负和正电压钳位装置直接漏电流到地。

5. 发明申请

US20070200180A1 Double density NROM with nitride strips (DDNS) 有权
标题翻译：双重密度NROM与氮化物条（DDNS）
公开(公告)号：US20070200180A1
公开(公告)日：2007-08-30
申请号：US11646430
申请日：2006-12-28
申请人： Rustom Irani , Boaz Eitan , Ilan Bloom , Assaf Shappir
发明人： Rustom Irani , Boaz Eitan , Ilan Bloom , Assaf Shappir
IPC分类号： H01L29/76
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/105 , H01L27/11573
摘要： An NVM cell such as an NROM cell is formed using a portion of one ONO stack and an adjacent portion of a neighboring NROM stack. A gate structure is formed between (and atop) the two ONO portions, or “strips” (or “stripes”). This provides having two physically separated charge storage regions (nitride “strips”, or “stripes”) in each memory cell.
摘要翻译：使用一个ONO堆栈的一部分和相邻NROM堆栈的相邻部分来形成诸如NROM单元的NVM单元。在（和顶部）两个ONO部分或“条带”（或“条纹”）之间形成栅极结构。这提供了在每个存储单元中具有两个物理分离的电荷存储区域（氮化物“条带”或“条纹”）。

6. 发明申请

US20070032016A1 Protective layer in memory device and method therefor 审中-公开
标题翻译：存储器件中的保护层及其方法
公开(公告)号：US20070032016A1
公开(公告)日：2007-02-08
申请号：US11490483
申请日：2006-07-20
申请人： Ilan Bloom , Boaz Eitan
发明人： Ilan Bloom , Boaz Eitan
IPC分类号： H01L21/336
CPC分类号： H01L21/28194 , H01L21/28202 , H01L27/115 , H01L27/11568 , H01L29/513 , H01L29/518 , H01L29/66833 , H01L29/792 , Y10S438/954
摘要： A method protecting a non-volatile memory device, the method including forming a non-volatile memory device including a polycide structure formed over a non-conducting charge trapping layer, and forming a protective layer over at least a portion of the polycide structure, die protective layer being adapted to absorb electromagnetic wave energy having a wavelength shorter than visible light. A device constructed in accordance with the method is also disclosed.
摘要翻译：一种保护非易失性存储器件的方法，所述方法包括形成非易失性存储器件，该非易失性存储器件包括在非导电电荷俘获层上形成的多晶硅结构，以及在该多晶硅结构的至少一部分上形成保护层保护层适于吸收波长短于可见光的电磁波能量。还公开了根据该方法构造的装置。

7. 发明申请

US20060007612A1 Protection of NROM devices from charge damage 有权
标题翻译：保护NROM设备免受充电损坏
公开(公告)号：US20060007612A1
公开(公告)日：2006-01-12
申请号：US11175801
申请日：2005-07-05
申请人： Eli Lusky , Ilan Bloom , Assaf Shappir , Boaz Eitan
发明人： Eli Lusky , Ilan Bloom , Assaf Shappir , Boaz Eitan
IPC分类号： H02H9/00
CPC分类号： H01L27/105 , G11C16/22 , H01L27/0266 , H01L27/11568
摘要： A method for protecting NROM devices from charge damage during process steps, the method including providing X-decoder structure for word line connections, wherein each word line is connected to a pair of transistors, a PMOS transistor T1 and an NMOS transistor T2, the PMOS transistors T1 sharing a common deep N well and the NMOS transistors T2 connected to a P well, wherein during negative charging, the NMOS transistors T2 shunt leakage current to ground, and during positive charging, the PMOS transistors T1 shunt leakage current to ground, providing an N+ tap connected to the N well and connecting the N+ tap to a positive voltage clamping device, and connecting all the P wells together to a common P+ tap and connecting the P+ tap to a negative voltage clamping device, wherein during process steps, the negative and positive voltage clamping devices direct leakage current to ground.
摘要翻译：一种用于在处理步骤期间保护NROM器件免受电荷损伤的方法，所述方法包括提供用于字线连接的X解码器结构，其中每个字线连接到一对晶体管，PMOS晶体管T1和NMOS晶体管T2，PMOS 晶体管T1共享共同的深N阱和连接到P阱的NMOS晶体管T2，其中在负电荷期间，NMOS晶体管T2将漏电流分配到地，并且在正充电期间，PMOS晶体管T1将漏电流分流到地，提供 N +抽头连接到N阱并将N +抽头连接到正电压钳位装置，并将所有P阱连接到一个公共P +抽头，并将P +抽头连接到负电压钳位装置，其中在处理步骤期间，负和正电压钳位器件将漏电流直接接地。

8. 发明授权

US06829172B2 Programming of nonvolatile memory cells 有权
标题翻译：非易失性存储单元的编程
公开(公告)号：US06829172B2
公开(公告)日：2004-12-07
申请号：US10155217
申请日：2002-05-28
申请人： Ilan Bloom , Boaz Eitan , Zeev Cohen , David Finzi , Eduardo Maayan
发明人： Ilan Bloom , Boaz Eitan , Zeev Cohen , David Finzi , Eduardo Maayan
IPC分类号： G11C1606
CPC分类号： G11C16/3481 , G11C11/5671 , G11C16/0475 , G11C16/3454 , G11C16/3468
摘要： A method for programming an NROM cell which includes the steps of applying a drain, a source and a gate voltage to the cell and verifying a programmed or a non-programmed state of the cell. If the cell is in the non-programmed state, the method includes the steps of increasing the drain voltage and maintaining the gate voltage at a constant level during at least a part of the step of increasing. The steps of applying, verifying, increasing and maintaining are repeated until the cell reaches the programmed state.
摘要翻译：一种用于对NROM单元进行编程的方法，其包括将漏极，源极和栅极电压施加到所述单元并验证所述单元的编程或非编程状态的步骤。如果电池处于非编程状态，则该方法包括以下步骤：在增加的步骤的至少一部分期间增加漏极电压并将栅极电压保持在恒定水平。重复应用，验证，增加和维护的步骤，直到单元达到编程状态。

9. 发明授权

US06396741B1 Programming of nonvolatile memory cells 有权
标题翻译：非易失性存储单元的编程
公开(公告)号：US06396741B1
公开(公告)日：2002-05-28
申请号：US09563923
申请日：2000-05-04
申请人： Ilan Bloom , Boaz Eitan , Zeev Cohen , David Finzi , Eduardo Maayan
发明人： Ilan Bloom , Boaz Eitan , Zeev Cohen , David Finzi , Eduardo Maayan
IPC分类号： G11C1606
CPC分类号： G11C16/3481 , G11C11/5671 , G11C16/0475 , G11C16/3454 , G11C16/3468
摘要： A method for programming an NROM cell which includes the steps of applying a drain, a source and a gate voltage to the cell and verifying a programmed of a non-programmed state of the cell. If the cell is in the non-programmed state, the method includes the steps of increasing the drain voltage and maintaining the gate voltage at a constant level during at least a part of the step of increasing. The steeps of applying, verifying, increasing and maintaining are repeated until the cell reaches the programmed state.
摘要翻译：一种用于对NROM单元进行编程的方法，其包括以下步骤：向所述单元施加漏极，源极和栅极电压，并验证编程的所述单元的非编程状态。如果电池处于非编程状态，则该方法包括以下步骤：在增加的步骤的至少一部分期间增加漏极电压并将栅极电压保持在恒定水平。重复施加，验证，增加和维护的陡峭度，直到单元达到编程状态。

10. 发明授权

US09490261B2 Minimizing disturbs in dense non volatile memory arrays 有权
标题翻译：最小化密集非易失性存储器阵列中的干扰
公开(公告)号：US09490261B2
公开(公告)日：2016-11-08
申请号：US13317460
申请日：2011-10-19
申请人： Ilan Bloom , Amichai Givant , Boaz Eitan
发明人： Ilan Bloom , Amichai Givant , Boaz Eitan
IPC分类号： H01L21/8238 , H01L21/8234 , H01L21/3205 , H01L27/115 , H01L29/66 , H01L29/792
CPC分类号： H01L27/11568 , H01L29/66833 , H01L29/792
摘要： A nitride read only memory (NROM) array includes a silicon substrate having trenches therein, a plurality of polysilicon bit lines deposited in the trenches and connecting columns of memory cells, a layer of (oxide nitride oxide) ONO at least within the memory cells and a plurality of polysilicon word lines to connect rows of the memory cells. An NROM array with a virtual ground architecture includes a plurality of bit lines to connect columns of NROM memory cells, a layer of ONO at least within the memory cells and a plurality of word lines to connect rows of the NROM memory cells, wherein a distance between word lines is at least twice the width of the word lines.
摘要翻译：氮化物只读存储器（NROM）阵列包括其中具有沟槽的硅衬底，沉积在存储器单元的沟槽和连接列中的多个多晶硅位线，至少在存储器单元内的（氧化物氧化物）ONO层，以及多条多晶硅字线连接存储单元的行。具有虚拟接地架构的NROM阵列包括多个位线，用于连接NROM存储器单元的列，至少在存储单元内的ONO层，以及多个字线，用于连接NROM存储单元的行，其中距离字线之间的距离至少是字线宽度的两倍。

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