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51. 发明授权

US07239213B2 Reduced cross-talk signaling circuit and method 失效
公开(公告)号：US07239213B2
公开(公告)日：2007-07-03
申请号：US11209549
申请日：2005-08-23
申请人： Daniel M. Dreps , Anand Haridass , Bao G. Truong , Joel D. Ziegelbein
发明人： Daniel M. Dreps , Anand Haridass , Bao G. Truong , Joel D. Ziegelbein
IPC分类号： H01P1/00
CPC分类号： H04L25/0272 , H04B3/32
摘要： Signaling between two or more ICs use a signaling scheme wherein a reference signal is generated at the driver side and the receiver side. The driver side reference signal is coupled to the receiver side reference signal with a transmission line channel forming a reference channel. Data signal channels are paired with a reference channel between each two adjacent data channels. Adjacent pairs of data signal channels are each separated with an empty wiring channel. The paired data signals are received in one input of a differential receiver. The reference signal of the reference channel between the two paired data channels is coupled to the other input of the two differential receivers. Coupling from the paired data channels to the reference channel appears a common mode noise and is rejected by the differential receivers. The number of channels is reduced from a full differential signaling scheme.

52. 发明申请

US20060215769A1 Differential transmitter circuit 有权
公开(公告)号：US20060215769A1
公开(公告)日：2006-09-28
申请号：US11086718
申请日：2005-03-22
申请人： Anand Haridass , Bao Truong , Joel Ziegelbein
发明人： Anand Haridass , Bao Truong , Joel Ziegelbein
IPC分类号： H04L25/00
CPC分类号： H04L25/0274 , H03F3/45197 , H03F2200/543 , H03F2203/45488
摘要： A driver circuit is configured as a frequency compensated differential amplifier having one input coupled to a first data signal and a second input coupled to a second data signal. Each stage of the differential amplifier is biased with a current source. The driver circuit generates a first output signal coupled to the input of a first transmission line and a second output signal coupled to the input of a second transmission line. The first and second output signals are generated as the difference between the first and second data signals amplified by a compensated gain. A compensation network that attenuates the low frequency components of the input signals relative to the high frequency components is coupled between current sources biasing the differential amplifier. The outputs of the first and second transmission lines are coupled to the inputs of a differential receiver that may or may not be frequency compensated.

53. 发明授权

US06951002B2 Design techniques for analyzing integrated circuit device characteristics 失效
标题翻译：分析集成电路器件特性的设计技术
公开(公告)号：US06951002B2
公开(公告)日：2005-09-27
申请号：US10455164
申请日：2003-06-05
申请人： Joachim Gerhard Clabes , Anand Haridass , Michael F. Wang
发明人： Joachim Gerhard Clabes , Anand Haridass , Michael F. Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5068
摘要： An improved method and system for integrated circuit device physical design and layout. The physical layout of the integrated circuit device is optimally stored in a database to provide improved analysis capabilities of the integrated circuit device's characteristics. The method and system evaluates local interactions between functional blocks and decoupling cells on a given floor plan of a chip using this optimized database in order to reduce memory and processor utilization. Local noise is projected by using dI/dt and capacitance estimates. Areas of highest noise concern are identified, and floor plan mitigation actions are taken by tuning the placement of neighboring decoupling cells and their properties. Upon several iterative cycles, a near optimal solution for a given floor plan of the total chip is achieved.
摘要翻译：一种改进的集成电路设备物理设计和布局的方法和系统。将集成电路器件的物理布局最佳地存储在数据库中，以提供集成电路器件特性的改进的分析能力。该方法和系统使用此优化数据库评估芯片给定平面图上的功能块和去耦单元之间的本地交互，以减少内存和处理器利用率。通过使用dI / dt和电容估计来预测局部噪声。识别出最高噪声的区域，并通过调整相邻去耦单元的布局及其属性来采取平面图缓解措施。在几个迭代循环中，实现了总芯片给定平面图的近似最优解。

54. 发明申请

US20130103354A1 DETECTING CROSS-TALK ON PROCESSOR LINKS 有权
标题翻译：检测处理器链接的交叉口
公开(公告)号：US20130103354A1
公开(公告)日：2013-04-25
申请号：US13281097
申请日：2011-10-25
申请人： Robert W. Berry, JR. , Anand Haridass , Prasanna Jayaraman
发明人： Robert W. Berry, JR. , Anand Haridass , Prasanna Jayaraman
IPC分类号： G06F11/30
CPC分类号： G06F9/30145 , G06F9/30 , G06F11/3409 , G06F11/3414 , G06F11/3466 , G06F11/349
摘要： A first of a plurality of data lanes of a first of a plurality of processor links is determined to have a weakest of base performance measurements for the plurality of data lanes. A switching data pattern is transmitted via a first set of the remainder processor links and a quiet data pattern is transmitted via a second set of the remainder processor links. If performance of the first data lane increases vis-à-vis the corresponding base performance measurement, the first set of remainder processor links is eliminated from the remainder processor links. If performance of the first data lanes decreases vis-à-vis the corresponding base performance measurement, the second set of remainder processor links is eliminated from the remainder processor links. The above operations are repeatedly executed until an aggressor processor link that is determined to decrease performance of the first of the plurality of data lanes is identified.
摘要翻译：多个处理器链路中的第一个处理器链路的多个数据通路中的第一个被确定为对于多个数据通道具有最弱的基本性能测量。经由剩余处理器链路的第一组发送切换数据模式，并且经由剩余处理器链路的第二组发送安静数据模式。如果第一数据线的性能相对于相应的基本性能测量增加，则剩余处理器链路的第一组从剩余处理器链路中消除。如果第一数据通道的性能相对于相应的基本性能测量值降低，则剩余处理器链路的第二组从剩余处理器链路中消除。重复执行上述操作，直到识别出被确定为降低多个数据通道中的第一个数据通道的性能的攻击者处理器链路。

55. 发明申请

US20110031627A1 Reducing Crosstalk In The Design Of Module Nets 有权
标题翻译：在模块网的设计中减少串扰
公开(公告)号：US20110031627A1
公开(公告)日：2011-02-10
申请号：US12537767
申请日：2009-08-07
申请人： Dulce M. Altabella Cabrera , Sungjun Chun , Anand Haridass , Tingdong Zhou
发明人： Dulce M. Altabella Cabrera , Sungjun Chun , Anand Haridass , Tingdong Zhou
IPC分类号： G06F17/50 , H01L23/52
CPC分类号： H01L23/5386 , G06F17/5077 , G06F2217/82 , H01L23/5222 , H01L23/552 , H01L25/0655 , H01L2224/16227 , H01L2224/16235 , H01L2924/15192
摘要： A method, a system and a computer program product for reducing coupling noise in low loss on-module wires used for connecting module components in electrical circuits/devices. During the design stage, an Enhanced Crosstalk Reduction (ECR) utility identifies interconnect wires as driven/aggressor traces or receiver traces. The ECR utility substantially avoids forward crosstalk in a victim trace by specially arranging driver traces adjacent to the receiver victim trace in order to provide a lower level and saturated level of backward crosstalk. In particular, the ECR utility provided a configuration of wire/trace layers based on one or more of: (a) the crosstalk impact of a trace when positioned in a particular location; (b) the crosstalk impact of the trace upon remaining components based on placement in the particular location; and (c) system component specifications. In addition, the ECR utility reduces crosstalk by providing a configuration of receiver wires and transmitter wires without the use of isolation layers.
摘要翻译：一种用于减少用于连接电路/设备中的模块部件的低损耗模块电线中的耦合噪声的方法，系统和计算机程序产品。在设计阶段，增强型串扰降低（ECR）实用程序将互连导线识别为驱动/侵入轨迹或接收器迹线。 ECR实用程序通过专门布置与接收器受害者跟踪相邻的驱动器迹线，基本上避免了受害者跟踪中的前向串扰，以便提供较低级别和饱和的后向串扰水平。特别地，ECR实用程序基于以下中的一个或多个提供了线/迹线层的配置：（a）当定位在特定位置时迹线的串扰影响; （b）基于在特定位置的放置，迹线对剩余部件的串扰影响; 和（c）系统组件规格。此外，ECR实用程序通过提供接收器线和发射器线的配置来减少串扰，而不使用隔离层。

56. 发明授权

US07835453B2 Differential transmitter circuit 失效
标题翻译：差分发射电路
公开(公告)号：US07835453B2
公开(公告)日：2010-11-16
申请号：US12350120
申请日：2009-01-07
申请人： Anand Haridass , Bao G. Truong , Joel D. Ziegelbein
发明人： Anand Haridass , Bao G. Truong , Joel D. Ziegelbein
IPC分类号： H04B3/00
CPC分类号： H04L25/0274 , H03F3/45197 , H03F2200/543 , H03F2203/45488
摘要： A driver circuit is configured as a frequency compensated differential amplifier having one input coupled to a first data signal and a second input coupled to a second data signal. Each stage of the differential amplifier is biased with a current source. The driver circuit generates a first output signal coupled to the input of a first transmission line and a second output signal coupled to the input of a second transmission line. The first and second output signals are generated as the difference between the first and second data signals amplified by a compensated gain. A compensation network that attenuates the low frequency components of the input signals relative to the high frequency components is coupled between current sources biasing the differential amplifier. The outputs of the first and second transmission lines are coupled to the inputs of a differential receiver that may or may not be frequency compensated.
摘要翻译：驱动器电路被配置为具有耦合到第一数据信号的一个输入和耦合到第二数据信号的第二输入的频率补偿差分放大器。差分放大器的每个级都用电流源偏置。驱动器电路产生耦合到第一传输线的输入的第一输出信号和耦合到第二传输线的输入的第二输出信号。第一和第二输出信号被产生为由补偿增益放大的第一和第二数据信号之间的差。相对于高频分量衰减输入信号的低频分量的补偿网络耦合在偏置差分放大器的电流源之间。第一和第二传输线的输出耦合到差分接收机的输入端，该差分接收机可以被频率补偿也可以不被频率补偿。

57. 发明授权

US07671273B2 Method and apparatus for facilitating signal transmission using differential transmission lines 失效
标题翻译：使用差分传输线促进信号传输的方法和装置
公开(公告)号：US07671273B2
公开(公告)日：2010-03-02
申请号：US11869130
申请日：2007-10-09
申请人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm Brian O'Reilly , Roger Donell Weekly
发明人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm Brian O'Reilly , Roger Donell Weekly
IPC分类号： H01B11/02
CPC分类号： H01B11/04
摘要： The illustrative embodiments described herein provide an apparatus and method for facilitating signal transmission using differential transmission lines. The apparatus includes a first differential transmission line. The first differential transmission line includes a first plurality of conductors. The first plurality of conductors includes a set of conductors. The apparatus also includes a second differential transmission line. The second differential transmission line includes a second plurality of conductors. The second plurality of conductors includes a first conductor and a second conductor. A first noise produced by the first conductor on the set of conductors is balanced by a second noise produced by the second conductor on the set of conductors. The first differential transmission line and the second differential transmission line facilitate signal transmission.
摘要翻译：本文描述的说明性实施例提供了一种用于使用差分传输线促进信号传输的装置和方法。该装置包括第一差分传输线。第一差分传输线包括第一多个导体。第一多个导体包括一组导体。该装置还包括第二差分传输线。第二差分传输线包括第二多个导体。第二多个导体包括第一导体和第二导体。由导体组上的第一导体产生的第一噪声由在该组导体上的第二导体产生的第二噪声平衡。第一差分传输线和第二差分传输线便于信号传输。

58. 发明申请

US20090164962A1 Method of Reducing Crosstalk Induced Noise in Circuitry Designs 有权
标题翻译：减少电路设计中串扰感应噪声的方法
公开(公告)号：US20090164962A1
公开(公告)日：2009-06-25
申请号：US11961440
申请日：2007-12-20
申请人： Sungjun Chun , Anand Haridass , Jesus Montanez , Xiaomin Shen
发明人： Sungjun Chun , Anand Haridass , Jesus Montanez , Xiaomin Shen
IPC分类号： G06F9/455
CPC分类号： G06F17/5036 , G06F17/5077
摘要： A method of reducing crosstalk induced noise in a physical circuit wiring design constructs a spatial vector for each interconnect wire segment in the physical circuit wiring design. The method compares the spatial vectors of said physical circuit wiring design and identifies any of the spatial vectors that are parallel to each other and have opposite directions. The method may identify all drivers and receivers in the physical circuit wiring design, and trace each interconnect line, starting with its driver, to determine a routed length from the driver to each segment break point of the interconnect line. The method may construct the spatial vector by defining an origin in the physical circuit wiring design. The method determines a starting point and an ending point of the spatial vector with respect to the origin. The starting point of the spatial vector is the break point of the interconnect wire segment closer to the driver. The ending point of the spatial vector is the break point of the interconnect wire segment farther from the driver. The method may define a Cartesian coordinate system with respect to the origin. The Cartesian coordinate system may be orthogonal with the interconnect wire segments of the physical circuit wiring design. The method may define one or more geometry windows in the physical circuit wiring design and compare the spatial vectors in each geometry window.
摘要翻译：在物理电路布线设计中减少串扰引起的噪声的方法在物理电路布线设计中为每个互连线段构造空间矢量。该方法比较了所述物理电路布线设计的空间矢量，并且识别彼此平行且具有相反方向的任何空间矢量。该方法可以识别物理电路布线设计中的所有驱动器和接收器，并且从其驱动器开始追踪每个互连线，以确定从驱动器到互连线的每个段断点的路由长度。该方法可以通过在物理电路布线设计中定义原点来构造空间矢量。该方法确定相对于原点的空间矢量的起始点和终点。空间矢量的起始点是互连线段靠近驾驶员的断点。空间矢量的终点是互连线段远离驾驶员的断点。该方法可以相对于原点定义笛卡尔坐标系。笛卡尔坐标系可以与物理电路布线设计的互连线段正交。该方法可以在物理电路布线设计中定义一个或多个几何窗口并比较每个几何窗口中的空间矢量。

59. 发明申请

US20090113107A1 DIFFERENTIAL TRANSMITTER CIRCUIT 失效
标题翻译：差分变送器电路
公开(公告)号：US20090113107A1
公开(公告)日：2009-04-30
申请号：US12350120
申请日：2009-01-07
申请人： Anand Haridass , Bao G. Truong , Joel D. Ziegelbein
发明人： Anand Haridass , Bao G. Truong , Joel D. Ziegelbein
IPC分类号： G06F13/40 , H04B3/00
CPC分类号： H04L25/0274 , H03F3/45197 , H03F2200/543 , H03F2203/45488
摘要： A driver circuit is configured as a frequency compensated differential amplifier having one input coupled to a first data signal and a second input coupled to a second data signal. Each stage of the differential amplifier is biased with a current source. The driver circuit generates a first output signal coupled to the input of a first transmission line and a second output signal coupled to the input of a second transmission line. The first and second output signals are generated as the difference between the first and second data signals amplified by a compensated gain. A compensation network that attenuates the low frequency components of the input signals relative to the high frequency components is coupled between current sources biasing the differential amplifier. The outputs of the first and second transmission lines are coupled to the inputs of a differential receiver that may or may not be frequency compensated.
摘要翻译：驱动器电路被配置为具有耦合到第一数据信号的一个输入和耦合到第二数据信号的第二输入的频率补偿差分放大器。差分放大器的每个级都用电流源偏置。驱动器电路产生耦合到第一传输线的输入的第一输出信号和耦合到第二传输线的输入的第二输出信号。第一和第二输出信号被产生为由补偿增益放大的第一和第二数据信号之间的差。相对于高频分量衰减输入信号的低频分量的补偿网络耦合在偏置差分放大器的电流源之间。第一和第二传输线的输出耦合到差分接收机的输入端，该差分接收机可以被频率补偿也可以不被频率补偿。

60. 发明授权

US07477068B2 System for reducing cross-talk induced source synchronous bus clock jitter 有权
标题翻译：减少串扰引起的源同步总线时钟抖动的系统
公开(公告)号：US07477068B2
公开(公告)日：2009-01-13
申请号：US12058689
申请日：2008-03-29
申请人： Bao G. Truong , Daniel Mark Dreps , Anand Haridass , John C. Schiff , Joel D. Ziegelbein
发明人： Bao G. Truong , Daniel Mark Dreps , Anand Haridass , John C. Schiff , Joel D. Ziegelbein
IPC分类号： H03K17/16
CPC分类号： H04L25/45
摘要： A first clock signal of frequency F is used to couple data to an off-chip driver (OCD) using a master/slave flip flop (FF), wherein the master latch is clocked with the first clock signal and the slave latch is clocked with the complement of the first clock signal. A second clock signal of frequency F/2 is generated from the first clock signal. The second clock signal is shifted a time equal to substantially one-half the cycle of the first clock signal. In one embodiment, the second clock is shifted using a delay line circuit. In another embodiment, the second clock is shifted using a master/slave FF, wherein the master latch is clocked with the complement of the first clock signal and the slave latch is clocked with the first clock signal. The logic state transitions of the data between edges of the propagating clock thereby reducing coupling to the clock transitions and thus reducing edge jitter.
摘要翻译：使用频率F的第一时钟信号用于使用主/从触发器（FF）将数据耦合到片外驱动器（OCD），其中主锁存器由第一时钟信号计时，从锁存器以第一个时钟信号的补码。从第一时钟信号产生频率为F / 2的第二时钟信号。第二时钟信号被移位等于第一时钟信号的周期的大致一半的时间。在一个实施例中，使用延迟线电路来移位第二时钟。在另一个实施例中，使用主/从FF来移位第二时钟，其中主锁存器用第一时钟信号的补码进行计时，从锁存器用第一时钟信号计时。传播时钟的边缘之间的数据的逻辑状态转换，从而减少与时钟转换的耦合，从而减少边缘抖动。

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