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1. 发明授权

US07239213B2 Reduced cross-talk signaling circuit and method 失效
公开(公告)号：US07239213B2
公开(公告)日：2007-07-03
申请号：US11209549
申请日：2005-08-23
申请人： Daniel M. Dreps , Anand Haridass , Bao G. Truong , Joel D. Ziegelbein
发明人： Daniel M. Dreps , Anand Haridass , Bao G. Truong , Joel D. Ziegelbein
IPC分类号： H01P1/00
CPC分类号： H04L25/0272 , H04B3/32
摘要： Signaling between two or more ICs use a signaling scheme wherein a reference signal is generated at the driver side and the receiver side. The driver side reference signal is coupled to the receiver side reference signal with a transmission line channel forming a reference channel. Data signal channels are paired with a reference channel between each two adjacent data channels. Adjacent pairs of data signal channels are each separated with an empty wiring channel. The paired data signals are received in one input of a differential receiver. The reference signal of the reference channel between the two paired data channels is coupled to the other input of the two differential receivers. Coupling from the paired data channels to the reference channel appears a common mode noise and is rejected by the differential receivers. The number of channels is reduced from a full differential signaling scheme.

2. 发明授权

US07208972B2 Circuit for generating a tracking reference voltage 失效
标题翻译：用于产生跟踪参考电压的电路
公开(公告)号：US07208972B2
公开(公告)日：2007-04-24
申请号：US10845568
申请日：2004-05-13
申请人： Daniel M. Dreps , Anand Haridass , Bao G. Truong
发明人： Daniel M. Dreps , Anand Haridass , Bao G. Truong
IPC分类号： H03K17/16
CPC分类号： H04L25/061 , H04L25/45
摘要： Two or more integrated circuit (IC) chips are separated by a significant distance relative to their communication frequency such that pseudo-differential signaling is used to improve signal detection. A derived reference voltage is generated that tracks the variations of the driver and receiver side power supply variations that normally reduce noise margins. The derived reference voltage is filtered to reduce high frequency response and coupled as the reference to differential receivers used to detect the logic levels of the communication signals.
摘要翻译：两个或多个集成电路（IC）芯片相对于它们的通信频率被隔开相当长的距离，使得伪差分信号用于改善信号检测。产生导出的参考电压，其跟踪通常降低噪声容限的驱动器和接收机侧电源变化的变化。导出的参考电压被滤波以降低高频响应并作为用于检测通信信号的逻辑电平的差分接收器的参考而耦合。

3. 发明授权

US07521968B2 Slew rate control for driver circuit 有权
标题翻译：驱动电路的转换速率控制
公开(公告)号：US07521968B2
公开(公告)日：2009-04-21
申请号：US11055852
申请日：2005-02-11
申请人： Daniel M. Dreps , John C. Schief , Glen A. Wiedemeier , Joel D. Ziegelbein
发明人： Daniel M. Dreps , John C. Schief , Glen A. Wiedemeier , Joel D. Ziegelbein
IPC分类号： H03K19/0175
CPC分类号： H03K17/164
摘要： The slew rate of signals output from an integrated circuit is selectively controlled to optimize the quality of the output data signal depending upon whether the communication channels require a faster or slower slew rate. Faster slew rates may be utilized when the communication channels are prone to attenuation, while slower slew rates may be implemented in the communication channels when crosstalk is more of a concern.
摘要翻译：选择性地控制从集成电路输出的信号的转换速率，以根据通信信道是否需要更快或更慢的转换速率来优化输出数据信号的质量。当通信信道易于衰减时，可以利用更快的转换速率，而当串扰更受关注时，可以在通信信道中实现较慢的转换速率。

4. 发明授权

US07212035B2 Logic line driver system for providing an optimal driver characteristic 失效
标题翻译：逻辑线驱动系统，提供最佳驱动特性
公开(公告)号：US07212035B2
公开(公告)日：2007-05-01
申请号：US11055834
申请日：2005-02-11
申请人： Daniel M. Dreps , John C. Schiff , Glen A. Wiedemeier , Joel D. Ziegelbein
发明人： Daniel M. Dreps , John C. Schiff , Glen A. Wiedemeier , Joel D. Ziegelbein
IPC分类号： H03K19/0175
CPC分类号： H03K19/0005
摘要： A line driver for off-chip communication comprises multiple parallel stages each with separate inputs. The parallel stages each have a controlled impedance when driving the line driver output node to a logic zero or a logic one. A line driver controller is used to select what combination of driver stages are used to drive the output node based on whether the output node is transitioning between logic state or is remaining static. During power-up, a test program tries different combinations of driver stages for particular symbol patterns and determines what is the optimal ratio between line driver resistance for the dynamic and static cases and stores the optimum combination. The data stream feeding the line driver is sampled in real time to determine the transition states and selects the optimal number of driver stages for each case.
摘要翻译：用于片外通信的线路驱动器包括多个并行级，每个并行级具有单独的输入。当将线路驱动器输出节点驱动到逻辑0或逻辑1时，并联级各自具有受控阻抗。线路驱动器控制器用于基于输出节点是在逻辑状态之间转换还是保持静态来选择驱动器级的组合来驱动输出节点。在上电期间，测试程序尝试针对特定符号模式的驱动器级的不同组合，并确定动态和静态情况下线驱动器电阻之间的最佳比例是多少，并存储最佳组合。馈送线路驱动器的数据流被实时采样以确定转换状态，并为每种情况选择最佳数量的驱动级。

5. 发明授权

US07242249B2 Peaking transmission line receiver for logic signals 失效
标题翻译：峰值传输线接收机用于逻辑信号
公开(公告)号：US07242249B2
公开(公告)日：2007-07-10
申请号：US11055806
申请日：2005-02-11
申请人： Daniel M. Dreps , Bao G. Truong , Glen A. Wiedemeier
发明人： Daniel M. Dreps , Bao G. Truong , Glen A. Wiedemeier
IPC分类号： H03F3/45 , H03K19/094
CPC分类号： G11C7/1078 , G11C7/02 , G11C7/1084
摘要： A receiver circuit is configured as a frequency compensated differential amplifier having one input coupled to the output of a transmission line to receive a transmitted signal and the second input coupled to a reference voltage. The differential amplifier has a high frequency gain equivalent to the gain of an uncompensated differential stage for the transmitted signal. The compensated differential amplifier has an attenuated low frequency gain for signal frequencies substantially lower than the high frequency and a transitional gain for frequencies between the low and high frequencies. A compensated stage provides the portion of the signal with a compensated response and an uncompensated stage provides the portion of the amplified signal that is uncompensated. Bias control signals determine how much of the output signal is from the compensated and uncompensated stages as a means for customizing response from transmission lines with varying losses.
摘要翻译：接收器电路被配置为频率补偿差分放大器，其具有耦合到传输线的输出的一个输入以接收传输的信号，而第二输入耦合到参考电压。差分放大器具有等于发射信号的未补偿差分级的增益的高频增益。补偿的差分放大器对于低于高频的信号频率具有衰减的低频增益，对于低频和高频之间的频率具有过渡增益。补偿级为信号的一部分提供补偿响应，并且未补偿级提供未被补偿的放大信号的部分。偏置控制信号确定来自补偿和无补偿级的输出信号的大小是用于定制来自具有不同损耗的传输线的响应的手段。

6. 发明申请

US20050253622A1 Circuit for generating a tracking reference voltage 失效
标题翻译：用于产生跟踪参考电压的电路
公开(公告)号：US20050253622A1
公开(公告)日：2005-11-17
申请号：US10845568
申请日：2004-05-13
申请人： Daniel M. Dreps , Anand Haridass , Bao Truong
发明人： Daniel M. Dreps , Anand Haridass , Bao Truong
IPC分类号： H03K17/16 , H04L25/06 , H04L25/45
CPC分类号： H04L25/061 , H04L25/45
摘要： Two or more integrated circuit (IC) chips are separated by a significant distance relative to their communication frequency such that pseudo-differential signaling is used to improve signal detection. A derived reference voltage is generated that tracks the variations of the driver and receiver side power supply variations that normally reduce noise margins. The derived reference voltage is filtered to reduce high frequency response and coupled as the reference to differential receivers used to detect the logic levels of the communication signals.
摘要翻译：两个或多个集成电路（IC）芯片相对于它们的通信频率被隔开相当长的距离，使得伪差分信号用于改善信号检测。产生导出的参考电压，其跟踪通常降低噪声容限的驱动器和接收机侧电源变化的变化。导出的参考电压被滤波以降低高频响应并作为用于检测通信信号的逻辑电平的差分接收器的参考而耦合。

7. 发明授权

US08018837B2 Self-healing chip-to-chip interface 失效
标题翻译：自愈芯片到芯片的接口
公开(公告)号：US08018837B2
公开(公告)日：2011-09-13
申请号：US12635121
申请日：2009-12-10
申请人： Wiren D. Becker , Daniel M. Dreps , Frank D. Ferraiolo , Anand Haridass , Robert J. Reese
发明人： Wiren D. Becker , Daniel M. Dreps , Frank D. Ferraiolo , Anand Haridass , Robert J. Reese
IPC分类号： G01R31/08
CPC分类号： H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.
摘要翻译：一种用于管理用于芯片的一组信号路径的方法，装置和计算机指令。检测用于芯片的信号路径集合内的有缺陷的信号路径。信号通过一组信号路径重新路由，使得有缺陷的信号路径从信号路径集合中移除，并使用信号路径组中的剩余数据信号路径发送信号，并且响应于检测到的信号路径有缺陷的信号路径。

8. 发明授权

US06930507B2 Thevenins receiver 失效
标题翻译：戴维宁接收器
公开(公告)号：US06930507B2
公开(公告)日：2005-08-16
申请号：US10616845
申请日：2003-07-10
申请人： Daniel M. Dreps , Frank D. Ferraiolo , Anand Haridass , Bao Gia-Harvey Truong
发明人： Daniel M. Dreps , Frank D. Ferraiolo , Anand Haridass , Bao Gia-Harvey Truong
IPC分类号： H03K19/003
CPC分类号： H04L25/0278 , H04L25/0296
摘要： A termination network has multiple resistors forming multiple voltage dividers with a common node. Half of the resistors are coupled to the positive power supply voltage with P channel field effect transistors (PFETs) and the other half are coupled to the negative or ground power supply voltage with N channel FETs (NFETs). Logic signals are used to control the gates of the FETs. By modifying which FETs are ON, the termination network can be selectively controlled to produce various offset levels with the same impedance level. The impedance levels may also be modified while maintaining the same offset level. A delay circuit may be selectively employed to feedback control signals after a selected delay time to adjust the threshold level to dynamically or statically optimize signal reception.
摘要翻译：终端网络具有多个电阻器，其形成具有公共节点的多个分压器。一半的电阻器与P沟道场效应晶体管（PFET）耦合到正电源电压，另一半电阻与N沟道FET（NFET）耦合到负极或接地电源电压。逻辑信号用于控制FET的栅极。通过修改哪些FET为ON，可以选择性地控制终端网络以产生具有相同阻抗水平的各种偏移电平。阻抗水平也可以被修改，同时保持相同的偏移水平。可以选择性地采用延迟电路来在所选择的延迟时间之后反馈控制信号以调整阈值电平以动态地或静态地优化信号接收。

9. 发明授权

US08050174B2 Self-healing chip-to-chip interface 失效
公开(公告)号：US08050174B2
公开(公告)日：2011-11-01
申请号：US12886404
申请日：2010-09-20
申请人： Wiren D. Becker , Daniel M. Dreps , Frank D. Ferraiolo , Anand Haridass , Robert J. Reese
发明人： Wiren D. Becker , Daniel M. Dreps , Frank D. Ferraiolo , Anand Haridass , Robert J. Reese
IPC分类号： G01R31/08
CPC分类号： H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.

10. 发明授权

US08718216B2 Digital phase detector with zero phase offset 失效
公开(公告)号：US08718216B2
公开(公告)日：2014-05-06
申请号：US13242053
申请日：2011-09-23
申请人： Daniel M. Dreps , Kyu-hyoun Kim , Glen A. Wiedemeier
发明人： Daniel M. Dreps , Kyu-hyoun Kim , Glen A. Wiedemeier
IPC分类号： H03D3/24
CPC分类号： H04L7/0037 , H03L7/0814 , H03L7/085 , H03L7/089
摘要： An embodiment of the invention comprises a digital phase detector with substantially zero phase offset. The digital phase detector receives a clock signal and a reference clock signal and provides a phase indicator signal to identify whether the clock signal leads or lags the reference clock signal. An embodiment of the invention comprises a method that adds substantially zero phase offset in processing an input clock signal and a delayed clock signal to generate a control signal. The control signal is processed in a variable delay line to generate the delayed clock signal. In an embodiment, a first processor comprises a delay locked loop having a digital phase detector, the digital phase detector comprising a first differential sense amplifier cross-coupled to a second differential sense amplifier, the digital phase detector receiving a clock signal and generating one or more delayed clock signals, a control signal, and a gated data signal.

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