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    • 53. 发明授权
    • Domino logic circuits and pipelined domino logic circuits
    • 多米诺逻辑电路和流水线多米诺逻辑电路
    • US08542033B2
    • 2013-09-24
    • US13234811
    • 2011-09-16
    • Hyoung-Wook LeeGun-Ok JungSuhwan KimAh-Reum KimRahul Singh
    • Hyoung-Wook LeeGun-Ok JungSuhwan KimAh-Reum KimRahul Singh
    • H03K19/00
    • H03K19/0966
    • A domino logic circuit includes a first evaluation unit, a second evaluation unit and an output unit. The first evaluation unit precharges a first dynamic node, discharges a footer node in a first phase of a clock signal, and evaluates a plurality of input signals to determine a logic level of the first dynamic node in a second phase of the clock signal. The second evaluation unit precharges a second dynamic node in the first phase of the clock signal, and determines a logic level of the second dynamic node in response to a logic level of the footer node in the second phase of the clock signal. The output unit provides an output signal having a logic level according to levels of a first voltage of the first dynamic node and a second voltage of the second dynamic node.
    • 多米诺逻辑电路包括第一评估单元,第二评估单元和输出单元。 第一评估单元对第一动态节点进行预充电,在时钟信号的第一阶段放电页脚节点,并且评估多个输入信号以在时钟信号的第二阶段中确定第一动态节点的逻辑电平。 第二评估单元在时钟信号的第一阶段中对第二动态节点进行预充电,并且响应于时钟信号的第二阶段中的页脚节点的逻辑电平来确定第二动态节点的逻辑电平。 输出单元提供具有根据第一动态节点的第一电压的电平和第二动态节点的第二电压的逻辑电平的输出信号。
    • 55. 发明授权
    • System and method for controlling access to web services resources
    • 用于控制对Web服务资源的访问的系统和方法
    • US08447829B1
    • 2013-05-21
    • US11351904
    • 2006-02-10
    • Alan S. GellerRahul Singh
    • Alan S. GellerRahul Singh
    • G06F15/173
    • H04L47/70G06F9/468G06F21/6218H04L9/3239H04L63/101H04L67/10
    • A system and method for controlling access to web services resources. A system may include a storage medium configured to store instructions and one or more processors configured to access the storage medium. The instructions may be executable by at least one of the processors to implement a web services access control system (ACS) configured to receive requests. Each request specifies an access operation to be performed with respect to a corresponding resource. Each of the requests is associated with a corresponding principal. For each received request, the ACS may be further configured to determine whether an access control entry exists that is associated with both the resource and principal associated with the request and that specifies an access type sufficient to perform the access operation. If no such entry exists, the ACS may deny the request.
    • 一种用于控制对Web服务资源的访问的系统和方法。 系统可以包括被配置为存储指令的存储介质和被配置为访问存储介质的一个或多个处理器。 指令可以由至少一个处理器执行以实现被配置为接收请求的web服务访问控制系统(ACS)。 每个请求指定对相应资源执行的访问操作。 每个请求与相应的主体相关联。 对于每个接收到的请求,ACS还可以被配置为确定是否存在与请求相关联的资源和主体相关联的访问控制条目,并且指定访问类型足以执行访问操作。 如果没有这样的条目,ACS可以拒绝该请求。
    • 59. 发明授权
    • Chroma phase error correction circuitry and methods and systems utilizing the same
    • 色相相位误差校正电路及利用该电路的方法和系统
    • US07330217B1
    • 2008-02-12
    • US10969277
    • 2004-10-20
    • Rahul Singh
    • Rahul Singh
    • H04N9/455H04N9/66
    • H04N9/45
    • Chrominance phase error correction circuitry includes a demodulator for demodulating a received video color burst signal into first and second demodulated signals and signal generation circuitry for providing to the demodulator a demodulating signal for demodulating video color burst signal. Phase correction circuitry detects a phase error from the first and second demodulated signals and varies a phase of the demodulating signal to provide a corrected demodulating signal for demodulating a video chrominance signal with the demodulator during an active video period.
    • 色度相位误差校正电路包括用于将接收到的视频彩色脉冲串信号解调为第一和第二解调信号的解调器和用于向解调器提供用于解调视频色同步信号的解调信号的信号产生电路。 相位校正电路检测来自第一和第二解调信号的相位误差,并且改变解调信号的相位以提供校正的解调信号,用于在有效视频周期期间用解调器解调视频色度信号。