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1. 发明授权

US09367577B2 Method for processing patent information for outputting convergence index 有权
标题翻译：用于处理用于输出收敛指数的专利信息的方法
公开(公告)号：US09367577B2
公开(公告)日：2016-06-14
申请号：US14116079
申请日：2011-12-30
申请人： Nak Kyu Lee , Hye Jin Lee , Jung Han Song , Jeanho Park , Sung Min Bae , Hyoung Wook Lee , Chul Young Kim
发明人： Nak Kyu Lee , Hye Jin Lee , Jung Han Song , Jeanho Park , Sung Min Bae , Hyoung Wook Lee , Chul Young Kim
IPC分类号： G06F17/30 , G06Q10/10 , G06Q50/18
CPC分类号： G06F17/30321 , G06Q10/10 , G06Q50/184
摘要： The present invention relates to a method for outputting a convergence index, and more particularly, to a method for outputting a convergence index by utilizing patent information. According to the method for outputting the convergence index of the present invention, the convergence index can be outputted by using time information related to a patent which is included in a patent group, a patent classification, and an industrial classification that corresponds to the patent classification. The method for outputting the convergence index of the present invention systematically outputs the convergence index by using patent data, which is an objective data, thereby outputting the convergence index which is objective and appropriate.
摘要翻译：本发明涉及一种用于输出收敛指数的方法，更具体地说，涉及一种通过利用专利信息来输出收敛指数的方法。根据本发明的收敛指标的输出方法，可以通过使用与专利分类相关的专利的时间信息，专利分类，对应于专利分类的工业分类，输出收敛指数。用于输出本发明的收敛指标的方法通过使用作为客观数据的专利数据系统地输出收敛指数，从而输出客观和适当的收敛指数。

2. 发明授权

US08525180B2 Thin film transistor array panel 有权
公开(公告)号：US08525180B2
公开(公告)日：2013-09-03
申请号：US12785969
申请日：2010-05-24
申请人： Yeo-Geon Yoon , Hyoung-Wook Lee , Mi-Ae Lee , Ho-Jun Lee
发明人： Yeo-Geon Yoon , Hyoung-Wook Lee , Mi-Ae Lee , Ho-Jun Lee
IPC分类号： H01L33/00 , H01L27/088 , H01L29/786
CPC分类号： H01L27/124 , H01L27/1214 , H01L29/41733
摘要： A thin film transistor (TFT) array panel includes: first and second pixel electrodes neighboring each other; a data line extending between the first and the second pixel electrodes; first and second gate lines extending perpendicularly to the data line; a first TFT including a first gate electrode connected to the first gate line, a first source electrode connected to the data line, and a first drain electrode facing the first source electrode and connected to the first pixel electrode; and a second TFT including a second gate electrode connected to the second gate line, a second source electrode connected to the data line, and a second drain electrode facing the second source electrode and connected to the second pixel electrode. The first source electrode has the same relative position with respect to the first drain electrode as the second source electrode with respect to the second drain electrode.

3. 发明授权

US08344780B2 Flip-flop circuits and system including the same 有权
标题翻译：触发电路和系统包括相同的
公开(公告)号：US08344780B2
公开(公告)日：2013-01-01
申请号：US12797852
申请日：2010-06-10
申请人： Hyoung-Wook Lee , Min-Su Kim
发明人： Hyoung-Wook Lee , Min-Su Kim
IPC分类号： H03K3/00
CPC分类号： H03K3/356191
摘要： Flip-flop circuits including a dynamic input unit and a control clock generator are provided. The dynamic input unit precharges an evaluation node to a power supply voltage in a first phase of a clock signal, selectively discharges the evaluation node based on input data in a second phase of the clock signal, and compensates for voltage drop of the evaluation node in response to a first control clock signal. The control clock generator generates the first control clock signal and a second control clock signal based on at least the clock signal.
摘要翻译：提供了包括动态输入单元和控制时钟发生器的触发电路。动态输入单元在时钟信号的第一阶段中将评估节点预充电到电源电压，基于时钟信号的第二相位中的输入数据选择性地放电评估节点，并且补偿评估节点的电压降响应于第一控制时钟信号。控制时钟发生器至少基于时钟信号产生第一控制时钟信号和第二控制时钟信号。

4. 发明申请

US20120326172A1 LIQUID CRYSTAL DISPLAY AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：液晶显示器及其制造方法
公开(公告)号：US20120326172A1
公开(公告)日：2012-12-27
申请号：US13361614
申请日：2012-01-30
申请人： Woo Yong SUNG , Tae Woon CHA , Jeong Ho LEE , Sang Gun CHOI , Hyoung Wook LEE
发明人： Woo Yong SUNG , Tae Woon CHA , Jeong Ho LEE , Sang Gun CHOI , Hyoung Wook LEE
IPC分类号： H01L33/50 , H01L33/08
CPC分类号： G02F1/133711 , G02F2201/501 , G02F2202/42 , H01L29/41733
摘要： Provided is a liquid crystal display including: a first substrate; a thin film transistor disposed on the first substrate; a passivation layer disposed on the thin film transistor and comprising a contact hole exposing an electrode of the thin film transistor; a pixel electrode disposed on the passivation layer and connected to the electrode of the thin film transistor through the contact hole; a lower buffer layer disposed on the pixel electrode; a lower alignment layer disposed on the lower buffer layer; a second substrate facing the first substrate; a common electrode disposed on the second substrate; an upper buffer layer disposed on the common electrode; and an upper alignment layer disposed on the upper buffer layer, in which the lower buffer layer comprises parylene, the upper buffer layer comprises parylene, or both the lower and the upper buffer layers comprise parylene.
摘要翻译：提供一种液晶显示器，包括：第一基板; 设置在所述第一基板上的薄膜晶体管; 钝化层，设置在所述薄膜晶体管上，并且包括暴露所述薄膜晶体管的电极的接触孔; 设置在所述钝化层上并通过所述接触孔与所述薄膜晶体管的电极连接的像素电极; 设置在像素电极上的下缓冲层; 下配置层设置在下缓冲层上; 面对所述第一基板的第二基板; 设置在所述第二基板上的公共电极; 设置在公共电极上的上缓冲层; 以及设置在上缓冲层上的上取向层，其中下缓冲层包括聚对二甲苯，上缓冲层包含聚对二甲苯，或者下缓冲层和上缓冲层都包括聚对二甲苯。

5. 发明申请

US20120007082A1 THIN FILM TRANSISTOR ARRAY PANEL 有权
标题翻译：薄膜晶体管阵列
公开(公告)号：US20120007082A1
公开(公告)日：2012-01-12
申请号：US13072962
申请日：2011-03-28
申请人： Yeo-Geon YOON , Hyoung-Wook LEE , Mi-Ae LEE , Ho-Jun Lee
发明人： Yeo-Geon YOON , Hyoung-Wook LEE , Mi-Ae LEE , Ho-Jun Lee
IPC分类号： H01L29/04
CPC分类号： H01L27/124 , H01L27/1214 , H01L27/1248
摘要： A thin film transistor array panel includes an insulating substrate, a plurality of pixel electrodes arranged on the insulating substrate in rows and columns, a plurality of thin film transistors connected with the plurality of pixel electrodes, respectively, and a plurality of gate lines and a plurality of data lines connected with the plurality of thin film transistors. When one data line and one pixel electrode which are connected with a single thin film transistor are referred to as a connected data line and a connected pixel electrode, respectively, the plurality of thin film transistors are positioned on a same side of the connected data line in two adjacent rows, and on alternating sides of the connected data line in every other two adjacent rows. Two boundary lines of the connected pixel electrode are overlapped with the connected data line.
摘要翻译：薄膜晶体管阵列面板包括绝缘基板，以行和列布置在绝缘基板上的多个像素电极，分别与多个像素电极连接的多个薄膜晶体管，以及多个栅极线和多个数据线与多个薄膜晶体管连接。将与单个薄膜晶体管连接的一个数据线和一个像素电极分别称为连接的数据线和连接的像素电极时，多个薄膜晶体管位于连接的数据线的同一侧在两个相邻的行中，并且在每隔一个两个相邻行中连接的数据线的交替侧。连接的像素电极的两条边界线与连接的数据线重叠。

6. 发明授权

US08809864B2 Liquid crystal display and method for manufacturing the same 有权
标题翻译：液晶显示器及其制造方法
公开(公告)号：US08809864B2
公开(公告)日：2014-08-19
申请号：US13361614
申请日：2012-01-30
申请人： Woo Yong Sung , Tae Woon Cha , Jeong Ho Lee , Sang Gun Choi , Hyoung Wook Lee
发明人： Woo Yong Sung , Tae Woon Cha , Jeong Ho Lee , Sang Gun Choi , Hyoung Wook Lee
IPC分类号： H01L33/00
CPC分类号： G02F1/133711 , G02F2201/501 , G02F2202/42 , H01L29/41733
摘要： Provided is a liquid crystal display including: a first substrate; a thin film transistor disposed on the first substrate; a passivation layer disposed on the thin film transistor and comprising a contact hole exposing an electrode of the thin film transistor; a pixel electrode disposed on the passivation layer and connected to the electrode of the thin film transistor through the contact hole; a lower buffer layer disposed on the pixel electrode; a lower alignment layer disposed on the lower buffer layer; a second substrate facing the first substrate; a common electrode disposed on the second substrate; an upper buffer layer disposed on the common electrode; and an upper alignment layer disposed on the upper buffer layer, in which the lower buffer layer comprises parylene, the upper buffer layer comprises parylene, or both the lower and the upper buffer layers comprise parylene.
摘要翻译：提供一种液晶显示器，包括：第一基板; 设置在所述第一基板上的薄膜晶体管; 钝化层，设置在所述薄膜晶体管上，并且包括暴露所述薄膜晶体管的电极的接触孔; 设置在所述钝化层上并通过所述接触孔与所述薄膜晶体管的电极连接的像素电极; 设置在像素电极上的下缓冲层; 下配置层设置在下缓冲层上; 面对所述第一基板的第二基板; 设置在所述第二基板上的公共电极; 设置在公共电极上的上缓冲层; 以及设置在上缓冲层上的上取向层，其中下缓冲层包括聚对二甲苯，上缓冲层包含聚对二甲苯，或者下缓冲层和上缓冲层都包括聚对二甲苯。

7. 发明申请

US20140195443A1 SYSTEM FOR CONVERGENCE INDEX SERVICE 审中-公开
标题翻译：综合指数服务系统
公开(公告)号：US20140195443A1
公开(公告)日：2014-07-10
申请号：US14116060
申请日：2011-12-30
申请人： Nak Kyu Lee , Hye Jin Lee , Jung Han Song , Jeanho Park , Sung Min Bae , Hyoung Wook Lee , Chul Young Kim
发明人： Nak Kyu Lee , Hye Jin Lee , Jung Han Song , Jeanho Park , Sung Min Bae , Hyoung Wook Lee , Chul Young Kim
IPC分类号： G06Q50/18 , G06Q10/00
CPC分类号： G06Q50/184 , G06Q10/00 , G06Q10/06 , G06Q50/10
摘要： The present invention relates to a system for servicing convergence index, and more particularly, to a system for servicing a convergence index for outputting a convergence index by utilizing patent information and servicing same. According to the system for servicing the convergence index of the present invention, the convergence index can be outputted by using time information related to a patent which is included in a patent group, a patent classification, and an industrial classification that corresponds to the patent classification. The system for servicing the convergence index of the present invention systematically outputs the convergence index by using patent data, which is an objective data, thereby outputting the convergence index which is objective and appropriate.
摘要翻译：技术领域本发明涉及一种用于服务收敛指数的系统，更具体地，涉及一种通过利用专利信息并对其进行维护来输出收敛指数的收敛指标的系统。根据本发明的收敛指标的维修系统，可以通过使用与专利组相关的专利的时间信息，专利分类和对应于专利分类的工业分类，输出收敛指数。用于维护本发明的收敛指标的系统通过使用作为客观数据的专利数据系统地输出收敛指数，从而输出客观和适当的收敛指数。

8. 发明申请

US20100308864A1 FLIP-FLOP CIRCUIT HAVING SCAN FUNCTION 有权
标题翻译：具有扫描功能的FLIP-FLOP电路
公开(公告)号：US20100308864A1
公开(公告)日：2010-12-09
申请号：US12795916
申请日：2010-06-08
申请人： Hyoung Wook LEE , Min-Su Kim
发明人： Hyoung Wook LEE , Min-Su Kim
IPC分类号： H03K19/173 , H03K3/356
CPC分类号： H03K3/356191 , G01R31/318541
摘要： A flip-flop circuit having a scan function includes an internal clock generator to receive a clock signal, a scan enable signal, and a first input signal, and to output an internal timing signal based on each of the clock signal, the scan enable signal, and the first input signal. The circuit includes a dynamic input unit to receive a second input signal, the scan enable signal, a first timing signal, and the internal timing signal, and to output a first output signal. The circuit also includes a static output unit to receive the first timing signal and the first output signal and to output a static output signal, and the dynamic input unit outputs the first output signal corresponding to one of the first input signal and the second input signal, respectively, based on a status of the scan enable signal.
摘要翻译：具有扫描功能的触发器电路包括内部时钟发生器，用于接收时钟信号，扫描使能信号和第一输入信号，并且基于每个时钟信号输出内部定时信号，扫描使能信号和第一输入信号。该电路包括用于接收第二输入信号，扫描使能信号，第一定时信号和内部定时信号的动态输入单元，并输出第一输出信号。该电路还包括静态输出单元，用于接收第一定时信号和第一输出信号并输出静态输出信号，动态输入单元输出对应于第一输入信号和第二输入信号之一的第一输出信号，分别基于扫描使能信号的状态。

9. 发明授权

US06323305B1 Process for preparing polyethylene naphthalate based polymers by using NDCA or its derivates 有权
标题翻译：通过使用NDCA或其衍生物制备聚萘二甲酸乙二醇酯基聚合物的方法
公开(公告)号：US06323305B1
公开(公告)日：2001-11-27
申请号：US09589267
申请日：2000-06-07
申请人： Hyun Nam Cho , Jae Min Hong , Hyoung-Wook Lee , Young Chan Ko , Il Seok Choi
发明人： Hyun Nam Cho , Jae Min Hong , Hyoung-Wook Lee , Young Chan Ko , Il Seok Choi
IPC分类号： C08G6302
CPC分类号： C08G63/78 , C08G63/189
摘要： The present invention provides a process for preparing polyethylene naphthalate polymers comprising: esterifying a slurry comprising NDCA or a dicarboxylic acid containing NDCA or derivatives thereof, and ethylene glycol or a glycol containing ethylene glycol or derivatives thereof to produce esterification compounds comprising bis (beta-hydroxyethyl) naphthalate or low molecular weight polymers thereof, wherein one or more primary alcohol is added to the slurry; and polycondensing the above resultant esterification compounds to produce polyethylene naphthalate polymers. The process of the present invention allows for the preparation of a slurry more easily and to maximize the manufacturing efficiency. Ultimately, it is possible to increase the productivity of the PEN polymers and to obtain high quality PEN since the method of the present invention has an effect of minimizing side products of the polymerization by reducing the amount of ethylene glycol considerably and of shortening the reaction time of the esterification reaction.
摘要翻译：本发明提供了一种制备聚萘二甲酸乙二醇酯聚合物的方法，包括：将包含NDCA或含有NDCA或其衍生物的二羧酸的淤浆和含乙二醇的乙二醇或其衍生物或其衍生物酯化，制备含有二（β-羟乙基）萘二甲酸酯或其低分子量聚合物，其中将一种或多种伯醇加入到浆料中; 并缩聚上述所得酯化化合物以制备聚萘二甲酸乙二醇酯聚合物。本发明的方法允许更容易地制备浆料并且最大化制造效率。最终，可以提高PEN聚合物的生产率并获得高质量的PEN，因为本发明的方法具有通过显着减少乙二醇的量并缩短反应时间而使聚合的副产物最小化的效果的酯化反应。

10. 发明授权

US08665405B2 Thin film transistor array panel 有权
标题翻译：薄膜晶体管阵列面板
公开(公告)号：US08665405B2
公开(公告)日：2014-03-04
申请号：US13072962
申请日：2011-03-28
申请人： Yeo-Geon Yoon , Hyoung-Wook Lee , Mi-Ae Lee , Ho-Jun Lee
发明人： Yeo-Geon Yoon , Hyoung-Wook Lee , Mi-Ae Lee , Ho-Jun Lee
IPC分类号： G02F1/1343 , G02F1/136
CPC分类号： H01L27/124 , H01L27/1214 , H01L27/1248
摘要： A thin film transistor array panel includes an insulating substrate, a plurality of pixel electrodes arranged on the insulating substrate in rows and columns, a plurality of thin film transistors connected with the plurality of pixel electrodes, respectively, and a plurality of gate lines and a plurality of data lines connected with the plurality of thin film transistors. When one data line and one pixel electrode which are connected with a single thin film transistor are referred to as a connected data line and a connected pixel electrode, respectively, the plurality of thin film transistors are positioned on a same side of the connected data line in two adjacent rows, and on alternating sides of the connected data line in every other two adjacent rows. Two boundary lines of the connected pixel electrode are overlapped with the connected data line.
摘要翻译：薄膜晶体管阵列面板包括绝缘基板，以行和列布置在绝缘基板上的多个像素电极，分别与多个像素电极连接的多个薄膜晶体管，以及多个栅极线和多个数据线与多个薄膜晶体管连接。将与单个薄膜晶体管连接的一个数据线和一个像素电极分别称为连接的数据线和连接的像素电极时，多个薄膜晶体管位于连接的数据线的同一侧在两个相邻的行中，并且在每隔一个两个相邻行中连接的数据线的交替侧。连接的像素电极的两条边界线与连接的数据线重叠。

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