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51. 发明授权

US07384833B2 Stress liner for integrated circuits 有权
标题翻译：集成电路应力衬垫
公开(公告)号：US07384833B2
公开(公告)日：2008-06-10
申请号：US11350160
申请日：2006-02-07
申请人： Igor Polishchuk , Krishnaswamy Ramkumar , Sagy Charel Levy
发明人： Igor Polishchuk , Krishnaswamy Ramkumar , Sagy Charel Levy
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： In one embodiment, a self-aligned contact (SAC) trench structure is formed through a dielectric layer to expose an active region of a MOS transistor. The SAC trench structure not only exposes the active region for electrical connection but also removes portions of a stress liner over the active region. This leaves the stress liner mostly on the sidewall and top of the gate of the MOS transistor. Removing portions of the stress liner over the active region substantially removes the lateral component of the strain imparted by the stress liner on the substrate, allowing for improved drive current without substantially degrading a complementary MOS transistor.
摘要翻译：在一个实施例中，通过电介质层形成自对准接触（SAC）沟槽结构以暴露MOS晶体管的有源区。 SAC沟槽结构不仅暴露用于电连接的有源区，而且还去除了有源区上的应力衬垫的部分。这使得应力衬垫主要在MOS晶体管的侧壁和顶部上方。在有源区上去除应力衬垫的部分基本上消除了由衬底上的应力衬垫施加的应变的横向分量，从而允许改进的驱动电流而不会使互补MOS晶体管基本上降级。

52. 发明授权

US07256087B1 Techniques for improving negative bias temperature instability (NBTI) lifetime of field effect transistors 有权
标题翻译：改善场效应晶体管负偏压温度不稳定性（NBTI）寿命的技术
公开(公告)号：US07256087B1
公开(公告)日：2007-08-14
申请号：US11018422
申请日：2004-12-21
申请人： Sharmin Sadoughi , Krishnaswamy Ramkumar , Ravindra Kapre , Igor Polishchuk , Maroun Khoury
发明人： Sharmin Sadoughi , Krishnaswamy Ramkumar , Ravindra Kapre , Igor Polishchuk , Maroun Khoury
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823842
摘要： In one embodiment, an integrated circuit includes a PMOS transistor having a gate stack comprising a P+ doped gate polysilicon layer and a nitrided gate oxide (NGOX) layer. The NGOX layer may be over a silicon substrate. The integrated circuit further includes an interconnect line formed over the transistor. The interconnect line includes a hydrogen getter material and may comprise a single material or stack of materials. The interconnect line advantageously getters hydrogen (e.g., H2 or H2O) that would otherwise be trapped in the NGOX layer/silicon substrate interface, thereby improving the negative bias temperature instability (NBTI) lifetime of the transistor.
摘要翻译：在一个实施例中，集成电路包括具有包括P +掺杂栅极多晶硅层和氮化栅极氧化物（NGOX）层的栅极堆叠的PMOS晶体管。 NGOX层可以在硅衬底之上。集成电路还包括形成在晶体管上的互连线。互连线包括吸氢材料，并且可以包括单一材料或材料堆。互连线有利地吸收否则将被捕获在NGOX层/硅衬底界面中的氢（例如，H 2 H 2或H 2 O 2），从而提高负偏压温度晶体管的不稳定性（NBTI）寿命。

53. 发明授权

US07227212B1 Method of forming a floating metal structure in an integrated circuit 有权
标题翻译：在集成电路中形成浮动金属结构的方法
公开(公告)号：US07227212B1
公开(公告)日：2007-06-05
申请号：US11021220
申请日：2004-12-23
申请人： Mira Ben-Tzur , Krishnaswamy Ramkumar , James Hunter , Thurman J. Rodgers , Mike Bruner , Klyoko Ikeuchi
发明人： Mira Ben-Tzur , Krishnaswamy Ramkumar , James Hunter , Thurman J. Rodgers , Mike Bruner , Klyoko Ikeuchi
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L23/5222 , H01L21/7682 , H01L21/76885 , H01L23/5227 , H01L23/53223 , H01L23/53238 , H01L28/87 , H01L2924/0002 , Y10S257/924 , H01L2924/00
摘要： In one embodiment, a sacrificial layer is deposited over a base layer. The sacrificial layer is used to define a subsequently formed floating metal structure. The floating metal structure may be anchored into the base layer. Once the floating metal structure is formed, the sacrificial layer surrounding the floating metal structure is etched to create a unity-k dielectric region separating the floating metal structure from the base layer. The unity-k dielectric region also separates the floating metal structure from another floating metal structure. In one embodiment, a noble gas fluoride such as xenon difluoride is used to etch a sacrificial layer of polycrystalline silicon.
摘要翻译：在一个实施例中，牺牲层沉积在基底层上。牺牲层用于限定随后形成的浮动金属结构。浮动金属结构可以锚定到基层中。一旦形成了浮动金属结构，则蚀刻围绕浮动金属结构的牺牲层，以产生将浮动金属结构与基底层分开的单位k介电区域。 unity-k电介质区域还将浮动金属结构与另一个浮动金属结构分离。在一个实施方案中，使用惰性气体氟化物如二氟化氙来蚀刻多晶硅的牺牲层。

54. 发明授权

US07192867B1 Protection of low-k dielectric in a passivation level 有权
标题翻译：保护低k电介质在钝化水平
公开(公告)号：US07192867B1
公开(公告)日：2007-03-20
申请号：US10184336
申请日：2002-06-26
申请人： Mira Ben-Tzur , Krishnaswamy Ramkumar , Seurabh Dutta Chowdhury , Michal Efrati Fastow
发明人： Mira Ben-Tzur , Krishnaswamy Ramkumar , Seurabh Dutta Chowdhury , Michal Efrati Fastow
IPC分类号： H01L21/302
CPC分类号： H01L21/76831 , H01L21/76814
摘要： In one embodiment, a passivation level includes a low-k dielectric. To prevent the low-k dielectric from absorbing moisture when exposed to air, exposed portions of the low-k dielectric are covered with spacers. As can be appreciated, this facilitates integration of low-k dielectrics in passivation levels. Low-k dielectrics in passivation levels help lower capacitance on metal lines, thereby reducing RC delay and increasing signal propagation speeds.
摘要翻译：在一个实施例中，钝化层包括低k电介质。为了防止低k电介质暴露于空气时吸收水分，低k电介质的暴露部分被间隔物覆盖。可以理解，这有助于低k电介质在钝化层中的集成。钝化层中的低k电介质有助于降低金属线路上的电容，从而减少RC延迟并增加信号传播速度。

55. 发明授权

US06835616B1 Method of forming a floating metal structure in an integrated circuit 有权
标题翻译：在集成电路中形成浮动金属结构的方法
公开(公告)号：US06835616B1
公开(公告)日：2004-12-28
申请号：US10059823
申请日：2002-01-29
申请人： Mira Ben-Tzur , Krishnaswamy Ramkumar , James Hunter , Thurman J. Rodgers , Mike Bruner , Klyoko Keuchi
发明人： Mira Ben-Tzur , Krishnaswamy Ramkumar , James Hunter , Thurman J. Rodgers , Mike Bruner , Klyoko Keuchi
IPC分类号： H01L218242
CPC分类号： H01L23/5222 , H01L21/7682 , H01L21/76885 , H01L23/5227 , H01L23/53223 , H01L23/53238 , H01L28/87 , H01L2924/0002 , Y10S257/924 , H01L2924/00
摘要： In one embodiment, a sacrificial layer is deposited over a base layer. The sacrificial layer is used to define a subsequently formed floating metal structure. The floating metal structure may be anchored into the base layer. Once the floating metal structure is formed, the sacrificial layer surrounding the floating metal structure is etched to create a unity-k dielectric region separating the floating metal structure from the base layer. The unity-k dielectric region also separates the floating metal structure from another floating metal structure. In one embodiment, a noble gas fluoride such as xenon difluoride is used to etch a sacrificial layer of polycrystalline silicon.
摘要翻译：在一个实施例中，牺牲层沉积在基底层上。牺牲层用于限定随后形成的浮动金属结构。浮动金属结构可以锚定到基层中。一旦形成了浮动金属结构，则蚀刻围绕浮动金属结构的牺牲层，以产生将浮动金属结构与基底层分开的单位k介电区域。 unity-k电介质区域还将浮动金属结构与另一个浮动金属结构分离。在一个实施方案中，使用惰性气体氟化物如二氟化氙来蚀刻多晶硅的牺牲层。

56. 发明授权

US06624052B2 Process for annealing semiconductors and/or integrated circuits 有权
公开(公告)号：US06624052B2
公开(公告)日：2003-09-23
申请号：US10200396
申请日：2002-07-22
申请人： Krishnaswamy Ramkumar , Manuj Rathor
发明人： Krishnaswamy Ramkumar , Manuj Rathor
IPC分类号： H01L21425
CPC分类号： H01L29/518 , H01L21/28176 , H01L21/3003 , H01L21/324 , H01L29/517
摘要： A method of making a semiconductor structure, includes annealing a structure in a deuterium-containing atmosphere. The structure includes (i) a substrate, (ii) a gate dielectric on the substrate, (iii) a gate on the gate dielectric, (iv) an etch-stop layer on the gate, and (v) an interlayer dielectric on the etch-stop layer.

57. 发明授权

US06555484B1 Method for controlling the oxidation of implanted silicon 失效
标题翻译：控制植入硅氧化的方法
公开(公告)号：US06555484B1
公开(公告)日：2003-04-29
申请号：US08878728
申请日：1997-06-19
申请人： Krishnaswamy Ramkumar , Hanna Bamnolker
发明人： Krishnaswamy Ramkumar , Hanna Bamnolker
IPC分类号： H01L21265
CPC分类号： H01L21/28185 , H01L21/2652 , H01L21/2822 , Y10S438/911 , Y10S438/92 , Y10S438/981
摘要： Two different regions of a semiconductor substrate are implanted with dopants/ions. The implantation may occur though a sacrificial oxide layer disposed over the substrate. Following implantation in one or both regions, the substrate may be annealed and the sacrificial oxide layer removed. An oxide layer is then grown over the implanted regions of the substrate. For some embodiments, the substrate may be implanted with arsenic and/or with phosphorus. Further, the anneal may be performed for approximately 30 to 120 minutes at a temperature between approximately 900° C. and 950° C.
摘要翻译：用掺杂剂/离子注入半导体衬底的两个不同区域。注入可以通过设置在衬底上的牺牲氧化层发生。在一个或两个区域中植入之后，可以对衬底进行退火并去除牺牲氧化物层。然后在衬底的注入区域上生长氧化物层。对于一些实施例，衬底可以用砷和/或磷进行注入。此外，退火可以在约900℃至950℃的温度下进行约30至120分钟。

58. 发明授权

US6033991A Isolation scheme based on recessed locos using a sloped Si etch and dry field oxidation 失效
标题翻译：基于使用倾斜Si蚀刻和干场氧化的凹陷区域的隔离方案
公开(公告)号：US6033991A
公开(公告)日：2000-03-07
申请号：US939838
申请日：1997-09-29
申请人： Krishnaswamy Ramkumar , Pamela Trammel , Sharmin Sadoughi
发明人： Krishnaswamy Ramkumar , Pamela Trammel , Sharmin Sadoughi
IPC分类号： H01L21/3065 , H01L21/311 , H01L21/316 , H01L21/762 , H01L21/302
CPC分类号： H01L21/76202 , H01L21/7621 , H01L21/3065 , H01L21/31116 , H01L21/31662
摘要： A method of forming a field oxide or an isolation region in a semiconductor die. An oxidation mask layer (over an oxide layer disposed over the substrate) is patterned and subsequently etched, preferably so that the oxidation mask layer may have a nearly vertical sidewall. The oxide layer and the substrate in the isolation region are etched to form a recess in the substrate having a sloped surface with respect to the sidewall of the oxidation mask layer. A field oxide is then grown in the recess using a dry oxidizing atmosphere. The sloped sidewall of the substrate recess effectively moves the face of the exposed substrate away from the edge of the oxidation mask layer sidewall. Compared to non-sloped techniques, the oxidation appears to start with a built-in offset from the patterned etch. This leads to a reduction of oxide encroachment and less field oxide thinning. The preferred range of slopes for the substrate sidewall is from approximately 10.degree. to 40.degree. with respect to the oxidation mask layer sidewall.
摘要翻译：在半导体管芯中形成场氧化物或隔离区域的方法。对氧化掩模层（位于衬底上方的氧化物层上方）进行构图并随后进行蚀刻，优选地使得氧化掩模层可具有几乎垂直的侧壁。蚀刻隔离区域中的氧化物层和衬底，以在衬底中形成相对于氧化掩模层的侧壁具有倾斜表面的凹部。然后使用干燥的氧化气氛将场氧化物生长在凹槽中。衬底凹槽的倾斜侧壁有效地将暴露的衬底的表面远离氧化掩模层侧壁的边缘移动。与非倾斜技术相比，氧化似乎从图案化蚀刻的内置偏移开始。这导致氧化物侵蚀减少和较少的场氧化物稀化。衬底侧壁的斜率的优选范围相对于氧化掩模层侧壁约为10°至40°。

59. 发明授权

US6004399A Ultra-low particle semiconductor cleaner for removal of particle contamination and residues from surface oxide formation on semiconductor wafers 失效
标题翻译：用于去除颗粒污染的超低颗粒半导体清洁剂和半导体晶片上表面氧化物形成的残留物
公开(公告)号：US6004399A
公开(公告)日：1999-12-21
申请号：US784207
申请日：1997-01-15
申请人： Kaichiu Wong , Krishnaswamy Ramkumar , Hanna Bamnolker , Suraj Puri , Rajiv Bhushan , David Wong , Gary Elmore , Raj Mohindra
发明人： Kaichiu Wong , Krishnaswamy Ramkumar , Hanna Bamnolker , Suraj Puri , Rajiv Bhushan , David Wong , Gary Elmore , Raj Mohindra
IPC分类号： B08B3/04 , B08B3/10 , B08B3/12 , H01L21/00 , B08B3/08
CPC分类号： H01L21/67057 , B08B3/04 , B08B3/102 , B08B3/12 , H01L21/67051 , Y10S134/902
摘要： A method is described for cleaning a semiconductor wafer. The method includes immersing a wafer in a liquid comprising water. The wafer has a front face, a back face, and an edge. The method also includes providing a substantially particle free environment adjacent to the front face and the back face as the liquid is being removed. A step of introducing a carrier gas comprising a cleaning enhancement substance also is included. It is believed that the cleaning enhancement substance dopes any liquid adhered to the front and back faces of the wafer to cause a concentration gradient of the cleaning enhancement substance in the liquid and accelerate removal of the adhered liquid off of the water.
摘要翻译：描述了一种用于清洁半导体晶片的方法。该方法包括将晶片浸入包含水的液体中。晶片具有前表面，后表面和边缘。该方法还包括当正在除去液体时提供与前表面和背面相邻的基本上无颗粒的环境。还包括引入包含清洁增强物质的载气的步骤。相信清洁增强物质会粘附到晶片的正面和背面的任何液体，从而引起液体中清洁增强物质的浓度梯度，并加速从水中除去附着液体。

60. 发明授权

US09716153B2 Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region 有权
公开(公告)号：US09716153B2
公开(公告)日：2017-07-25
申请号：US13539459
申请日：2012-07-01
申请人： Sagy Levy , Fredrick Jenne , Krishnaswamy Ramkumar
发明人： Sagy Levy , Fredrick Jenne , Krishnaswamy Ramkumar
IPC分类号： H01L29/792 , H01L29/40 , H01L21/28 , H01L29/51 , H01L29/66 , H01L29/78 , H01L29/786 , H01L29/04 , H01L29/06 , H01L29/16
CPC分类号： H01L29/408 , H01L21/28282 , H01L29/04 , H01L29/0676 , H01L29/16 , H01L29/513 , H01L29/518 , H01L29/66833 , H01L29/785 , H01L29/78696 , H01L29/792 , H01L29/7926
摘要： Scaling a charge trap memory device and the article made thereby. In one embodiment, the charge trap memory device includes a substrate having a source region, a drain region, and a channel region electrically connecting the source and drain. A tunnel dielectric layer is disposed above the substrate over the channel region, and a multi-layer charge-trapping region disposed on the tunnel dielectric layer. The multi-layer charge-trapping region includes a first deuterated layer disposed on the tunnel dielectric layer, a first nitride layer disposed on the first deuterated layer and a second nitride layer.

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