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1. 发明授权

US06624052B2 Process for annealing semiconductors and/or integrated circuits 有权
公开(公告)号：US06624052B2
公开(公告)日：2003-09-23
申请号：US10200396
申请日：2002-07-22
申请人： Krishnaswamy Ramkumar , Manuj Rathor
发明人： Krishnaswamy Ramkumar , Manuj Rathor
IPC分类号： H01L21425
CPC分类号： H01L29/518 , H01L21/28176 , H01L21/3003 , H01L21/324 , H01L29/517
摘要： A method of making a semiconductor structure, includes annealing a structure in a deuterium-containing atmosphere. The structure includes (i) a substrate, (ii) a gate dielectric on the substrate, (iii) a gate on the gate dielectric, (iv) an etch-stop layer on the gate, and (v) an interlayer dielectric on the etch-stop layer.

2. 发明授权

US06969689B1 Method of manufacturing an oxide-nitride-oxide (ONO) dielectric for SONOS-type devices 有权
标题翻译：用于SONOS型器件的氧化物 - 氮化物（ONO）电介质的制造方法
公开(公告)号：US06969689B1
公开(公告)日：2005-11-29
申请号：US10184715
申请日：2002-06-28
申请人： Krishnaswamy Ramkumar , Manuj Rathor , Biju Parameshwaran , Loren Lancaster
发明人： Krishnaswamy Ramkumar , Manuj Rathor , Biju Parameshwaran , Loren Lancaster
IPC分类号： H01L21/28 , H01L21/31 , H01L21/314 , H01L21/469 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11568 , H01L21/28282 , H01L21/3144 , H01L27/115
摘要： A method of forming oxide-nitride-oxide (ONO) dielectric of a SONOS-type nonvolatile storage device is disclosed. According to a first embodiment, a method may include the steps of forming a tunneling dielectric (step 102), forming a charge storing dielectric (step 104), and forming a top insulating layer (step 106) all in the same wafer processing tool. According to various aspects of the embodiments, all layers of an ONO dielectric of a SONOS-type device may be formed in the same general temperature range. Further, a tunneling dielectric may include a tunnel oxide formed with a long, low pressure oxidation, and a top insulating layer may include silicon dioxide formed with a preheated source gas.
摘要翻译：公开了一种形成SONOS型非易失性存储装置的氧化物 - 氧化物 - 氧化物（ONO）电介质的方法。根据第一实施例，一种方法可以包括以下步骤：形成隧道电介质（步骤102），形成电荷存储电介质（步骤104），以及在相同的晶片处理工具中形成顶部绝缘层（步骤106）。根据实施例的各个方面，SONOS型器件的ONO电介质的所有层可以形成在相同的一般温度范围内。此外，隧道电介质可以包括形成有长的低压氧化的隧道氧化物，并且顶部绝缘层可以包括用预热的源气体形成的二氧化硅。

3. 发明授权

US06436799B1 Process for annealing semiconductors and/or integrated circuits 有权
公开(公告)号：US06436799B1
公开(公告)日：2002-08-20
申请号：US09670089
申请日：2000-09-26
申请人： Krishnaswamy Ramkumar , Manuj Rathor
发明人： Krishnaswamy Ramkumar , Manuj Rathor
IPC分类号： H01L21425
CPC分类号： H01L29/518 , H01L21/28176 , H01L21/3003 , H01L21/324 , H01L29/517
摘要： A method of making a semiconductor structure, includes annealing a structure in a deuterium-containing atmosphere. The structure includes (i) a substrate, (ii) a gate dielectric on the substrate, (iii) a gate on the gate dielectric, (iv) an etch-stop layer on the gate, and (v) an interlayer dielectric on the etch-stop layer.

4. 发明授权

US06818558B1 Method of manufacturing a dielectric layer for a silicon-oxide-nitride-oxide-silicon (SONOS) type devices 有权
标题翻译：制造氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）型器件的介质层的方法
公开(公告)号：US06818558B1
公开(公告)日：2004-11-16
申请号：US10185470
申请日：2002-06-28
申请人： Manuj Rathor , Krishnaswamy Ramkumar , Fred Jenne , Loren Lancaster
发明人： Manuj Rathor , Krishnaswamy Ramkumar , Fred Jenne , Loren Lancaster
IPC分类号： H01L21311
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/42332 , H01L29/7882
摘要： A method of forming a charge storing layer is disclosed. According to an embodiment, a method may include the steps of forming a first portion of a charge storing layer with a first gas flow rate ratio (step 102), forming at least a second portion of the charge storing layer by changing to a second gas flow rate ratio that is different than the first gas flow rate ratio (step 104), and forming at least a third portion of the charge storing layer by changing to a third gas flow rate ratio that is different than the second gas flow rate ratio (step 106).
摘要翻译：公开了形成电荷存储层的方法。根据实施例，一种方法可以包括以第一气体流速比形成电荷存储层的第一部分（步骤102）的步骤，通过改变到第二气体形成电荷存储层的至少第二部分流量比与第一气体流量比不同（步骤104），并且通过改变到与第二气体流量比不同的第三气体流量比形成至少第三部分的电荷存储层（步骤106）。

5. 发明授权

US08710578B2 SONOS stack with split nitride memory layer 有权
标题翻译： SONOS堆叠带有划痕的氮化物存储层
公开(公告)号：US08710578B2
公开(公告)日：2014-04-29
申请号：US13431069
申请日：2012-03-27
申请人： Fredrick Jenne , Krishnaswamy Ramkumar
发明人： Fredrick Jenne , Krishnaswamy Ramkumar
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , B82Y10/00 , H01L21/28282 , H01L29/513 , H01L29/785 , H01L29/7926
摘要： Embodiments of a non-planar memory device including a split charge-trapping region and methods of forming the same are described. Generally, the device comprises: a channel formed from a thin film of semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide overlying the channel; a split charge-trapping region overlying the tunnel oxide, the split charge-trapping region including a bottom charge-trapping layer comprising a nitride closer to the tunnel oxide, and a top charge-trapping layer, wherein the bottom charge-trapping layer is separated from the top charge-trapping layer by a thin anti-tunneling layer comprising an oxide. Other embodiments are also disclosed.
摘要翻译：描述了包括分离电荷捕获区域的非平面存储器件及其形成方法的实施例。通常，该器件包括：由覆盖存储器件的源极和漏极的衬底上的表面的半导体材料薄膜形成的沟道; 覆盖通道的隧道氧化物; 分离电荷捕获区域，覆盖隧道氧化物，分离电荷捕获区域包括底部电荷捕获层，其包含更接近隧道氧化物的氮化物，以及顶部电荷捕获层，其中底部电荷捕获层被分离从顶部的电荷捕获层通过包含氧化物的薄的抗隧道层。还公开了其他实施例。

6. 发明申请

US20130178030A1 METHOD OF ONO INTEGRATION INTO LOGIC CMOS FLOW 有权
标题翻译： ONO集成到逻辑CMOS流的方法
公开(公告)号：US20130178030A1
公开(公告)日：2013-07-11
申请号：US13434347
申请日：2012-03-29
申请人： Krishnaswamy Ramkumar , Bo Jin , Fredrick Jenne
发明人： Krishnaswamy Ramkumar , Bo Jin , Fredrick Jenne
IPC分类号： H01L21/336
CPC分类号： B82Y10/00 , H01L21/28282 , H01L21/823431 , H01L21/823821 , H01L27/105 , H01L27/1052 , H01L27/11568 , H01L27/11573 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer.
摘要翻译：描述了将非易失性存储器件集成到逻辑MOS流中的方法的实施例。通常，该方法包括：在衬底的第一区域之上形成MOS器件的焊盘电介质层; 从半导体材料的薄膜形成存储器件的沟道，该半导体材料的薄膜覆盖在衬底的第二区域上方的表面，所述通道连接存储器件的源极和漏极; 形成覆盖在第二区域上方的通道上的图案化电介质堆叠，所述图案化电介质叠层包括隧道层，电荷俘获层和牺牲顶层; 同时从衬底的第二区域去除牺牲顶层，以及从衬底的第一区域去除焊盘介电层; 并且同时在衬底的第一区域上方形成栅极电介质层，并且在电荷俘获层上方形成阻挡电介质层。

7. 发明申请

US20130175504A1 OXIDE-NITRIDE-OXIDE STACK HAVING MULTIPLE OXYNITRIDE LAYERS 有权
标题翻译：具有多个氧化物层的氧化物 - 氮氧化物堆
公开(公告)号：US20130175504A1
公开(公告)日：2013-07-11
申请号：US13436872
申请日：2012-03-31
申请人： Sagy Levy , Krishnaswamy Ramkumar , Fredrick Jenne , Sam Geha
发明人： Sagy Levy , Krishnaswamy Ramkumar , Fredrick Jenne , Sam Geha
IPC分类号： H01L29/775
CPC分类号： H01L29/66833 , B82Y10/00 , G11C16/0466 , G11C16/10 , G11C16/14 , H01L21/28282 , H01L29/0673 , H01L29/0676 , H01L29/4234 , H01L29/42392 , H01L29/66795 , H01L29/7833 , H01L29/792 , H01L29/7926
摘要： An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.
摘要翻译：描述了包括多层电荷存储层的半导体存储器件的实施例及其形成方法。通常，该器件包括由半导体材料形成的沟道，该半导体材料覆盖连接存储器件的源极和漏极的衬底上的表面; 覆盖通道的隧道氧化物层; 以及多层电荷存储层，其在所述隧道氧化物层上包含富氧的第一氧氮化物层，其中所述第一氧氮化物层的化学计量组成导致其基本上无陷阱，并且将贫氧的第二氮氧化物层置于第一氧氮化物层，其中第二氧氮化物层的化学计量组成导致其陷阱致密。在一个实施例中，该器件包括非平面晶体管，其包括具有邻接通道的多个表面的栅极，并且栅极包括隧道氧化物层和多层电荷存储层。

8. 发明授权

US08445381B2 Oxide-nitride stack gate dielectric 有权
标题翻译：氧化氮化物堆叠栅极电介质
公开(公告)号：US08445381B2
公开(公告)日：2013-05-21
申请号：US11961750
申请日：2007-12-20
申请人： Krishnaswamy Ramkumar , Sundar Narayanan
发明人： Krishnaswamy Ramkumar , Sundar Narayanan
IPC分类号： H01L21/02
CPC分类号： H01L21/022 , H01L21/0217 , H01L21/02233 , H01L21/02337 , H01L21/28044 , H01L21/3144 , H01L29/4941 , H01L29/78
摘要： A method of making a semiconductor structure comprises forming an oxide layer on a substrate; forming a silicon nitride layer on the oxide layer; annealing the layers in NO; and annealing the layers in ammonia. The equivalent oxide thickness of the oxide layer and the silicon nitride layer together is at most 25 Angstroms.
摘要翻译：制造半导体结构的方法包括在衬底上形成氧化物层; 在氧化物层上形成氮化硅层; 在NO中退火层; 并在氨中退火层。氧化物层和氮化硅层的等效氧化物厚度在一起为至多25埃。

9. 发明授权

US08143129B2 Integration of non-volatile charge trap memory devices and logic CMOS devices 有权
标题翻译：集成非易失性电荷陷阱存储器件和逻辑CMOS器件
公开(公告)号：US08143129B2
公开(公告)日：2012-03-27
申请号：US12185747
申请日：2008-08-04
申请人： Krishnaswamy Ramkumar , Ravindra Kapre , Jeremy Warren
发明人： Krishnaswamy Ramkumar , Ravindra Kapre , Jeremy Warren
IPC分类号： H01L29/792
CPC分类号： H01L29/7833 , H01L21/823412 , H01L21/823425 , H01L21/823462 , H01L27/105 , H01L27/1052 , H01L27/11568 , H01L27/11573 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7836 , H01L29/7843
摘要： A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.
摘要翻译：一种半导体结构及其形成方法。半导体结构包括具有设置在第一区域上的非易失性电荷陷阱存储器件和设置在第二区域上的逻辑器件的衬底。可以在形成逻辑器件的阱和通道之后形成电荷陷阱电介质叠层。可以避免HF预清洗和SC1清洁，以提高非挥发性电荷陷阱存储器件的阻挡层的质量。在逻辑MOS栅极绝缘体层的热氧化或氮化期间，阻挡层可以被热再氧化或氮化，以致密封阻挡层。可以使用多层衬垫来首先在高压逻辑器件中偏置源极和漏极注入，并且还阻挡非易失性电荷陷阱存储器件的硅化。

10. 发明授权

US07898852B1 Trapped-charge non-volatile memory with uniform multilevel programming 有权
标题翻译：具有均匀多电平编程的陷阱充电非易失性存储器
公开(公告)号：US07898852B1
公开(公告)日：2011-03-01
申请号：US12005803
申请日：2007-12-27
申请人： Sagy Levy , Krishnaswamy Ramkumar , Peter Voss
发明人： Sagy Levy , Krishnaswamy Ramkumar , Peter Voss
IPC分类号： G11C16/04
CPC分类号： G11C16/0466 , G11C11/56 , H01L21/28282 , H01L29/42324 , H01L29/4234 , H01L29/7881 , H01L29/792
摘要： Methods and apparatus for programming and sensing a bi-nitride layer trapped-charge memory device in one of a first and second programmed states or one of a first and second erased states, where the first and second programmed states correspond to first and second uniform trapped charge distributions of a first charge type and the first and second erased states correspond to first and second uniform trapped charge distributions of a second charge type.
摘要翻译：用于以第一和第二编程状态或第一和第二擦除状态中的一种编程和感测二氮化物层捕获电荷存储器件的方法和装置，其中第一和第二编程状态对应于第一和第二均匀捕获第一充电类型和第一和第二擦除状态的电荷分布对应于第二充电类型的第一和第二均匀俘获电荷分布。

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