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1. 发明授权

US06555484B1 Method for controlling the oxidation of implanted silicon 失效
标题翻译：控制植入硅氧化的方法
公开(公告)号：US06555484B1
公开(公告)日：2003-04-29
申请号：US08878728
申请日：1997-06-19
申请人： Krishnaswamy Ramkumar , Hanna Bamnolker
发明人： Krishnaswamy Ramkumar , Hanna Bamnolker
IPC分类号： H01L21265
CPC分类号： H01L21/28185 , H01L21/2652 , H01L21/2822 , Y10S438/911 , Y10S438/92 , Y10S438/981
摘要： Two different regions of a semiconductor substrate are implanted with dopants/ions. The implantation may occur though a sacrificial oxide layer disposed over the substrate. Following implantation in one or both regions, the substrate may be annealed and the sacrificial oxide layer removed. An oxide layer is then grown over the implanted regions of the substrate. For some embodiments, the substrate may be implanted with arsenic and/or with phosphorus. Further, the anneal may be performed for approximately 30 to 120 minutes at a temperature between approximately 900° C. and 950° C.
摘要翻译：用掺杂剂/离子注入半导体衬底的两个不同区域。注入可以通过设置在衬底上的牺牲氧化层发生。在一个或两个区域中植入之后，可以对衬底进行退火并去除牺牲氧化物层。然后在衬底的注入区域上生长氧化物层。对于一些实施例，衬底可以用砷和/或磷进行注入。此外，退火可以在约900℃至950℃的温度下进行约30至120分钟。

2. 发明授权

US6004399A Ultra-low particle semiconductor cleaner for removal of particle contamination and residues from surface oxide formation on semiconductor wafers 失效
标题翻译：用于去除颗粒污染的超低颗粒半导体清洁剂和半导体晶片上表面氧化物形成的残留物
公开(公告)号：US6004399A
公开(公告)日：1999-12-21
申请号：US784207
申请日：1997-01-15
申请人： Kaichiu Wong , Krishnaswamy Ramkumar , Hanna Bamnolker , Suraj Puri , Rajiv Bhushan , David Wong , Gary Elmore , Raj Mohindra
发明人： Kaichiu Wong , Krishnaswamy Ramkumar , Hanna Bamnolker , Suraj Puri , Rajiv Bhushan , David Wong , Gary Elmore , Raj Mohindra
IPC分类号： B08B3/04 , B08B3/10 , B08B3/12 , H01L21/00 , B08B3/08
CPC分类号： H01L21/67057 , B08B3/04 , B08B3/102 , B08B3/12 , H01L21/67051 , Y10S134/902
摘要： A method is described for cleaning a semiconductor wafer. The method includes immersing a wafer in a liquid comprising water. The wafer has a front face, a back face, and an edge. The method also includes providing a substantially particle free environment adjacent to the front face and the back face as the liquid is being removed. A step of introducing a carrier gas comprising a cleaning enhancement substance also is included. It is believed that the cleaning enhancement substance dopes any liquid adhered to the front and back faces of the wafer to cause a concentration gradient of the cleaning enhancement substance in the liquid and accelerate removal of the adhered liquid off of the water.
摘要翻译：描述了一种用于清洁半导体晶片的方法。该方法包括将晶片浸入包含水的液体中。晶片具有前表面，后表面和边缘。该方法还包括当正在除去液体时提供与前表面和背面相邻的基本上无颗粒的环境。还包括引入包含清洁增强物质的载气的步骤。相信清洁增强物质会粘附到晶片的正面和背面的任何液体，从而引起液体中清洁增强物质的浓度梯度，并加速从水中除去附着液体。

3. 发明授权

US06794269B1 Method for and structure formed from fabricating a relatively deep isolation structure 有权
标题翻译：通过制造相对较深的隔离结构形成的方法和结构
公开(公告)号：US06794269B1
公开(公告)日：2004-09-21
申请号：US10324989
申请日：2002-12-20
申请人： Prabhuram Gopalan , Biju Parameshwaran , Krishnaswamy Ramkumar , Hanna Bamnolker , Sundar Narayanan
发明人： Prabhuram Gopalan , Biju Parameshwaran , Krishnaswamy Ramkumar , Hanna Bamnolker , Sundar Narayanan
IPC分类号： H01L2176
CPC分类号： H01L21/763 , H01L21/76202
摘要： A method is provided which includes forming a deep isolation structure within a semiconductor topography. In some cases, the method may include forming a first isolation structure within a semiconductor layer and etching an opening within the isolation structure to expose the semiconductor layer. In addition, the method may include etching the semiconductor layer to form a trench extending through the isolation structure and at least part of the semiconductor layer. In some cases, the method may include removing part of a first fill layer deposited within the trench such that an upper surface of the fill layer is below an upper portion of the trench. In such an embodiment, the vacant portion of the trench may be filled with a second fill layer. In yet other embodiments, the method may include planarizing the first fill layer within the trench and subsequently oxidizing an upper portion of the fill layer.
摘要翻译：提供了一种方法，其包括在半导体形貌内形成深度隔离结构。在一些情况下，该方法可以包括在半导体层内形成第一隔离结构并蚀刻隔离结构内的开口以暴露半导体层。此外，该方法可以包括蚀刻半导体层以形成延伸穿过隔离结构和半导体层的至少一部分的沟槽。在一些情况下，该方法可以包括去除沉积在沟槽内的第一填充层的部分，使得填充层的上表面在沟槽的上部下方。在这样的实施例中，沟槽的空缺部分可以填充第二填充层。在其他实施例中，该方法可以包括平坦化沟槽内的第一填充层，随后氧化填充层的上部。

4. 发明授权

US07129178B1 Reducing defect formation within an etched semiconductor topography 有权
标题翻译：减少蚀刻半导体形貌内的缺陷形成
公开(公告)号：US07129178B1
公开(公告)日：2006-10-31
申请号：US10074888
申请日：2002-02-13
申请人： Benjamin C. E. Schwarz , Chan Lon Yan , Hanna Bamnolker , Daniel J. Arnzen
发明人： Benjamin C. E. Schwarz , Chan Lon Yan , Hanna Bamnolker , Daniel J. Arnzen
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/32136 , H01L21/31116 , H01L21/31138 , H01L21/32137
摘要： A method is provided which includes etching one or more layers in an etch chamber while introducing a noble gas heavier than helium into the etch chamber. In a preferred embodiment, the introduction of such a noble gas may reduce the formation of defects within an etched portion of the semiconductor topography. Such defects may include bilayer mounds of nitride and a material comprising silicon, for example. In some embodiments, the method may include etching a stack of layers within a single etch chamber. The stack of layers may include, for example, a nitride layer interposed between an anti-reflective layer and an underlying layer. In addition, the single etch chamber may be a plasma etch chamber designed to etch materials comprising silicon. As such, the method may include etching an anti-reflective layer in a plasma etch chamber designed to etch materials comprising silicon.
摘要翻译：提供了一种方法，其包括在蚀刻室中蚀刻一个或多个层，同时将比氦更重的惰性气体引入蚀刻室。在优选实施例中，引入这种惰性气体可以减少半导体形貌的蚀刻部分内的缺陷的形成。这样的缺陷可以包括例如氮化物的双层堆积物和包含硅的材料。在一些实施例中，该方法可以包括在单个蚀刻室内蚀刻一层层。层叠层可以包括例如介于抗反射层和下层之间的氮化物层。此外，单蚀刻室可以是设计用于蚀刻包含硅的材料的等离子体蚀刻室。因此，该方法可以包括在设计成蚀刻包含硅的材料的等离子体蚀刻室中蚀刻抗反射层。

5. 发明授权

US6103379A Process for the preparation of microspheres and microspheres made thereby 失效
标题翻译：由此制备微球和微球的方法
公开(公告)号：US6103379A
公开(公告)日：2000-08-15
申请号：US809957
申请日：1997-04-03
申请人： Shlomo Margel , Hanna Bamnolker
发明人： Shlomo Margel , Hanna Bamnolker
IPC分类号： B01J13/14 , G01N33/543 , B32B5/16
CPC分类号： G01N33/54346 , B01J13/14 , B82Y5/00 , G01N33/5434 , G01N2333/8125 , G01N2446/10 , G01N2446/80 , G01N2446/86 , G01N2446/90 , Y10T428/2991 , Y10T428/2993 , Y10T428/2998
摘要： A process for the preparation of a microsphere comprising a coating composed of one or more silica nanoparticles layers, comprises the steps of: a) providing a microsphere of polymeric material, the said microsphere having adsorbed on its surface one or more surfactants; and b) causing a layer of silica nanoparticles to coat the surface of the said microsphere by means of seeded polymerization of alkyl silicates onto the surface of said microsphere.
摘要翻译： PCT No.PCT / US95 / 12988 Sec。 371日期1997年4月3日 102（e）日期1997年4月3日PCT提交1995年10月5日PCT公布。公开号WO96 / 11054 日期1996年04月18日制备包含由一个或多个二氧化硅纳米粒子层组成的涂层的微球的方法包括以下步骤：a）提供聚合物材料的微球，所述微球在其表面上吸附一个或多个表面活性剂和b）使二氧化硅纳米颗粒层通过在所述微球表面上的硅烷化硅的接合聚合来涂覆所述微球的表面。

6. 发明授权

US06756315B1 Method of forming contact openings 有权
标题翻译：形成接触孔的方法
公开(公告)号：US06756315B1
公开(公告)日：2004-06-29
申请号：US09672836
申请日：2000-09-29
申请人： Hanna Bamnolker , Prashant Phatak , Usha Raghuram , Sam Geha
发明人： Hanna Bamnolker , Prashant Phatak , Usha Raghuram , Sam Geha
IPC分类号： H01L21302
CPC分类号： H01L21/02063 , H01L21/76802 , H01L21/76814
摘要： The present invention provides a method of forming, in semiconductor substrates, contact openings having low contact resistance. The method involves, in particular, the introduction of a “soft etch” cleaning step that is used to clean the bottom of the contact openings. The “soft etch” cleaning step uses fluorocarbon chemistry. It is shown that the resulting resistance of the contact openings is reduced.
摘要翻译：本发明提供了一种在半导体衬底中形成具有低接触电阻的接触开口的方法。该方法特别涉及引入用于清洁接触开口底部的“软蚀刻”清洁步骤。 “软蚀刻”清洁步骤使用碳氟化合物。显示出所产生的接触开口的电阻降低。

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