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41. 发明授权

US06304207B1 Cyclic analog to digital converter with mis-operational detector 失效
标题翻译：具有误操作检测器的循环模数转换器
公开(公告)号：US06304207B1
公开(公告)日：2001-10-16
申请号：US09432252
申请日：1999-11-02
申请人： Dae Hun Lee
发明人： Dae Hun Lee
IPC分类号： H03M106
CPC分类号： H03M1/0687 , H03M1/40
摘要： A cyclic analog/digital converter includes a first multiplexer for selectively outputting an analog signal and a first input signal pursuant to a control signal; a sample/hold unit for sampling/holding an output signal from the first multiplexer; a doubling amplifier for amplifying an output signal from the sample/hold unit; a first comparator for comparing an output signal from the doubling amplifier with a reference voltage; a second multiplexer for selectively outputting the reference voltage and a ground voltage pursuant to an output signal from the first comparator; a voltage subtracter for subtracting output signals from the doubling amplifier and the second multiplexer, and providing the first input signal to the first multiplexer; and a mis-operation detector for detecting a mis-operation of the first comparator, and controlling an operation of the first multiplexer.
摘要翻译：循环模拟/数字转换器包括：第一多路复用器，用于根据控制信号选择性地输出模拟信号和第一输入信号; 用于对来自第一多路复用器的输出信号进行采样/保持的采样/保持单元; 用于放大来自采样/保持单元的输出信号的双倍放大器; 第一比较器，用于将倍增放大器的输出信号与参考电压进行比较; 第二多路复用器，用于根据来自第一比较器的输出信号选择性地输出参考电压和接地电压; 减法器，用于从双倍放大器和第二多路复用器中减去输出信号，并将第一输入信号提供给第一多路复用器; 以及用于检测第一比较器的误操作并控制第一多路复用器的操作的误操作检测器。

42. 发明授权

US06297757B1 Method and circuit for testing an analog-to-digital converter module on a data processing system having an intermodule bus 有权
标题翻译：用于在具有模块间总线的数据处理系统上测试模拟 - 数字转换器模块的方法和电路
公开(公告)号：US06297757B1
公开(公告)日：2001-10-02
申请号：US09248551
申请日：1999-02-11
申请人： Jules D. Campbell, Jr. , Jiang Chen , Robert S. Jones, III , Christian Ahrens , Scott Willard Herrin
发明人： Jules D. Campbell, Jr. , Jiang Chen , Robert S. Jones, III , Christian Ahrens , Scott Willard Herrin
IPC分类号： H03M106
CPC分类号： H03M1/108 , H03M1/12
摘要： A data processing system (20) includes a plurality of modules (44, 48) and an analog-to-digital converter (ADC) (46). The ADC (46) includes at least one port terminal (66) for transmitting test information from the ADC (46). The plurality of modules (44,48) and the ADC (46) are coupled to a central processing unit (CPU) (22) via an intermodule bus (42). A tester can exchange test information with the ADC (46) directly through the port terminal (66) instead of using the intermodule bus (42). Also, various sub-modules (62, 64, 60, 74) of the ADC (46) can be independently tested without performing a conversion process.
摘要翻译：数据处理系统（20）包括多个模块（44,48）和模数转换器（ADC）（46）。 ADC（46）包括用于从ADC（46）发送测试信息的至少一个端口（66）。多个模块（44,48）和ADC（46）经由模块间总线（42）耦合到中央处理单元（CPU）（22）。测试人员可以直接通过端口（66）与ADC（46）交换测试信息，而不是使用模块间总线（42）。此外，可以独立地测试ADC（46）的各个子模块（62,64,60,74），而不进行转换处理。

43. 发明授权

US06255976B1 Low-frequency noise removing method and a related CMOS sensing circuit 有权
标题翻译：低频噪声去除方法和相关的CMOS感测电路
公开(公告)号：US06255976B1
公开(公告)日：2001-07-03
申请号：US09427549
申请日：1999-10-27
申请人： Takamoto Watanabe , Toshio Ikuta , Noboru Endo
发明人： Takamoto Watanabe , Toshio Ikuta , Noboru Endo
IPC分类号： H03M106
CPC分类号： G04F10/005 , H03M1/0619 , H03M1/14 , H03M1/502 , H03M1/60
摘要： An intentional offset value is set beforehand. The intentional offset value is larger than a sensing objective signal “sig.” A measuring device is provided for measuring the intentional offset value to obtain a measured intentional offset value “a” representing the quantity of the intentional offset value, and also for measuring a sum of the sensing objective signal “sig” and the intentional offset value to obtain a measured signal value “b” representing a summation of the quantity of the sensing objective signal and the quantity of the intentional offset value. A ratio (b/a) of the measured signal value to the measured intentional offset value is obtained. The obtained ratio is used as noise reducing data for reducing the noise involved in a sensor output.
摘要翻译：预先设定有意偏移值。有意的偏移值大于感测对象信号“sig”。提供测量装置用于测量有意偏移值以获得表示有意偏移值的量的测量人为偏移值“a”，并且还用于测量感测目标信号“sig”和人为偏移值之和获得表示感测对象信号的量与有意偏移值的量的和的测量信号值“b”。获得测量信号值与测量的人为偏移值的比率（b / a）。所获得的比值被用作降低传感器输出中所涉及的噪声的降噪数据。

44. 发明授权

US06232897B1 System and method for calibrating an analog to digital converter through stimulation of current generators 有权
标题翻译：通过激励电流发生器校准模数转换器的系统和方法
公开(公告)号：US06232897B1
公开(公告)日：2001-05-15
申请号：US09351759
申请日：1999-07-12
申请人： Niels Knusen
发明人： Niels Knusen
IPC分类号： H03M106
CPC分类号： H03M3/388 , H03M3/424 , H03M3/458
摘要： A system and method for calibrating an analog to digital (A/D) converter. The A/D converter includes an internal D/A converter, wherein the internal D/A converter includes a plurality of current generators, and wherein one or more of the current generators may produce linearity errors in the A/D converter. The A/D converter includes a switching element connected to the internal D/A converter. During calibration, the switching element operates to adjust connections to the current generators in the internal D/A converter one or more times according to different switching patterns, thereby causing different ones of the current generators to be stimulated by an input to the A/D converter. This avoids the necessity of using a complex and costly waveform generator input during calibration, which would normally be required to ensure that all of the current generators in the internal D/A converter are stimulated. Rather, a much simpler input can be used in calibrating the A/D converter, thereby reducing cost. A plurality of output digital signals from the A/D converter are recorded during calibration, wherein these recorded signals contain linearity error information associated with the respective current generators. This linearity error information may be extracted and used in calibrating the A/D converter.
摘要翻译：一种用于校准模数（A / D）转换器的系统和方法。 A / D转换器包括内部D / A转换器，其中内部D / A转换器包括多个电流发生器，并且其中一个或多个电流发生器可能在A / D转换器中产生线性误差。 A / D转换器包括连接到内部D / A转换器的开关元件。在校准期间，开关元件工作以根据不同的开关模式调节与内部D / A转换器中的电流发生器的连接一次或多次，从而使得不同的电流发生器被A / D的输入激励转换器。这避免了在校准期间需要使用复杂且昂贵的波形发生器输入，通常需要这样来确保内部D / A转换器中的所有电流发生器被激励。相反，可以使用更简单的输入来校准A / D转换器，从而降低成本。在校准期间记录来自A / D转换器的多个输出数字信号，其中这些记录信号包含与各个电流发生器相关联的线性误差信息。该线性误差信息可以被提取并用于校准A / D转换器。

45. 发明授权

US06198416B1 Linearity error compensator 有权
标题翻译：线性误差补偿器
公开(公告)号：US06198416B1
公开(公告)日：2001-03-06
申请号：US09548069
申请日：2000-04-12
申请人： Scott R. Velazquez
发明人： Scott R. Velazquez
IPC分类号： H03M106
CPC分类号： H03M1/0614 , H03M1/12
摘要： In one aspect, the present invention is directed to a compensator for compensating linearity errors, such as harmonic distortion and intermodulation distortion, in devices. The compensator includes a means for phase-shifting and a means for exponentiation to generate a compensation signal such that the linearity error distortion signals are canceled in the system output while maintaining the desired fundamental signal. Another aspect of the invention is directed to methods for calibrating the linearity error compensator. Another aspect of the invention is directed to a modeling linearity errors in a device.
摘要翻译：一方面，本发明涉及用于补偿装置中的线性误差（诸如谐波失真和互调失真）的补偿器。补偿器包括用于相移的装置和用于求幂的装置以产生补偿信号，使得线性误差失真信号在系统输出中被消除，同时保持期望的基本信号。本发明的另一方面涉及校准线性误差补偿器的方法。本发明的另一方面涉及一种设备中的建模线性误差。

46. 发明授权

US06181263B2 Signal processor 有权
标题翻译：信号处理器
公开(公告)号：US06181263B2
公开(公告)日：2001-01-30
申请号：US09258534
申请日：1999-02-26
申请人： Hassan Malik , William C. Rempfer , James L. Brubaker
发明人： Hassan Malik , William C. Rempfer , James L. Brubaker
IPC分类号： H03M106
CPC分类号： H03M1/06 , H03M1/785
摘要： A switch impedance insensitive signal processor is provided. A signal processor according to the present invention overcomes the problem of switch impedance by adding an individual buffer, e.g. a unity-gain amplifier, between the switch and the processor portion of the circuit. The buffer isolates the signal processor from the switch impedance.
摘要翻译：提供开关阻抗不敏感信号处理器。根据本发明的信号处理器通过添加单个缓冲器来克服开关阻抗的问题，例如，在电路的开关和处理器部分之间的单位增益放大器。缓冲器将信号处理器与开关阻抗隔离开来。

47. 发明授权

US06836227B2 Digitizer module, a waveform generating module, a converting method, a waveform generating method and a recording medium for recording a program thereof 失效
标题翻译：数字化器模块，波形发生模块，转换方法，波形生成方法和用于记录其程序的记录介质
公开(公告)号：US06836227B2
公开(公告)日：2004-12-28
申请号：US10374769
申请日：2003-02-25
申请人： Koji Asami
发明人： Koji Asami
IPC分类号： H03M106
CPC分类号： H03M1/0836 , H03M1/12
摘要： A digitizer module comprises an AD converter for sampling a pair of analog signals at a predetermined time interval and converting into a first and second digital signals respectively, a second signal frequency component calculating unit for calculating a second signal frequency component representing a component of each frequency of the second digital signal on the basis of the second digital signal, a skew frequency component calculating unit for calculating a skew frequency component representing a phase error of each frequency of the second digital signal corresponding to the first digital signal on the basis of a skew of a timing with which the pair of analog signals are sampled by the AD converter and a second signal frequency component correcting unit for correcting the second signal frequency component on the basis of the skew frequency component.
摘要翻译：数字转换器模块包括一个AD转换器，用于以预定的时间间隔对一对模拟信号进行采样并分别转换成第一和第二数字信号;第二信号频率分量计算单元，用于计算表示每个频率的分量的第二信号频率分量基于第二数字信号的第二数字信号的偏移频率分量计算单元，用于基于歪斜来计算表示对应于第一数字信号的第二数字信号的每个频率的相位误差的偏斜频率分量所述AD转换器对所述一对模拟信号进行采样的定时，以及用于基于所述偏斜频率分量校正所述第二信号频率分量的第二信号频率分量校正单元。

48. 发明授权

US06778126B2 Structures and methods that improve the linearity of analog-to-digital converters with introduced nonlinearities 有权
标题翻译：通过引入非线性改善模数转换器的线性度的结构和方法
公开(公告)号：US06778126B2
公开(公告)日：2004-08-17
申请号：US10302173
申请日：2002-11-21
申请人： Ahmed Mohamed Abdelatty Ali
发明人： Ahmed Mohamed Abdelatty Ali
IPC分类号： H03M106
CPC分类号： H03M1/0612 , H03M1/167 , H03M1/442
摘要： Analog-to-digital converter (ADC) structures and methods are provided that reduce an initial converter nonlinearity by introducing an inverse nonlinearity into the converter's response that is substantially the inverse of the initial converter nonlinearity. In a pipelined ADC embodiment, for example, upstream converter stages are selected that generate an upstream digital code which defines sufficient upstream code words to designate respective segments of the inverse nonlinearity. In response to each of the upstream code words, the conversion gain of the remaining downstream converter stages is then sufficiently adjusted to insert the inverse nonlinearity into the converter response.
摘要翻译：提供了模数转换器（ADC）结构和方法，其通过将逆非线性引入到基本上与初始转换器非线性相反的转换器响应中来减少初始转换器非线性。在流水线ADC实施例中，例如，选择上游转换器级，其产生上游数字代码，其定义足够的上游代码字以指定逆非线性的相应段。响应于每个上游码字，然后充分调整剩余下游转换器级的转换增益，以将逆非线性插入转换器响应。

49. 发明授权

US06724331B1 Adaptive digital spectral compensation and calibration of analog components and transceiver chains 有权
标题翻译：模拟组件和收发器链的自适应数字频谱补偿和校准
公开(公告)号：US06724331B1
公开(公告)日：2004-04-20
申请号：US10304331
申请日：2002-11-26
申请人： Hussein S. El-Ghoroury , Murat F. Karsi
发明人： Hussein S. El-Ghoroury , Murat F. Karsi
IPC分类号： H03M106
CPC分类号： H03M1/0626 , H03M1/1038
摘要： According to one aspect of the invention, an apparatus is provided which includes one or more analog components, an analog to digital (A/D) converter, and a spectral compensator. The operational characteristics of the one or more analog components have variations based on input signal frequency. The one or more analog components perform their corresponding operations with respect to an input analog signal to generate an output analog signal. The analog to digital (A/D) converter is coupled to receive the output analog signal from the one or more analog components and to convert the output analog signal to a digital signal. The spectral compensator is coupled to receive the digital signal generated by the A/D converter and to compensate spectral characteristics of the digital signal based on variations in the operational characteristics of the one or more analog components.
摘要翻译：根据本发明的一个方面，提供一种包括一个或多个模拟组件，模数（A / D）转换器和频谱补偿器的装置。一个或多个模拟组件的操作特性具有基于输入信号频率的变化。一个或多个模拟组件相对于输入模拟信号进行相应的操作以产生输出模拟信号。模数（A / D）转换器被耦合以从一个或多个模拟组件接收输出模拟信号，并将输出模拟信号转换为数字信号。频谱补偿器被耦合以接收由A / D转换器产生的数字信号，并且基于一个或多个模拟部件的操作特性的变化来补偿数字信号的频谱特性。

50. 发明授权

US06593864B1 Digital-to-analog converter with temperature compensation 失效
标题翻译：具有温度补偿功能的数模转换器
公开(公告)号：US06593864B1
公开(公告)日：2003-07-15
申请号：US10124114
申请日：2002-04-15
申请人： Timothy J. Reilly
发明人： Timothy J. Reilly
IPC分类号： H03M106
CPC分类号： H03M1/089 , H03M1/822
摘要： A PWM DAC including an emitter follower buffer circuit provides increased accuracy and reduced cost. The emitter follower buffer circuit that enables inexpensive implementation of the PWM DAC. A temperature compensation circuit adjusts the digital input value applied to the PWM to compensate for temperature-induced variation introduced by the emitter follower buffer circuit. The compensation circuit may incorporate circuitry that replicates the PWM DAC at least in part, and monitors the base-emitter voltage of a replicated emitter follower buffer to track temperature-induced variation in the PWM DAC. The compensation circuit generates an error value that can be used to compensate one or more PWM DACs within a particular system.
摘要翻译：包括射极跟随器缓冲电路的PWM DAC提供更高的精度并降低成本。射极跟随器缓冲电路，可实现廉价的PWM DAC实现。温度补偿电路调整施加到PWM的数字输入值，以补偿由射极跟随器缓冲电路引入的温度引起的变化。补偿电路可以包括至少部分地复制PWM DAC的电路，并且监视复制射极跟随器缓冲器的基极 - 发射极电压以跟踪PWM DAC中的温度引起的变化。补偿电路产生可用于补偿特定系统内的一个或多个PWM DAC的误差值。

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