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1. 发明申请

US20110210877A1 CALIBRATION METHODS AND STRUCTURES FOR PIPELINED CONVERTER SYSTEMS 有权
标题翻译：用于管道转换器系统的校准方法和结构
公开(公告)号：US20110210877A1
公开(公告)日：2011-09-01
申请号：US12715102
申请日：2010-03-01
申请人： Ahmed Mohamed Abdelatty Ali , Andrew Stacy Morgan
发明人： Ahmed Mohamed Abdelatty Ali , Andrew Stacy Morgan
IPC分类号： H03M1/10
CPC分类号： H03M1/1033 , H03M1/164
摘要： Calibration methods and structures are provided for pipelined analog-to-digital converter systems. They are arranged to process samples of the digital codes with an algorithm that is preferably configured to repeatedly update an estimate of the transfer function with the difference between one of the input signals and the analog equivalent of the corresponding digital code. The calibration methods and structures are further configured to calibrate the transfer function of the converter stage wherein the samples are selected in accordance with various steps. These steps can include the step of injecting dither signals into a flash portion and an MDAC portion of the converter stage to thereby maintain dynamic range. They can also include the step of limiting the samples to those processed through a selected subrange of the subranges. They can further include the step of limiting the samples to those in which the absolute value of the input signals is less that 0.25 of the selected subrange and the absolute value of the dither signals is less that 0.25 of the selected subrange. If the selected subrange is not a central subrange, the steps can further include the step of shifting the samples by a distance between the selected subrange and the central subrange.
摘要翻译：为流水线模数转换器系统提供校准方法和结构。它们被布置成用算法处理数字代码的样本，该算法优选地被配置为用输入信号中的一个和对应的数字代码的模拟等效物之间的差重复更新传递函数的估计。校准方法和结构还被配置为校准转换器级的传递函数，其中根据各种步骤选择样本。这些步骤可以包括将抖动信号注入转换器级的闪存部分和MDAC部分，从而保持动态范围的步骤。它们还可以包括将样品限制在通过所选子范围的子范围进行处理的样品的步骤。它们还可以包括将样本限制为其中输入信号的绝对值小于所选子范围的0.25并且抖动信号的绝对值小于所选子范围的0.25的步骤。如果选择的子范围不是中央子范围，则步骤还可以包括将样本移位所选子范围和中心子范围之间的距离的步骤。

2. 发明授权

US07830288B2 Fast, efficient reference networks for providing low-impedance reference signals to signal processing systems 有权
标题翻译：快速，高效的参考网络，用于向信号处理系统提供低阻抗参考信号
公开(公告)号：US07830288B2
公开(公告)日：2010-11-09
申请号：US12692967
申请日：2010-01-25
申请人： Gregory W. Patterson , Ahmed Mohamed Abdelatty Ali
发明人： Gregory W. Patterson , Ahmed Mohamed Abdelatty Ali
IPC分类号： H03M1/00
CPC分类号： G05F1/56 , H03M1/164 , H03M1/44
摘要： Reference network embodiments are provided for use in pipelined signal converter systems. The network embodiments are fast and power efficient and they generate low-impedance reference signals through the use of at least one output transistor, a diode-coupled transistor coupled to the output transistor, and a controller. The controller is configured to provide a backgate voltage to the diode-coupled transistor to thereby establish a substantially-constant output current. The controller is further configured to provide a gate voltage to the output transistor to establish a reference voltage.
摘要翻译：参考网络实施例被提供用于流水线信号转换器系统。网络实施例是快速和功率有效的，并且它们通过使用至少一个输出晶体管，耦合到输出晶体管的二极管耦合晶体管和控制器来产生低阻抗参考信号。控制器被配置为向二极管耦合晶体管提供背栅电压，从而建立基本上恒定的输出电流。控制器还被配置为向输出晶体管提供栅极电压以建立参考电压。

3. 发明授权

US07728752B2 Residue generators for reduction of charge injection in pipelined converter systems 有权
标题翻译：用于减少流水线转换器系统中的电荷注入的残渣发生器
公开(公告)号：US07728752B2
公开(公告)日：2010-06-01
申请号：US12291262
申请日：2008-11-05
申请人： Ahmed Mohamed Abdelatty Ali , Gregory W. Patterson
发明人： Ahmed Mohamed Abdelatty Ali , Gregory W. Patterson
IPC分类号： H03M1/38
CPC分类号： H03M1/0863 , H03M1/164 , H03M1/442
摘要： Pipelined converter systems include a plurality of converter stages in which some stages generate and pass a residue signal to a succeeding stage for further conversion. The generation of the residue signal can inject spurious charges into a reference source that is used in the generation. The spurious charges reduce the accuracy of the residue signal and the accuracy of the system. Residue generator embodiments are thereby formed to provide reduction charges to the reference source that are arranged to oppose and reduce the spurious charges. This reduction of spurious charges significantly enhances system accuracy and linearity.
摘要翻译：流水线转换器系统包括多个转换器级，其中一些级产生残余信号并将其传递到后一级用于进一步转换。残留信号的产生可以将杂散电荷注入到在生成中使用的参考源中。杂散电荷降低了残留信号的准确度和系统的精度。由此形成残留发生器实施例，以向参考源提供被布置为反对并减少杂散电荷的减少电荷。这种减少杂散电荷显着提高了系统的精度和线性。

4. 发明授权

US07414564B1 Enhanced-accuracy converter stages for pipelined signal converter systems 有权
标题翻译：用于流水线信号转换器系统的增强型精度转换器级
公开(公告)号：US07414564B1
公开(公告)日：2008-08-19
申请号：US11820298
申请日：2007-06-18
申请人： Ahmed Mohamed Abdelatty Ali
发明人： Ahmed Mohamed Abdelatty Ali
IPC分类号： H03M1/38
CPC分类号： H03M1/0607 , H03M1/0695 , H03M1/44
摘要： Converter systems are provided which complement sample capacitors in at least one converter stage with replica capacitors. The replica capacitors are switched to receive replica charges from the analog input signal during the same operational mode in which the sample capacitors receive undesirable remnant charges. In an initial portion of a subsequent operational mode, the remnant capacitors are briefly switched to the sample capacitors to substantially cancel the remnant charges. The sample capacitors then participate in obtaining input-signal samples during the remainder of the subsequent operational mode. Because the remnant charges have been substantially canceled, the accuracy of the subsequent operational mode is considerably enhanced. In another system embodiment, the replica capacitor is replaced by a discharge switch which provides a discharge path in an initial portion of the subsequent operational mode.
摘要翻译：提供了转换器系统，其在具有复制电容器的至少一个转换器级中补充采样电容器。在相同的操作模式下，复制电容器被切换以从模拟输入信号接收副本电荷，其中采样电容器接收不期望的剩余电荷。在随后的操作模式的初始部分中，剩余电容器被短暂切换到采样电容器以基本上消除剩余电荷。然后，采样电容器在随后的操作模式的剩余时间期间参与获得输入信号采样。由于剩余费用已经被大幅度取消，所以后续操作模式的准确性显着提高。在另一系统实施例中，复制电容器由放电开关代替，该放电开关在后续操作模式的初始部分提供放电路径。

5. 发明授权

US09276534B2 High speed amplifier 有权
标题翻译：高速放大器
公开(公告)号：US09276534B2
公开(公告)日：2016-03-01
申请号：US14012165
申请日：2013-08-28
申请人： Ahmed Mohamed Abdelatty Ali
发明人： Ahmed Mohamed Abdelatty Ali
IPC分类号： H03F3/193 , H03F1/02 , H03F3/195
CPC分类号： H03F3/193 , H03F1/0266 , H03F3/1935 , H03F3/195 , H03F2200/18 , H03K2217/0018
摘要： A circuit may include one or more transistors connected directly to an output, and a biasing network connected to at least one of a substrate, a well, and a back-gate of at least one of the transistors. The biasing network may bias the at least one of the substrate, the well, and the back-gate to a virtual floating bias, such that the virtual floating bias shifts in voltage level based upon an AC input signal of the circuit, to reduce the parasitic capacitance of the output node of the circuit.
摘要翻译：电路可以包括直接连接到输出的一个或多个晶体管，以及连接到至少一个晶体管的衬底，阱和背栅中的至少一个的偏置网络。偏压网络可以将衬底，阱和后栅中的至少一个偏置到虚拟浮置偏置，使得虚拟浮置偏置基于电路的AC输入信号而在电压电平上偏移，以减少电路输出节点的寄生电容。

6. 发明授权

US08471740B2 Reducing the effect of non-linear kick-back in switched capacitor networks 有权
标题翻译：减少开关电容网络中非线性反冲的影响
公开(公告)号：US08471740B2
公开(公告)日：2013-06-25
申请号：US13314451
申请日：2011-12-08
申请人： Huseyin Dinc , Ahmed Mohamed Abdelatty Ali , Paritosh Bhoraskar
发明人： Huseyin Dinc , Ahmed Mohamed Abdelatty Ali , Paritosh Bhoraskar
IPC分类号： H03M1/10
CPC分类号： H03M1/0641 , H03M1/0863 , H03M1/167
摘要： A method and device involve a circuit having a switched capacitor network that is switchably connected to an input signal. A randomly determined amount of dither is injected into a circuit having a switched capacitor network that is switchably connected to an input signal. After injecting the dither, at least one correlation value is determined. The correlation value(s) indicates a degree of correlation between the injected dither and an output of the circuit. Distortion caused by an amount of charge kicked back into the circuit when the switched capacitor network is reconnected to the input signal may then be reduced. The reduction is calculated as a function of the correlation value(s).
摘要翻译：一种方法和装置涉及具有可切换地连接到输入信号的开关电容网络的电路。将随机确定的抖动量注入到具有可切换地连接到输入信号的开关电容器网络的电路中。注入抖动后，确定至少一个相关值。相关值（s）表示注入的抖动与电路的输出之间的相关程度。然后可以减少当开关电容器网络重新连接到输入信号时由电荷量引起的失真导致的电路失真。按照相关值（s）的函数计算减少量。

7. 发明授权

US08390487B2 System and method of analog-to-digital converters 有权
公开(公告)号：US08390487B2
公开(公告)日：2013-03-05
申请号：US13159734
申请日：2011-06-14
申请人： Ahmed Mohamed Abdelatty Ali
发明人： Ahmed Mohamed Abdelatty Ali
IPC分类号： H03M1/06
CPC分类号： H03M1/1014 , H03M1/1061 , H03M1/164
摘要： An analog-to-digital converter system that includes a pipeline of successively-cascaded signal converters, each operating alternatively in a first circuit configuration and a second circuit configuration, an error estimator coupled to the pipeline to receive the digitized error for estimating an amplifier gain of the present signal converter stage, and a code aligner/corrector that temporally aligns and corrects the digital codes received from the successively-cascaded signal converters to provide a digital out of the ADC system.

8. 发明授权

US07746171B2 Amplifier networks with controlled common-mode level and converter systems for use therewith 有权
公开(公告)号：US07746171B2
公开(公告)日：2010-06-29
申请号：US12220558
申请日：2008-07-25
申请人： Ahmed Mohamed Abdelatty Ali
发明人： Ahmed Mohamed Abdelatty Ali
IPC分类号： H03F3/45
CPC分类号： H03F3/45286 , H03F3/45802 , H03F3/45807 , H03F2203/45101 , H03F2203/45418 , H03F2203/45424 , H03F2203/45434 , H03F2203/45512 , H03F2203/45514 , H03F2203/45642 , H03F2203/45681 , H03F2203/45722
摘要： Effective control of the common-mode level of amplifiers is obtained through control structures (both closed-loop and open-loop structures) which are directed to various amplifier functions such as the reduction of amplifier loading, accurate sensing of common-mode levels, mitigation of headroom restraints, and proper transistor biasing. This common-mode control is especially useful in multiplying analog-to-digital converters (MDACs) of signal processing systems.

9. 发明申请

US20100149015A1 FAST, EFFICIENT REFERENCE NETWORKS FOR PROVIDING LOW-IMPEDANCE REFERENCE SIGNALS TO SIGNAL PROCESSING SYSTEMS 有权
标题翻译：快速，高效的参考网络，用于向信号处理系统提供低阻抗参考信号
公开(公告)号：US20100149015A1
公开(公告)日：2010-06-17
申请号：US12692967
申请日：2010-01-25
申请人： Gregory W. Patterson , Ahmed Mohamed Abdelatty Ali
发明人： Gregory W. Patterson , Ahmed Mohamed Abdelatty Ali
IPC分类号： H03M1/12 , G05F1/00
CPC分类号： G05F1/56 , H03M1/164 , H03M1/44
摘要： Reference network embodiments are provided for use in pipelined signal converter systems. The network embodiments are fast and power efficient and they generate low-impedance reference signals through the use of at least one output transistor, a diode-coupled transistor coupled to the output transistor, and a controller. The controller is configured to provide a backgate voltage to the diode-coupled transistor to thereby establish a substantially-constant output current. The controller is further configured to provide a gate voltage to the output transistor to establish a reference voltage.
摘要翻译：参考网络实施例被提供用于流水线信号转换器系统。网络实施例是快速和功率有效的，并且它们通过使用至少一个输出晶体管，耦合到输出晶体管的二极管耦合晶体管和控制器来产生低阻抗参考信号。控制器被配置为向二极管耦合晶体管提供背栅电压，从而建立基本上恒定的输出电流。控制器还被配置为向输出晶体管提供栅极电压以建立参考电压。

10. 发明授权

US07719452B2 Pipelined converter systems with enhanced linearity 有权
公开(公告)号：US07719452B2
公开(公告)日：2010-05-18
申请号：US12284672
申请日：2008-09-23
申请人： Scott Gregory Bardsley , Bryan Scott Puckett , Michael Ray Elliott , Ravi Kishore Kummaraguntla , Ahmed Mohamed Abdelatty Ali , Carroll Clifton Speir , James Carroll Camp
发明人： Scott Gregory Bardsley , Bryan Scott Puckett , Michael Ray Elliott , Ravi Kishore Kummaraguntla , Ahmed Mohamed Abdelatty Ali , Carroll Clifton Speir , James Carroll Camp
IPC分类号： H03M1/20
CPC分类号： H03M1/0695 , H03M1/0641 , H03M1/167 , H03M1/365 , H03M1/44 , H03M1/806
摘要： Signal converter system embodiments are provided to substantially reduce symmetrical and asymmetrical conversion errors. Signal-processing stages of these embodiments may include a signal sampler in addition to successively-arranged signal converters. In system embodiments, injected analog dither signals are initiated in response to a random digital code. They combine with a system's analog input signal and the combined signal is processed down randomly-selected signal-processing paths of the converter system to thereby realize significant improvements in system linearity. Because these linearity improvements are realized by simultaneous processing of the input signal and the injected dither signal, a combined digital code is realized at the system's output. A first portion of this combined digital code corresponds to the analog input signal and a second portion corresponds to the injected analog dither signal. The final system digital code is realized by subtracting out the second portion with a back-end decoder that responds to the random digital code.

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