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1. 发明授权

US06255976B1 Low-frequency noise removing method and a related CMOS sensing circuit 有权
标题翻译：低频噪声去除方法和相关的CMOS感测电路
公开(公告)号：US06255976B1
公开(公告)日：2001-07-03
申请号：US09427549
申请日：1999-10-27
申请人： Takamoto Watanabe , Toshio Ikuta , Noboru Endo
发明人： Takamoto Watanabe , Toshio Ikuta , Noboru Endo
IPC分类号： H03M106
CPC分类号： G04F10/005 , H03M1/0619 , H03M1/14 , H03M1/502 , H03M1/60
摘要： An intentional offset value is set beforehand. The intentional offset value is larger than a sensing objective signal “sig.” A measuring device is provided for measuring the intentional offset value to obtain a measured intentional offset value “a” representing the quantity of the intentional offset value, and also for measuring a sum of the sensing objective signal “sig” and the intentional offset value to obtain a measured signal value “b” representing a summation of the quantity of the sensing objective signal and the quantity of the intentional offset value. A ratio (b/a) of the measured signal value to the measured intentional offset value is obtained. The obtained ratio is used as noise reducing data for reducing the noise involved in a sensor output.
摘要翻译：预先设定有意偏移值。有意的偏移值大于感测对象信号“sig”。提供测量装置用于测量有意偏移值以获得表示有意偏移值的量的测量人为偏移值“a”，并且还用于测量感测目标信号“sig”和人为偏移值之和获得表示感测对象信号的量与有意偏移值的量的和的测量信号值“b”。获得测量信号值与测量的人为偏移值的比率（b / a）。所获得的比值被用作降低传感器输出中所涉及的噪声的降噪数据。

2. 发明授权

US06307496B1 Sensing apparatus including an A/D conversion circuit for detecting a physical quantity 有权
标题翻译：包括用于检测物理量的A / D转换电路的检测装置
公开(公告)号：US06307496B1
公开(公告)日：2001-10-23
申请号：US09411319
申请日：1999-10-04
申请人： Toshio Ikuta , Noboru Endo , Takamoto Watanabe
发明人： Toshio Ikuta , Noboru Endo , Takamoto Watanabe
IPC分类号： H03M112
CPC分类号： H03M1/60 , G01D3/022 , G01D3/0365
摘要： An analog multiplexer is provided to time divisionally process a reference signal Sa obtained from a reference voltage generating circuit, a temperature signal St obtained from a temperature detecting bridge circuit, and a sensor signal Sd obtained from a pressure detecting bridge circuit. These signals Sa, St and Sd are converted into digital data through a common differential amplification circuit and a common A/D conversion circuit. A correction circuit calculates an applied pressure value based on the digital data produced from the A/D conversion circuit, as a value corrected with reference to the temperature signal St and the reference signal Sa.
摘要翻译：提供模拟多路复用器，以分时处理从参考电压产生电路获得的参考信号Sa，从温度检测桥接电路获得的温度信号St和从压力检测桥接电路获得的传感器信号Sd。这些信号Sa，St和Sd通过公共差分放大电路和公共A / D转换电路转换成数字数据。校正电路根据由A / D转换电路产生的数字数据计算施加的压力值，作为参考温度信号St和参考信号Sα校正的值。

3. 发明申请

US20070103356A1 Analog to digital converter with a series of inverting elements 失效
标题翻译：具有一系列反相元件的模数转换器
公开(公告)号：US20070103356A1
公开(公告)日：2007-05-10
申请号：US11586653
申请日：2006-10-26
申请人： Yasuaki Makino , Noboru Endo , Takamoto Watanabe , Mitsuharu Kato
发明人： Yasuaki Makino , Noboru Endo , Takamoto Watanabe , Mitsuharu Kato
IPC分类号： H03M1/12
CPC分类号： H03M1/0836 , G04F10/005 , H03M1/14 , H03M1/502 , H03M1/60
摘要： An A/D converter has inverting elements and delay elements alternately disposed in series. Each inverting element receives an analog voltage signal as a power source and converts a pulse signal in an inversion operation time depending on the analog voltage signal. Each delay element delays transmission of the pulse signal. The transmission of the pulse signal is started from a starting inverting element at a start time, and a transit position of the pulse signal is detected at a detection time later than the start time by a predetermined time. A digital value indicating a level of the analog voltage signal is determined from the detected transit position of the pulse signal. Because transmission of the pulse signal is delayed by the delay elements, the transit position depending on the analog voltage signal can be correctly detected.
摘要翻译： A / D转换器具有交替设置的反相元件和延迟元件。每个反相元件接收模拟电压信号作为电源，并根据模拟电压信号在反转操作时间中转换脉冲信号。每个延迟元件延迟脉冲信号的传输。脉冲信号的发送在开始时从启动反转元件开始，并且在比开始时间晚一个预定时间的检测时间检测脉冲信号的转接位置。从检测到的脉冲信号的转接位置确定表示模拟电压信号的电平的数字值。由于脉冲信号的传输被延迟元件延迟，所以可以正确地检测取决于模拟电压信号的传输位置。

4. 发明授权

US07345614B2 Analog to digital converter with a series of inverting elements 失效
标题翻译：具有一系列反相元件的模数转换器
公开(公告)号：US07345614B2
公开(公告)日：2008-03-18
申请号：US11586653
申请日：2006-10-26
申请人： Yasuaki Makino , Noboru Endo , Takamoto Watanabe , Mitsuharu Kato
发明人： Yasuaki Makino , Noboru Endo , Takamoto Watanabe , Mitsuharu Kato
IPC分类号： H03M1/60
CPC分类号： H03M1/0836 , G04F10/005 , H03M1/14 , H03M1/502 , H03M1/60
摘要： An A/D converter has inverting elements and delay elements alternately disposed in series. Each inverting element receives an analog voltage signal as a power source and converts a pulse signal in an inversion operation time depending on the analog voltage signal. Each delay element delays transmission of the pulse signal. The transmission of the pulse signal is started from a starting inverting element at a start time, and a transit position of the pulse signal is detected at a detection time later than the start time by a predetermined time. A digital value indicating a level of the analog voltage signal is determined from the detected transit position of the pulse signal. Because transmission of the pulse signal is delayed by the delay elements, the transit position depending on the analog voltage signal can be correctly detected.
摘要翻译： A / D转换器具有交替设置的反相元件和延迟元件。每个反相元件接收模拟电压信号作为电源，并根据模拟电压信号在反转操作时间中转换脉冲信号。每个延迟元件延迟脉冲信号的传输。脉冲信号的发送在开始时从启动反转元件开始，并且在比开始时间晚一个预定时间的检测时间检测脉冲信号的转接位置。从检测到的脉冲信号的转接位置确定表示模拟电压信号的电平的数字值。由于脉冲信号的传输被延迟元件延迟，所以可以正确地检测取决于模拟电压信号的传输位置。

5. 发明申请

US20100237923A1 Method of placing delay units of pulse delay circuit on programmable logic device 有权
标题翻译：在可编程逻辑器件上放置脉冲延迟电路的延迟单元的方法
公开(公告)号：US20100237923A1
公开(公告)日：2010-09-23
申请号：US12661156
申请日：2010-03-11
申请人： Tomohito Terazawa , Shigenori Yamauchi , Takamoto Watanabe
发明人： Tomohito Terazawa , Shigenori Yamauchi , Takamoto Watanabe
IPC分类号： H03H11/26 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/17728
摘要： A method of placing delay units of a pulse delay circuit on a programmable logic device having logic cells in each of cell strings has a step of arranging each delay unit in one logic cell of the device such that the delay units are placed in respective specific cell strings aligned in a row direction and a step of serially connecting the delay units with one another as a straight delay line such that the delay units placed in the specific cell strings in the connecting order are aligned in the row direction. In the device, an inter-string transmission delay time on a line between two logic cells of different cell strings differs from an intra-string transmission delay time on a line between two logic cells of one cell string.
摘要翻译：将脉冲延迟电路的延迟单元放置在具有每个单元串中的逻辑单元的可编程逻辑器件上的方法具有将每个延迟单元布置在器件的一个逻辑单元中的步骤，使得延迟单元放置在相应的特定单元中在行方向排列的串和将延迟单元串联连接的直线延迟线的步骤，使得以连接顺序放置在特定单元串中的延迟单元在行方向上对齐。在该装置中，不同单元串的两个逻辑单元之间的行上的串间传输延迟时间与一个单元串的两个逻辑单元之间的一行上的串内传输延迟时间不同。

6. 发明授权

US07755530B2 Analog to digital converter with a series of delay units 有权
标题翻译：具有一系列延时单元的模数转换器
公开(公告)号：US07755530B2
公开(公告)日：2010-07-13
申请号：US12218531
申请日：2008-07-16
申请人： Tomohito Terazawa , Takamoto Watanabe
发明人： Tomohito Terazawa , Takamoto Watanabe
IPC分类号： H03M1/60
CPC分类号： H03M1/502
摘要： An A/D converter has a series of M delay units through which a pulse signal is transmitted while being delayed in each delay unit by a delay time depending on a level of an analog signal. A unit of the converter latches the pulse signal outputted from each delay unit at N sampling times to hold M×N latched data. Another unit of the converter receives the M×N pieces of latched data as a piece of combined data composed of the latched data arranged in an order corresponding to an arranging order of M×N sampling points in the pulse signal, converts the combined data into numeral data, corresponding to a position of the pulse signal in the delay units, at one time, and produces converted digital data corresponding to the level of the analog signal from the numeral data.
摘要翻译： A / D转换器具有一系列M个延迟单元，根据模拟信号的电平，在每个延迟单元中延迟延迟时间，脉冲信号通过该延迟单元被发送。转换器的单位在N个采样时间中锁存从每个延迟单元输出的脉冲信号，以保持M×N个锁存数据。转换器的另一单元接收M×N个锁存数据作为由按脉冲信号中的M×N个采样点的排列次序排列的锁存数据组成的一组合数据，将组合数据转换成数字数据对应于延迟单元中的脉冲信号的位置，并且产生与来自数字数据的模拟信号的电平对应的转换的数字数据。

7. 发明授权

US07733152B2 Control signal generating circuit enabling value of period of a generated clock signal to be set as the period of a reference signal multiplied or divided by an arbitrary real number 有权
标题翻译：控制信号发生电路使所生成的时钟信号的周期值能够被设置为与任意实数相乘或除以的参考信号的周期
公开(公告)号：US07733152B2
公开(公告)日：2010-06-08
申请号：US12324287
申请日：2008-11-26
申请人： Takamoto Watanabe
发明人： Takamoto Watanabe
IPC分类号： G06F1/04
CPC分类号： H03K3/0315 , H03K23/425
摘要： A pulse signal circulates around a ring of delay elements with respective traversal signals being thereby successively outputted from the delay elements. The period of a reference signal is multiplied or divided by a real number to obtain control data specifying a required period of a clock signal as a value having an integer part and a fractional part. The control data are used to select the timings of specific traversal signal, and the clock signal is generated based these selected timings, with the timing selection being repetitively adjusted in accordance with the fractional part of the control data.
摘要翻译：脉冲信号在延迟元件环周围循环，各个遍历信号由延迟元件依次输出。将参考信号的周期相乘或除以实数，以获得指定时钟信号的所需周期的控制数据，作为具有整数部分和小数部分的值。控制数据用于选择特定遍历信号的定时，并且基于这些选择的定时生成时钟信号，根据控制数据的小数部分重复地调整定时选择。

8. 发明授权

US07671313B2 Image sensor and control method of the image sensor 有权
标题翻译：图像传感器的图像传感器和控制方法
公开(公告)号：US07671313B2
公开(公告)日：2010-03-02
申请号：US11393818
申请日：2006-03-31
申请人： Takamoto Watanabe
发明人： Takamoto Watanabe
IPC分类号： H01L27/00 , H01J40/14
CPC分类号： H04N5/37455
摘要： An image sensor has plural array blocks B1 to B20 arranged in a two dimensional (2D) arrangement. Each array block has a sub array and a corresponding analogue to digital (A/D) converter for performing an A/D conversion of light signals (or detection signals) output from the sub array. The sub array has plural picture element cells arranged in a 2D arrangement. Each A/D converter has a pulse delay circuit having delay units of plural stages connected in series. Each delay unit delays an input pulse by a delay time corresponding to a level of the light signals received from the sub array. A pulse delay type A/D converter is used as the A/D converter, which outputs the number of the delay units as an A/D conversion data item through which the input pulse passes for a measurement time period.
摘要翻译：图像传感器具有以二维（2D）布置排列的多个阵列块B1至B20。每个阵列块具有子阵列和相应的模数（A / D）转换器，用于执行从子阵列输出的光信号（或检测信号）的A / D转换。子阵列具有以2D排列布置的多个像素单元。每个A / D转换器具有串联连接的多级延迟单元的脉冲延迟电路。每个延迟单元将输入脉冲延迟与从子阵列接收的光信号的电平相对应的延迟时间。使用脉冲延迟型A / D转换器作为A / D转换器，其输出延迟单元的数量作为输入脉冲经过测量时间段的A / D转换数据项。

9. 发明申请

US20090135040A1 Method for controlling delay time of pulse delay circuit and pulse delay circuit thereof 有权
标题翻译：用于控制脉冲延迟电路的延迟时间及其脉冲延迟电路的方法
公开(公告)号：US20090135040A1
公开(公告)日：2009-05-28
申请号：US12292761
申请日：2008-11-25
申请人： Takamoto Watanabe , Shigenori Yamauchi
发明人： Takamoto Watanabe , Shigenori Yamauchi
IPC分类号： H03M1/60 , H03H11/26 , G04F10/04
CPC分类号： H03K5/133
摘要： An inverter circuit configuring a delay unit is a so-called CMOS transistor including a PMOS transistor and an NMOS transistor, of which respective gates are interconnected and respective drains are interconnected. The source and a back gate of the NMOS transistor are connected to the ground. The source of the PMOS transistor is connected to a positive drive terminal and controlled by an analog input signal. The back gate of the PMOS transistor is connected to a control terminal and controlled by a control signal.
摘要翻译：配置延迟单元的逆变器电路是所谓的CMOS晶体管，其包括PMOS晶体管和NMOS晶体管，其中相应的栅极互连并且相应的漏极互连。 NMOS晶体管的源极和背栅极连接到地。 PMOS晶体管的源极连接到正极驱动端子并由模拟输入信号控制。 PMOS晶体管的背栅极连接到控制端子并由控制信号控制。

10. 发明授权

US07292175B2 Method of testing A/D converter circuit and A/D converter circuit 有权
标题翻译： A / D转换电路和A / D转换电路的测试方法
公开(公告)号：US07292175B2
公开(公告)日：2007-11-06
申请号：US11407211
申请日：2006-04-20
申请人： Takamoto Watanabe
发明人： Takamoto Watanabe
IPC分类号： H03M1/60
CPC分类号： H03M1/108 , H03M1/14 , H03M1/502 , H03M1/60
摘要： For testing an A/D converter circuit including a pulse delay circuit constituted by a plurality of cascade-connected delay units, and an encoding circuit configured to count the number of the delay units through which the input pulse signal passes within a predetermined measuring time and to output a digital signal representing the counted number, the method includes the steps of setting the A/D converter circuit in a test mode where the measuring time is set at a short test-use sampling period, applying the input pulse signal to each of serial delay blocks each of which is constituted by a predetermined number of the delay units, and determining good and bad of the A/D converter circuit on the basis of digital signals outputted from the encoding circuit representing the numbers of the delay units through which the input pulse signal has passed within each of the serial delay blocks.
摘要翻译：为了测试包括由多个级联连接的延迟单元构成的脉冲延迟电路的A / D转换电路，以及编码电路，被配置为对在预定测量时间内输入脉冲信号通过的延迟单元的数量进行计数;以及为了输出表示所述计数的数字信号，所述方法包括以下步骤：将所述A / D转换电路设定为测试时间设定在短的测试使用采样周期的测试模式，将所述输入脉冲信号施加到串行延迟块，每个延迟块由预定数量的延迟单元构成，并且基于从编码电路输出的数字信号确定A / D转换器电路的好坏，所述数字信号表示延迟单元的数量，输入脉冲信号已通过每个串行延迟块。

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