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41. 发明授权

US5965934A Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS 失效
标题翻译：用于实现生产有价值，低电介质，低互连电阻和高性能ICS的加工技术
公开(公告)号：US5965934A
公开(公告)日：1999-10-12
申请号：US681141
申请日：1996-07-22
申请人： Robin W. Cheung , Mark S. Chang
发明人： Robin W. Cheung , Mark S. Chang
IPC分类号： H01L21/28 , H01L21/027 , H01L21/768 , H01L23/532 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/53242 , H01L23/53228 , H01L23/53238 , H01L23/53252 , H01L23/5329 , H01L2924/0002 , Y10S148/10 , Y10S148/106 , Y10S438/95 , Y10S438/951
摘要： The interconnects in a semiconductor device contacting metal lines comprise a low resistance metal, such as copper, gold, silver, or platinum, and are separated by a material having a low dielectric constant, such as benzocyclobutene or a derivative thereof A tri-layer resist structure is used, together with a lift-off process, to form the interconnects. The low dielectric constant material provides a diffusion barrier to the diffusion of the low resistance metal. The tri-layer resist comprises a first layer of a dissolvable polymer, a second layer of a hard mask material, and a third layer of a resist material. The resulting structure provides an integrated circuit with increased speed and ease of fabrication.
摘要翻译：接触金属线的半导体器件中的互连包括诸如铜，金，银或铂的低电阻金属，并且由具有低介电常数的材料例如苯并环丁烯或其衍生物分离。三层抗蚀剂结构与剥离过程一起使用以形成互连。低介电常数材料为低电阻金属的扩散提供扩散阻挡层。三层抗蚀剂包括可溶解聚合物的第一层，硬掩模材料的第二层和抗蚀剂材料的第三层。所得到的结构提供了具有增加的速度和易于制造的集成电路。

42. 发明授权

US5918130A Transistor fabrication employing formation of silicide across source and drain regions prior to formation of the gate conductor 失效
标题翻译：在形成栅极导体之前，使用在源极和漏极区域之间形成硅化物的晶体管制造
公开(公告)号：US5918130A
公开(公告)日：1999-06-29
申请号：US929197
申请日：1997-09-08
申请人： Fred N. Hause , Mark I. Gardner , H. Jim Fulford, Jr.
发明人： Fred N. Hause , Mark I. Gardner , H. Jim Fulford, Jr.
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66621 , H01L29/7834 , Y10S148/10 , Y10S438/951
摘要： The present invention advantageously provides a method for forming a transistor in which silicide contact areas are formed to the junctions during fabrication of the transistor. The silicide contact areas may be formed using a single high temperature anneal since silicide forming near sidewalls of the gate oxide is prevented. In one embodiment, dopants are first forwarded into a lateral region of a silicon-based substrate to form an implant region. Then a silicide layer is formed across the implant region using a high temperature anneal. A sacrificial material is deposited across the silicide layer and the substrate. A contiguous opening is formed vertically through the sacrificial material and the silicide layer, exposing a portion of the substrate. Dopants of the type opposite to the dopants implanted previously are then implanted into the exposed substrate region to form a channel. Thus, the implant region is separated into source and drain regions having a channel interposed between them. Spacers may be formed on opposed sidewall surfaces of the sacrificial material within the opening. A gate oxide is then formed across the exposed region, followed by the formation of a polysilicon gate conductor across the gate oxide. A polycide is formed across the gate conductor before the sacrificial material is removed.
摘要翻译：本发明有利地提供了一种形成晶体管的方法，其中在晶体管的制造期间，其中形成硅化物接触区域到结。可以使用单个高温退火来形成硅化物接触区域，因为防止在栅极氧化物的侧壁附近形成硅化物。在一个实施例中，首先将掺杂剂转移到硅基衬底的横向区域中以形成植入区域。然后使用高温退火在所述注入区域上形成硅化物层。在硅化物层和衬底之间沉积牺牲材料。通过牺牲材料和硅化物层垂直地形成连续的开口，暴露基板的一部分。然后将与先前注入的掺杂剂相反的类型的掺杂剂注入暴露的衬底区域中以形成沟道。因此，注入区被分离成具有介于它们之间的通道的源区和漏区。间隔件可以形成在开口内的牺牲材料的相对的侧壁表面上。然后在暴露区域之间形成栅极氧化物，随后在栅极氧化物上形成多晶硅栅极导体。在除去牺牲材料之前，跨越栅极导体形成多晶硅化物。

43. 发明授权

US5854097A Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US5854097A
公开(公告)日：1998-12-29
申请号：US440917
申请日：1995-05-15
申请人： Tadahiro Ohmi , Mamoru Miyawaki
发明人： Tadahiro Ohmi , Mamoru Miyawaki
IPC分类号： H01L29/73 , H01L21/283 , H01L21/316 , H01L21/331 , H01L21/336 , H01L29/08 , H01L29/10 , H01L29/417 , H01L29/423 , H01L29/737 , H01L29/78 , H01L21/338
CPC分类号： H01L29/66287 , H01L21/31683 , H01L29/0847 , H01L29/1033 , H01L29/41775 , H01L29/42304 , H01L29/66272 , H01L29/66545 , H01L29/66613 , H01L29/66628 , H01L29/7375 , H01L29/7378 , H01L2924/0002 , Y10S148/10 , Y10S438/926 , Y10S438/951
摘要： A device having, at least, a first film having a surface on which neither a natural oxide film nor impurity grains caused by a resist residue is or are present, and a conductive material layer formed on a surface adjacent to the surface of the first film, wherein an insulative compound film is formed on a surface of the conductive material layer by a surface reaction with the conductive material layer, and a predetermined second film required for an arrangement is formed on the surface of the first film.
摘要翻译：一种具有至少具有其表面上没有自然氧化物膜和由抗蚀剂残渣引起的杂质颗粒的表面的第一膜的器件，以及形成在与第一膜的表面相邻的表面上的导电材料层其中通过与导电材料层的表面反应在导电材料层的表面上形成绝缘化合物膜，并且在第一膜的表面上形成预定的第二膜。

44. 发明授权

US5500381A Fabrication method of field-effect transistor 失效
标题翻译：场效应晶体管的制造方法
公开(公告)号：US5500381A
公开(公告)日：1996-03-19
申请号：US413616
申请日：1995-03-30
申请人： Takayoshi Yoshida , Yasunobu Nashimoto
发明人： Takayoshi Yoshida , Yasunobu Nashimoto
IPC分类号： H01L29/812 , H01L21/285 , H01L21/335 , H01L21/338 , H01L29/778
CPC分类号： H01L29/66462 , H01L21/28587 , H01L29/7787 , Y10S148/10
摘要： A fabrication method of a FET that enables to realize a shorter length between a source-side edge of a recess and an opposing edge of a gate electrode at a higher accuracy than the accuracy limit of the present lithography technique, i.e., about .+-.0.1 .mu.m. After channel, carrier-supply, and contact layers are epitaxially grown on a semiconductor substrate in this order, a patterned insulator layer is formed on the contact layer. Using the insulator layer as a mask, the contact layer is isotropically etched to form a symmetrical recess on the underlying carrier-supply layer. One of the ends of the contact layer facing the symmetrical recess is etched again to make it asymmetric. During the etching processes, the underlying carrier-supply layer is almost never etched due to large etch rate differences for the contact layer and the carrier-supply layer. A patterned conductor layer is formed on the patterned insulator layer to form the gate electrode in Schottky contact with the carrier-supply layer. After removing the insulator layer, and source and drain electrodes are formed on the contact layer. An etch-stop layer is additionally formed between the carrier-supply layer and the contact layer.
摘要翻译：一种FET的制造方法，其能够以比本光刻技术的精度极限更高的精度实现凹部的源极侧边缘和栅电极的相对边缘之间的更短的长度，即约+/- 0.1亩。在半导体衬底上依次外延生长通道，载流子供应和接触层之后，在接触层上形成图案化的绝缘体层。使用绝缘体层作为掩模，接触层被各向同性地蚀刻以在下层载体供给层上形成对称的凹部。面对对称凹部的接触层的端部之一被再次蚀刻以使其不对称。在蚀刻工艺期间，由于接触层和载体供应层的较大的蚀刻速率差，底层载体供应层几乎不被蚀刻。在图案化的绝缘体层上形成图案化导体层，以形成与载体供给层肖特基接触的栅电极。在去除绝缘体层之后，在接触层上形成源极和漏极。在载体供给层和接触层之间另外形成蚀刻停止层。

45. 发明授权

US5266526A Method of forming trench buried wiring for semiconductor device 失效
标题翻译：形成用于半导体器件的沟槽埋地布线的方法
公开(公告)号：US5266526A
公开(公告)日：1993-11-30
申请号：US854812
申请日：1992-03-19
申请人： Masaharu Aoyama , Masahiro Abe
发明人： Masaharu Aoyama , Masahiro Abe
IPC分类号： H01L21/3205 , H01L21/288 , H01L21/74 , H01L21/768 , H01L23/52 , H01L21/441 , H01L21/469
CPC分类号： H01L21/7688 , H01L21/743 , Y10S148/10
摘要： A method of forming a trench buried wiring on a semiconductor device. The method includes the steps of: forming a trench in a first insulating film formed on a semiconductor substrate, by using as a mask a photoresist layer, the trench having substantially an upright step; depositing a first electrode material on the surface of the photoresist layer and on the bottom of the trench, while leaving the photoresist layer; removing the photoresist layer and the first electrode material on the photoresist layer while leaving the first electrode material only on the bottom of the trench; and filling a second electrode material in the trench to form a composite electrode with the second electrode material being superposed on the first electrode material.
摘要翻译：一种在半导体器件上形成沟槽埋入布线的方法。该方法包括以下步骤：在形成在半导体衬底上的第一绝缘膜中形成沟槽，通过使用光刻胶层作为掩模，该沟槽具有基本上直立的步骤; 在光致抗蚀剂层的表面上和沟槽的底部上沉积第一电极材料，同时留下光致抗蚀剂层; 在光致抗蚀剂层上除去光致抗蚀剂层和第一电极材料，同时仅在沟槽的底部留下第一电极材料; 以及在沟槽中填充第二电极材料以形成复合电极，其中第二电极材料叠置在第一电极材料上。

46. 发明授权

US5220186A Semiconductor device with a mushroom-shaped gate electrode 失效
标题翻译：具有MUSHROOM型门电极的半导体器件
公开(公告)号：US5220186A
公开(公告)日：1993-06-15
申请号：US802560
申请日：1991-12-05
申请人： Nobuyuki Kasai , Shinichi Sakamoto , Takuji Sonoda , Tetsuya Yagi
发明人： Nobuyuki Kasai , Shinichi Sakamoto , Takuji Sonoda , Tetsuya Yagi
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3213 , H01L21/338 , H01L29/423 , H01L29/47 , H01L29/812
CPC分类号： H01L29/66863 , H01L21/28587 , H01L21/32136 , H01L29/42316 , H01L29/475 , Y10S148/10
摘要： A mushroom-shaped gate electrode has a lower end in a recess in a semiconductor active layer on a semiconductor substrate. The gate electrode has an enlarged head. A metallic side wall is disposed on a portion of the leg of the gate electrode adjacent the head. Thus, the gate length of a semiconductor device, such as a field effect transistor, is reduced while the effective cross-sectional area of the gate electrode is increased whereby the noise characteristics of the semiconductor device are improved.
摘要翻译：蘑菇形栅电极在半导体衬底上的半导体有源层的凹部中具有下端。栅电极具有扩大的头部。金属侧壁设置在邻近头部的栅电极的腿部的一部分上。因此，诸如场效应晶体管的半导体器件的栅极长度减小，同时栅电极的有效截面面积增加，从而提高了半导体器件的噪声特性。

47. 发明授权

US5215939A Method of manufacturing a planar buried heterojunction laser 失效
标题翻译：制造平面波导异常激光的方法
公开(公告)号：US5215939A
公开(公告)日：1993-06-01
申请号：US832024
申请日：1992-02-06
申请人： Leon Goldstein , Dominique Bonnevie , Francois Brillouet , Francis Poingt , Jean-Louis Lievin
发明人： Leon Goldstein , Dominique Bonnevie , Francois Brillouet , Francis Poingt , Jean-Louis Lievin
IPC分类号： H01S5/00 , H01S5/20 , H01S5/227
CPC分类号： H01S5/227 , H01S5/2081 , H01S5/2275 , Y10S148/09 , Y10S148/10
摘要： In a method of manufacturing a planar buried heterojunction laser, after etching to delimit a laser stripe in relief on a substrate, lateral layers to surround the stripe are formed by a non-selective growth method not only at the sides of the stripe but also above it to create a parasitic projection. This projection is then removed after separation from the substrate by selective attack of a lift-off stripe which was deposited for this purpose above the stripe prior to this etching. Passages are formed for the attack medium used for this purpose. The invention can be applied in particular to the manufacture of fiber optic transmission systems.
摘要翻译：在制造平面埋入异质结激光器的方法中，在蚀刻以限定基板上的激光条纹之后，不仅在条纹侧面而且在上方都通过非选择性生长方法形成围绕条纹的横向层它创建一个寄生投影。然后通过选择性地攻击在该蚀刻之前在条纹上方沉积的剥离条纹从衬底分离之后，去除该突起。形成用于此目的的攻击介质的通道。本发明可以特别应用于光纤传输系统的制造。

48. 发明授权

US5171711A Method of manufacturing integrated circuit devices 失效
标题翻译：集成电路器件的制造方法
公开(公告)号：US5171711A
公开(公告)日：1992-12-15
申请号：US774986
申请日：1991-10-17
申请人： Hiroshi Tobimatsu
发明人： Hiroshi Tobimatsu
IPC分类号： H01L21/60 , H01L23/485
CPC分类号： H01L24/11 , H01L24/13 , H01L2224/05572 , H01L2224/1147 , H01L2224/11474 , H01L2224/13099 , H01L2224/13144 , H01L2224/13565 , H01L2924/0001 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/0106 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , Y10S148/10
摘要： A method of manufacturing IC devices is applied in forming bumps on an electrode pads to be an input/output terminal of the ICs with a conductive metal layer interposed therebetween. Firstly, a first resist having a prescribed opening is formed over a semiconductor substrate having the electrode pads formed thereon. Thereafter, the metal layer is formed over the semiconductor substrate, and furthermore, a second resist is formed over it by making an opening in a region almost the same as the opening of the first resist. Then, the second resist is removed after forming the bumps within the opening of the second resist. Thereafter, the first resist is removed after removing an exposed portion of the metal layer. According to the processes, overetching of and generation of an etching residue of the metal layer are prevented.
摘要翻译：应用制造IC器件的方法，在电极焊盘上形成凸起，作为IC之间的导电金属层，作为IC的输入/输出端子。首先，在其上形成有电极焊盘的半导体衬底上形成具有规定开口的第一抗蚀剂。此后，在半导体衬底上形成金属层，此外，通过在与第一抗蚀剂的开口几乎相同的区域中形成开口形成第二抗蚀剂。然后，在第二抗蚀剂的开口内形成凸起之后，除去第二抗蚀剂。此后，在去除金属层的暴露部分之后去除第一抗蚀剂。根据该方法，防止金属层的蚀刻残渣的过蚀刻和产生。

49. 发明授权

US5091342A Multilevel resist plated transfer layer process for fine line lithography 失效
标题翻译：用于精细线切割的多层耐蚀层转移层过程
公开(公告)号：US5091342A
公开(公告)日：1992-02-25
申请号：US315351
申请日：1989-02-24
申请人： Lawrence G. Studebaker , Edward H. Wong
发明人： Lawrence G. Studebaker , Edward H. Wong
IPC分类号： G03F7/26 , H01L21/027 , H01L21/311 , H01L21/338
CPC分类号： H01L29/66863 , H01L21/0272 , H01L21/31144 , Y10S148/10 , Y10S148/105 , Y10S148/143 , Y10S438/945 , Y10S438/947 , Y10S438/949
摘要： A multilevel resist process for fine line e-beam lithography, or, alternatively, deep ultraviolet (DUV) optical lithography with a clear field mask involving the use of a plated transfer layer for image reversal. The process preferably uses a high brightness, quarter-micron diameter electron beam and a high speed negative resist to fabricate microwave MESFETs, MODFETs, and integrated circuits with gate lengths of 0.25 micron and below. This is achieved by producing a line of negative resist which can be developed to 0.25 micron or below. A plated transfer layer is then applied which provides image reversal, converting the line of resist into an opening suitable for conventional gate recess etching, gate metal deposition, and lift-off. A positive resist can be substituted for the negative e-beam resist and exposed with DUV through a clear field mask instead of an electron beam for the fabrication of MESFETs.

50. 发明授权

US5084409A Method for patterned heteroepitaxial growth 失效
标题翻译：图案异质外延生长方法
公开(公告)号：US5084409A
公开(公告)日：1992-01-28
申请号：US543644
申请日：1990-06-26
申请人： Edward A. Beam, III , Yung-Chung Kao
发明人： Edward A. Beam, III , Yung-Chung Kao
IPC分类号： H01L21/302 , H01L21/20 , H01L21/203 , H01L21/3065 , H01L21/76 , H01L21/8252
CPC分类号： H01L21/02381 , H01L21/02395 , H01L21/0242 , H01L21/02463 , H01L21/02532 , H01L21/02546 , H01L21/02639 , H01L21/7605 , H01L21/8252 , Y10S148/10 , Y10S148/161
摘要： Shadow masking layer (130) is undercut during etch of sidewall layer (120) thus preventing sidewall growth during growth of heteroepitaxial region (140), resulting in a planar structure with a high integrity of crystal in the grown region (140).
摘要翻译：阴影掩模层（130）在蚀刻侧壁层（120）期间被底切，从而防止异质外延区域（140）生长期间的侧壁生长，导致在生长区域（140）中晶体的高完整性的平面结构。

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