专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5760457A Bipolar transistor circuit element having base ballasting resistor 失效
标题翻译：具有基极镇流电阻的双极晶体管电路元件
公开(公告)号：US5760457A
公开(公告)日：1998-06-02
申请号：US806396
申请日：1997-02-26
申请人： Shigeru Mitsui , Takuji Sonoda , Teruyuki Shimura , Saburo Takamiya
发明人： Shigeru Mitsui , Takuji Sonoda , Teruyuki Shimura , Saburo Takamiya
IPC分类号： H01L21/331 , H01L21/8222 , H01L27/06 , H01L29/08 , H01L29/205 , H01L29/73 , H01L29/737 , H01L29/00 , H01L31/0328
CPC分类号： H01L29/0817 , H01L27/0658 , H01L29/7304 , H01L29/7371
摘要： A bipolar transistor circuit element includes a semiconductor substrate; successively disposed on the substrate, a base layer, an emitter layer, and a collector layer; a bipolar transistor formed from parts of the collector, base, and emitter layers and including a base electrode electrically connected to the base layer and a base electrode pad for making an external connection to the base layer; a base ballasting resistor formed from a part of the base layer isolated from the bipolar transistor and electrically connecting the base electrode to the base electrode pad; and a base parallel capacitor connected in parallel with the base ballasting resistor wherein the base parallel capacitor includes part of the base input pad, a dielectric film disposed on part of the base electrode pad, and a second electrode disposed on the dielectric layer opposite the base electrode pad and electrically connected to the emitter electrode of the bipolar transistor. The base ballasting resistor has a high resistance relative to an emitter ballasting reactor so that it can be easily mass produced with good uniformity and yield.
摘要翻译：双极晶体管电路元件包括半导体衬底; 依次设置在基板上，基底层，发射极层和集电极层; 由集电极，基极和发射极层的部分形成的双极性晶体管，并且包括电连接到基极层的基极和用于与基极层进行外部连接的基极焊盘; 由与所述双极型晶体管隔离的所述基极层的一部分形成的基极保护电阻器，并且将所述基极电极与所述基极电极焊盘电连接; 以及与所述基极镇流电阻并联连接的基极并联电容器，其中所述基极并联电容器包括所述基极输入焊盘的一部分，设置在所述基极电极焊盘的一部分上的电介质膜，以及设置在与所述基极相对的所述电介质层上的第二电极电极焊盘并电连接到双极晶体管的发射极。碱性镇流电阻器相对于发射极压载反应器具有高电阻，使得其可以容易地以均匀性和产率良好地批量生产。

2. 发明授权

US5428224A Field effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：US5428224A
公开(公告)日：1995-06-27
申请号：US144483
申请日：1993-10-28
申请人： Kazuo Hayashi , Takuji Sonoda
发明人： Kazuo Hayashi , Takuji Sonoda
IPC分类号： H01L29/812 , H01L21/338 , H01L29/772 , H01L29/778 , H01L29/161 , H01L29/205
CPC分类号： B82Y10/00 , H01L29/772
摘要： A field effect transistor with improved operation speed and reduced noise includes a drain electrode disposed on a channel layer with a contact layer interposed therebetween, a source electrode, and a gate electrode disposed between the drain and source electrodes. A resonant tunneling diode is disposed between the source electrode and the channel region for supplying hot electrons to the channel layer beneath the gate electrode.
摘要翻译：具有改善的操作速度和降低的噪声的场效应晶体管包括布置在其间插入接触层的沟道层上的漏电极，源电极和设置在漏极和源电极之间的栅电极。谐振隧道二极管设置在源电极和沟道区之间，用于向栅电极下方的沟道层提供热电子。

3. 发明授权

US5139968A Method of producing a t-shaped gate electrode 失效
标题翻译：生产t形栅电极的方法
公开(公告)号：US5139968A
公开(公告)日：1992-08-18
申请号：US606855
申请日：1990-10-31
申请人： Iwao Hayase , Takuji Sonoda
发明人： Iwao Hayase , Takuji Sonoda
IPC分类号： H01L21/285 , H01L21/338 , H01L29/423 , H01L29/812
CPC分类号： H01L29/66863 , H01L21/28587 , H01L29/42316 , H01L29/8128 , Y10S148/14
摘要： A semiconductor device includes a relatively broad recess in a semiconductor substrate between a source electrode and a drain electrode, a relatively narrow, deeper recess closer to the source electrode than to the drain electrode, and a T-shaped gate electrode having a broad head disposed in the narrower recess. A production method for a semiconductor device having a T-shaped gate electrode provided with a broad head and disposed in a two stage recess includes producing a relatively broad recess in a semiconductor substrate leaving a dummy gate, producing a resist pattern for producing the head of the T-shaped gate electrode, exposing the dummy gate by removing some of the resist pattern, and thereafter producing a narrower, deeper recess closer to the source electrode than to the drain electrode, thereby producing a two stage recess structure and producing a T-shaped gate electrode in the deeper recess.
摘要翻译：半导体器件包括在源电极和漏电极之间的半导体衬底中的相对宽的凹槽，比漏极更靠近源电极的相对窄的较深的凹槽，以及具有宽的头部的T形栅电极在狭窄的凹处。一种半导体器件的制造方法，其具有设置有宽头部并设置在两级凹槽中的T形栅电极，包括在半导体衬底中产生相对宽的凹槽，留下虚拟栅极，产生用于制造 T形栅电极，通过去除一些抗蚀剂图案露出伪栅，然后产生比漏电极更靠近源电极的较深的较深的凹陷，从而产生两级凹槽结构并产生T- 在较深的凹槽中形成栅电极。

4. 发明授权

US5679603A Method of making semiconductor device including high resistivity layer 失效
标题翻译：制造具有高电阻率层的半导体器件的方法
公开(公告)号：US5679603A
公开(公告)日：1997-10-21
申请号：US386804
申请日：1995-02-06
申请人： Tatsuya Kimura , Takao Ishida , Takuji Sonoda
发明人： Tatsuya Kimura , Takao Ishida , Takuji Sonoda
IPC分类号： H01L21/205 , H01L21/20
CPC分类号： H01L21/02392 , H01L21/02546 , H01L21/02579 , H01L21/0262 , Y10S438/917
摘要： A high resistance compound semiconductor layer included in a semiconductor device including a plurality of compound semiconductor layers having different compositions includes a compound semiconductor that is vapor phase grown employing an organic metal compound including In, an organic metal compound including Al, and a hydrogenated compound or an organic metal compound including As. The high resistance compound semiconductor layer includes p type impurities having a concentration that positions the Fermi level of the compound semiconductor approximately at the center of the band gap of the compound semiconductor. Therefore, it is possible to produce a high resistance AlInAs layer that has less impurities that are diffused into an adjacent compound semiconductor layer.
摘要翻译：包括在具有不同组成的多个化合物半导体层的半导体器件中的高电阻化合物半导体层包括使用包含In的有机金属化合物，包含Al的有机金属化合物和氢化化合物进行气相生长的化合物半导体，或包含As的有机金属化合物。高电阻化合物半导体层包括具有将化合物半导体的费米能级大致位于化合物半导体的带隙的中心的浓度的p型杂质。因此，可以生产具有较少杂质扩散到相邻化合物半导体层中的高电阻AlInAs层。

5. 发明授权

US5362677A Method for producing a field effect transistor with a gate recess structure 失效
标题翻译：一种具有栅极凹陷结构的场效应晶体管的制造方法
公开(公告)号：US5362677A
公开(公告)日：1994-11-08
申请号：US627777
申请日：1990-12-14
申请人： Shinichi Sakamoto , Takuji Sonoda
发明人： Shinichi Sakamoto , Takuji Sonoda
IPC分类号： H01L21/306 , H01L21/285 , H01L21/338 , H01L29/778 , H01L29/812
CPC分类号： H01L29/66863 , H01L21/28587 , H01L29/7787 , H01L29/8128
摘要： A field effect transistor has an active layer containing a multi-step recess that becomes narrower as it approaches the substrate. A gate electrode is produced at the deepest portion of the recess section. The transistor may be produced by successively selectively etching the active layer and an overlying semiconductor surface protection film to produce a multi-step configuration recess, depositing a gate electrode at the bottom of the recess, and depositing source and drain electrodes on the active layer.
摘要翻译：场效应晶体管具有包含多步骤凹陷的有源层，随着它接近基板而变窄。在凹部的最深部产生栅电极。可以通过连续选择性地蚀刻有源层和上覆的半导体表面保护膜来产生晶体管，以产生多步构型凹槽，在凹槽的底部沉积栅电极，以及在活性层上沉积源电极和漏电极。

6. 发明授权

US5045497A Method of making a schottky electrode 失效
标题翻译：制作肖特基电极的方法
公开(公告)号：US5045497A
公开(公告)日：1991-09-03
申请号：US426183
申请日：1989-10-25
申请人： Kazuo Hayashi , Takuji Sonoda
发明人： Kazuo Hayashi , Takuji Sonoda
IPC分类号： H01L29/872 , H01L21/338 , H01L29/47 , H01L29/812
CPC分类号： H01L29/8122 , H01L29/47 , Y10S148/088 , Y10S148/139 , Y10S148/14
摘要： A semiconductor device includes a semiconductor body and a metal contact forming a Schottky barrier with said body, the metal contact including a layer of nickel disposed on the semiconductor body, an aluminum layer disposed on the nickel layer, and a nickel aluminum alloy disposed at the interface of the layers. The alloy is formed by heating the metal layers.
摘要翻译：半导体器件包括半导体本体和与所述主体形成肖特基势垒的金属接触，金属接触包括设置在半导体本体上的镍层，设置在镍层上的铝层和设置在镍层上的镍铝合金层的界面。通过加热金属层形成合金。

7. 发明授权

US4984036A Field effect transistor with multiple grooves 失效
标题翻译：具有多个沟槽的场效应晶体管
公开(公告)号：US4984036A
公开(公告)日：1991-01-08
申请号：US367685
申请日：1989-06-19
申请人： Shinichi Sakamoto , Takuji Sonoda
发明人： Shinichi Sakamoto , Takuji Sonoda
IPC分类号： H01L21/306 , H01L21/285 , H01L21/338 , H01L29/778 , H01L29/812
CPC分类号： H01L29/66863 , H01L21/28587 , H01L29/7787 , H01L29/8128
摘要： A field effect transistor has an active layer containing a multi-step recess that becomes narrower as it approaches the substrate. A gate electrode is produced at the deepest portion of the recess section. The transistor may be produced by successively selectively etching the active layer and an overlying semiconductor surface protection film to produce a multi-step configuration recess, depositing a gate electrode at the bottom of the recess, and depositing source and drain electrodes on the active layer.
摘要翻译：场效应晶体管具有包含多步骤凹陷的有源层，随着它接近基板而变窄。在凹部的最深部产生栅电极。可以通过连续选择性地蚀刻有源层和上覆的半导体表面保护膜来产生晶体管，以产生多步构型凹槽，在凹槽的底部沉积栅电极，以及在活性层上沉积源电极和漏电极。

8. 发明授权

US5288654A Method of making a mushroom-shaped gate electrode of semiconductor device 失效
标题翻译：制造半导体器件的蘑菇状栅电极的方法
公开(公告)号：US5288654A
公开(公告)日：1994-02-22
申请号：US14857
申请日：1993-02-08
申请人： Nobuyuki Kasai , Shinichi Sakamoto , Takuji Sonoda , Tetsuya Yagi
发明人： Nobuyuki Kasai , Shinichi Sakamoto , Takuji Sonoda , Tetsuya Yagi
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3213 , H01L21/338 , H01L29/423 , H01L29/47 , H01L29/812 , H01L21/265
CPC分类号： H01L29/66863 , H01L21/28587 , H01L21/32136 , H01L29/42316 , H01L29/475 , Y10S148/10
摘要： A mushroom-shaped gate electrode has a lower end in a recess in a semiconductor active layer on a semiconductor substrate. The gate electrode has an enlarged head. A metallic side wall is disposed on a portion of the leg of the gate electrode adjacent the head. Thus, the gate length of a semiconductor device, such as a field effect transistor, is reduced while the effective cross-sectional area of the gate electrode is increased whereby the noise characteristics of the semiconductor device are improved.
摘要翻译：蘑菇形栅电极在半导体衬底上的半导体有源层的凹部中具有下端。栅电极具有扩大的头部。金属侧壁设置在邻近头部的栅电极的腿部的一部分上。因此，诸如场效应晶体管的半导体器件的栅极长度减小，同时栅电极的有效截面面积增加，从而提高了半导体器件的噪声特性。

9. 发明授权

US5285087A Heterojunction field effect transistor 失效
标题翻译：异质结场效应晶体管
公开(公告)号：US5285087A
公开(公告)日：1994-02-08
申请号：US719196
申请日：1991-06-21
申请人： Koichi Narita , Kazuo Hayashi , Takuji Sonoda
发明人： Koichi Narita , Kazuo Hayashi , Takuji Sonoda
IPC分类号： H01L29/20 , H01L21/338 , H01L29/778 , H01L29/812 , H01L31/072 , H01L31/0328 , H01L31/0336 , H01L31/109
CPC分类号： H01L29/7783
摘要： A heterojunction field effect transistor includes a semi-insulating crystalline layer, a pseudomorphic channel layer disposed on the semi-insulating crystalline layer, and an electron supply layer disposed on said pseudomorphic layer. The channel layer has a lattice constant equal to or close to that of the semi-insulating crystalline layer adjacent to semi-insulating crystalline layer and different from the semi-insulating crystalline layer adjacent to the electron supply layer.
摘要翻译：异质结场效应晶体管包括半绝缘晶体层，设置在半绝缘晶体层上的假晶格层，以及设置在所述伪晶层上的电子供应层。沟道层的晶格常数等于或接近与半绝缘结晶层相邻并且与电子供应层相邻的半绝缘晶体层的半绝缘晶体层的晶格常数。

10. 发明授权

US4967242A Heterojunction field effect transistor 失效
标题翻译：异质结场效应晶体管
公开(公告)号：US4967242A
公开(公告)日：1990-10-30
申请号：US300262
申请日：1989-01-19
申请人： Takuji Sonoda , Kazuo Hayashi
发明人： Takuji Sonoda , Kazuo Hayashi
IPC分类号： H01L29/205 , H01L21/338 , H01L29/778 , H01L29/812
CPC分类号： H01L29/7783 , H01L29/7787
摘要： A heterojunction field effect transistor includes a carrier supplying layer comprising material which is not likely to produce a deep level even by doping. A channel layer comprises material which has the largest electron affinity among three types of semiconductor material constituting the heterojunction FET and has a high carrier mobility. A spacer layer is interposed between the channel layer and the carrier supplying layer and comprises material which enables the reduction of Coulomb interaction between two-dimensional carriers in the channel layer and ions in the carrier supplying layer. In addition, the spacer layer increases the effective conduction band energy discontinuity .DELTA.E.sub.c between the carrier supplying layer and the channel layer.
摘要翻译：异质结场效应晶体管包括载体供给层，其包含即使通过掺杂也不可能产生深电平的材料。沟道层包括在构成异质结FET的三种类型的半导体材料中具有最大的电子亲和力并且具有高载流子迁移率的材料。间隔层插入在沟道层和载体供应层之间，并且包括能够减少沟道层中的二维载流子与载流子供应层中的离子之间的库仑相互作用的材料。此外，间隔层增加载体供给层和沟道层之间的有效导带能量不连续性DELTA Ec。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式