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41. 发明授权

US06718496B1 Self-repairing semiconductor device having a testing unit for testing under various operating conditions 失效
标题翻译：具有用于在各种操作条件下进行测试的测试单元的自修复半导体器件
公开(公告)号：US06718496B1
公开(公告)日：2004-04-06
申请号：US09527597
申请日：2000-03-17
申请人： Hiroto Fukuhisa , Yukihiro Urakawa
发明人： Hiroto Fukuhisa , Yukihiro Urakawa
IPC分类号： G01R3128
CPC分类号： G11C29/4401 , G11C29/44 , G11C29/848
摘要： A semiconductor device is provided having an internal circuit to be tested, a redundancy circuit used when detecting a defective part in the internal circuit, and a switching unit connected to the internal circuit and the redundancy circuit. The switching unit switches wiring in order to ensure proper operation of the semiconductor. A test unit is connected to the internal circuit for testing for the internal circuit. An operation environment change unit is connected to the internal circuit, wherein for changing an environment of the internal circuit when during testing. According to the present invention, testing of semiconductor devices can be performed under an actual environment so that a defective part can be detected under the actual operation environment. Moreover, it is possible to widen the range of guaranteed operation of semiconductor devices when a plurality of tests are performed under a plurality of operation environments.
摘要翻译：提供了具有要测试的内部电路的半导体器件，当检测内部电路中的缺陷部分时使用的冗余电路以及连接到内部电路和冗余电路的开关单元。开关单元切换接线，以确保半导体的正常工作。测试单元连接到内部电路，用于内部电路的测试。操作环境改变单元连接到内部电路，其中用于在测试期间改变内部电路的环境。根据本发明，可以在实际环境下进行半导体器件的测试，从而可以在实际操作环境下检测缺陷部分。此外，当在多个操作环境下执行多个测试时，可以扩大半导体器件的保证操作的范围。

42. 发明授权

US06578179B2 LSI layout design apparatus, layout design method, recording medium recording layout design program, and semiconductor integrated circuit 失效
公开(公告)号：US06578179B2
公开(公告)日：2003-06-10
申请号：US09962272
申请日：2001-09-26
申请人： Tsukasa Shirotori , Yukihiro Urakawa
发明人： Tsukasa Shirotori , Yukihiro Urakawa
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F17/5068
摘要： A migration section conducting process migration for converting first layout according to a first design standard into second layout according to a second design standard and a designated transistor size; an extraction section extracting transistor sizes and parasitic capacitances from the first and the second layout; a delay calculation section calculating first delay time from the transistor size and the parasitic capacitance extracted from the first layout and a driving current value of a transistor based on the first design standard, and calculating second delay time from the transistor size and the parasitic capacitance extracted from the second layout and a driving current value of the transistor based on the second design standard; and an optimum value calculation section calculating an optimum value of the transistor size after the process migration in order that the second delay time becomes equal to the first delay time, are provided.

43. 发明授权

US06414525B2 I/O interface circuit, semiconductor chip and semiconductor system 失效
标题翻译： I / O接口电路，半导体芯片和半导体系统
公开(公告)号：US06414525B2
公开(公告)日：2002-07-02
申请号：US09899036
申请日：2001-07-06
申请人： Yukihiro Urakawa
发明人： Yukihiro Urakawa
IPC分类号： H03K190175
CPC分类号： H03K19/018592
摘要： A push-pull output buffer contained in an I/O interface circuit of the present invention comprises a P channel MOSFET and a N channel MOSFET. The P channel MOSFET is connected between an I/O node connected to an external circuit through a transmission path and a first potential node to which a first potential is applied. The N channel MOSFET is connected between a second potential node to which a second potential is applied and the I/O node. On/off status of the P channel MOSFET and N channel MOSFET are controlled depending on an input mode for inputting a signal from an external circuit and an output mode for outputting a signal to the external circuit through a transmission path. In this I/O interface circuit, the first and second potentials are terminating potentials, and when input mode is selected, out of the P channel MOSFET and N channel MOSFET, the MOSFET connected to a potential node to which a terminating potential is applied is controlled to be always on.
摘要翻译：包含在本发明的I / O接口电路中的推挽输出缓冲器包括P沟道MOSFET和N沟道MOSFET。 P沟道MOSFET连接在通过传输路径连接到外部电路的I / O节点和施加第一电位的第一电位节点之间。 N沟道MOSFET连接在施加第二电位的第二电位节点和I / O节点之间。根据用于输入来自外部电路的信号的输入模式和通过传输路径将信号输出到外部电路的输出模式来控制P沟道MOSFET和N沟道MOSFET的开/关状态。在该I / O接口电路中，第一和第二电位为终止电位，当选择输入模式时，从P沟道MOSFET和N沟道MOSFET中，连接到施加了终止电位的电位节点的MOSFET为控制着永远在上。

44. 发明授权

US5512772A Semiconductor device having bipolar transistor and MOS transistor 失效
标题翻译：具有双极晶体管和MOS晶体管的半导体器件
公开(公告)号：US5512772A
公开(公告)日：1996-04-30
申请号：US309034
申请日：1994-09-20
申请人： Takeo Maeda , Hiroshi Momose , Yukihiro Urakawa , Masataka Matsui
发明人： Takeo Maeda , Hiroshi Momose , Yukihiro Urakawa , Masataka Matsui
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8249 , H01L27/06 , H01L29/165 , H01L29/737 , H01L27/02 , H01L29/161
CPC分类号： H01L27/0623 , H01L29/7378
摘要： A semiconductor device of this invention includes a bipolar transistor and MOS transistors which are formed on the same semiconductor substrate. The bipolar transistor is hetero-bipolar transistor having a hetero junction. The hetero-bipolar transistor is a bipolar transistor of double-hetero structure in which a material used for forming the base region thereof has a band gap narrower than a material used for forming the emitter and collector regions thereof.
摘要翻译：本发明的半导体器件包括形成在同一半导体衬底上的双极晶体管和MOS晶体管。双极晶体管是具有异质结的异双极晶体管。异双极晶体管是双异质结构的双极晶体管，其中用于形成其基极区的材料的带隙比用于形成其发射极和集电极区域的材料窄。

45. 发明授权

US5049806A Band-gap type voltage generating circuit for an ECL circuit 失效
标题翻译：用于ECL电路的带隙型电压发生电路
公开(公告)号：US5049806A
公开(公告)日：1991-09-17
申请号：US456556
申请日：1989-12-26
申请人： Yukihiro Urakawa , Masataka Matsui
发明人： Yukihiro Urakawa , Masataka Matsui
IPC分类号： G05F3/30
CPC分类号： G05F3/30 , Y10S323/907
摘要： A voltage generating circuit includes a first current source which generates a first current and a first voltage generating circuit which generates a first voltage having a first temperature dependency. A second voltage generating circuit generates a second voltage having a second temperature dependency different than the first temperature dependency. A voltage adder circuit coupled to the first and second voltage generating circuits adds the first and second voltages to generate a third voltage having no temperature dependency. A voltage replicating circuit coupled to the voltage adder circuit coupled to the voltage adder circuit replicates the third voltage as a fourth voltage having a level corresponding to the third voltage. A second current source generates a constant second current through a resistive element biased by the fourth voltage and a current replicating circuit coupled to the first and second current sources replicates the second current as the first current.
摘要翻译：电压产生电路包括产生第一电流的第一电流源和产生具有第一温度依赖性的第一电压的第一电压产生电路。第二电压产生电路产生具有不同于第一温度依赖性的第二温度依赖性的第二电压。耦合到第一和第二电压产生电路的电压加法器电路将第一和第二电压相加以产生不具有温度依赖性的第三电压。耦合到耦合到电压加法器电路的电压加法器电路的电压复制电路复制第三电压作为具有对应于第三电压的电平的第四电压。第二电流源通过由第四电压偏置的电阻元件产生恒定的第二电流，并且耦合到第一和第二电流源的电流复制电路复制第二电流作为第一电流。

46. 发明授权

US4992681A Logic level converting circuit 失效
标题翻译：逻辑电平转换电路
公开(公告)号：US4992681A
公开(公告)日：1991-02-12
申请号：US451316
申请日：1989-12-15
申请人： Yukihiro Urakawa , Masataka Matsui
发明人： Yukihiro Urakawa , Masataka Matsui
IPC分类号： H03K5/02 , H03K3/356 , H03K19/0175 , H03K19/0185 , H03K19/08
CPC分类号： H03K3/356069 , H03K3/356052 , H03K3/356147
摘要： A logic level converting circuit for converting an ECL level signal to a CMOS level signal comprises complementary signal generating means and level shifting means. The complementary signal generating means generates complementary signals in response to the ECL level input signal and a first reference voltage. The level shifting means operates as a flip-flop circuit, and includes a first and a second PMOS transistors which are either conductive or not conductive in response to the relationship between the complementary signals and a second reference voltage applied to the gate electrodes of the PMOS transistors.
摘要翻译：用于将ECL电平信号转换为CMOS电平信号的逻辑电平转换电路包括互补信号产生装置和电平转换装置。互补信号发生装置响应于ECL电平输入信号和第一参考电压产生互补信号。电平移动装置用作触发器电路，并且包括响应于互补信号之间的关系导通或不导电的第一和第二PMOS晶体管，以及施加到PMOS的栅电极的第二参考电压晶体管。

47. 发明授权

US08077499B2 Semiconductor integrated memory circuit and trimming method thereof 有权
标题翻译：半导体集成存储电路及其修整方法
公开(公告)号：US08077499B2
公开(公告)日：2011-12-13
申请号：US12540022
申请日：2009-08-12
申请人： Atsushi Kawasumi , Yukihiro Urakawa
发明人： Atsushi Kawasumi , Yukihiro Urakawa
IPC分类号： G11C11/00
CPC分类号： G11C7/1045 , G11C7/065 , G11C11/412
摘要： A latch circuit includes first and second inverters connected in a cross-coupling manner at a first node and a second node. A voltage application circuit applies a hot carrier generation voltage for generating hot carrier at a transistor included in the first inverter or the second inverter. An inverting circuit generates an inversion signal as an inverted signal of an amplified signal provided from the latch circuit to the bit line pair to provide the inversion signal to the first node and the second node.
摘要翻译：锁存电路包括在第一节点和第二节点处以交叉耦合方式连接的第一和第二反相器。电压施加电路在包含在第一逆变器或第二逆变器中的晶体管上施加用于产生热载流子的热载流子产生电压。反相电路产生作为从锁存电路向位线对提供的放大信号的反相信号的反相信号，以向第一节点和第二节点提供反转信号。

48. 发明申请

US20100052096A1 STACKED-CHIP DEVICE 有权
标题翻译：堆叠芯片设备
公开(公告)号：US20100052096A1
公开(公告)日：2010-03-04
申请号：US12546806
申请日：2009-08-25
申请人： Yukihiro Urakawa
发明人： Yukihiro Urakawa
IPC分类号： H01L23/52 , H01L29/86 , H01L25/07
CPC分类号： H01L25/0657 , H01L23/645 , H01L24/48 , H01L24/49 , H01L28/10 , H01L2224/32145 , H01L2224/48091 , H01L2224/49175 , H01L2225/06513 , H01L2225/06527 , H01L2924/00014 , H01L2924/15311 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A stacked-chip device includes a first inductive chip having a first function, a second inductive chip having a second function different from the first function, which is stacked on the first inductive chip, and a third inductive chip having the second function, which is stacked on the second inductive chip. Each of the first, second and third inductive chips has transmitting inductors which transmit data and receiving inductors which receive data. The transmitting inductors and the receiving inductors are disposed in line symmetry to an axis of symmetry. The axes of symmetry of the first, second and third inductive chips are overlapped. Each of the second and third inductive chips is disposed in upside-down or back to front to the first inductive chip.
摘要翻译：堆叠式芯片装置包括具有第一功能的第一感应芯片，具有与第一功能不同的第二功能的第二感应芯片，其堆叠在第一感应芯片上，以及具有第二功能的第三感应芯片，堆叠在第二感应芯片上。第一，第二和第三感应芯片中的每一个具有发送数据的发送电感器和接收数据的接收电感器。发射电感器和接收电感器以对称轴线对称设置。第一，第二和第三感应芯片的对称轴线重叠。第二感应芯片和第三感应芯片中的每一个被设置在第一感应芯片的上下或后面。

49. 发明授权

US07490018B2 Thermal management system 失效
标题翻译：热管理系统
公开(公告)号：US07490018B2
公开(公告)日：2009-02-10
申请号：US11698619
申请日：2007-01-26
申请人： Takashi Inukai , Yukihiro Urakawa
发明人： Takashi Inukai , Yukihiro Urakawa
IPC分类号： G06K1/08
CPC分类号： H01L23/34 , G06F1/206 , H01L2924/0002 , H01L2924/00
摘要： A thermal management system according to an embodiment of the present invention includes first and second thermo sensors embedded in a chip, a trimming control circuit which determines a characteristic of the first thermo sensor based on a trimming value, a nonvolatile memory which stores trimming data relating the characteristic of the first thermo sensor in an initial state and a system controller which provides temperature data to the trimming control circuit, wherein the temperature data relates a chip temperature detected by the second thermo sensor, wherein the trimming control circuit updates the trimming value based on the temperature data and the trimming data.
摘要翻译：根据本发明的实施例的热管理系统包括嵌入芯片中的第一和第二热敏传感器，修整控制电路，其基于修整值确定第一热敏传感器的特性;非易失性存储器，其存储有关的修整数据初始状态下的第一热敏传感器的特征和向修整控制电路提供温度数据的系统控制器，其中温度数据涉及由第二热敏传感器检测的芯片温度，其中微调控制电路基于修整值更新修整值关于温度数据和修剪数据。

50. 发明授权

US07466029B2 Chip on chip device including basic chips capable of functioning independently from each other, and a system in package device including the chip on chip device 失效
标题翻译：片上芯片器件包括能够彼此独立起作用的基本芯片，以及包括片上芯片器件的封装器件系统
公开(公告)号：US07466029B2
公开(公告)日：2008-12-16
申请号：US10787413
申请日：2004-02-27
申请人： Yukihiro Urakawa
发明人： Yukihiro Urakawa
IPC分类号： H01L25/00
CPC分类号： H01L25/18 , G11C5/04 , G11C7/1045 , G11C11/005 , G11C29/006 , G11C2029/1804 , H01L22/20 , H01L22/22 , H01L23/544 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L27/10897 , H01L2223/54406 , H01L2223/5446 , H01L2223/54473 , H01L2223/5448 , H01L2224/16145 , H01L2224/32225 , H01L2224/451 , H01L2224/48137 , H01L2224/48227 , H01L2224/73265 , H01L2924/01019 , H01L2924/01079 , H01L2924/1305 , H01L2924/13091 , H01L2924/19041 , H01L2924/00012 , H01L2924/00 , H01L2924/00015
摘要： In a wafer, a plurality of basic chips F is arranged therein. The basic chip F has a memory capacity of i-mega bytes. By dicing, a memory chip including four basic chips F is cut out of the wafer. The memory chip has a memory capacity of 4×i-mega bytes. A dicing line is interposed between four basic chips F configuring the memory chip, Four basic chips F can change word organization by a control signal individually.
摘要翻译：在晶片中，配置有多个基本芯片F. 基本芯片F具有i兆字节的存储容量。通过切割，从晶片切出包括四个基本芯片F的存储芯片。存储器芯片的存储容量为4xi兆字节。在配置存储器芯片的四个基本芯片F之间插入切割线，四个基本芯片F可以通过单独的控制信号改变单词组织。

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