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1. 发明授权

US08867868B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US08867868B2
公开(公告)日：2014-10-21
申请号：US11906725
申请日：2007-10-03
申请人： Natsuki Kushiyama , Yukihiro Urakawa
发明人： Natsuki Kushiyama , Yukihiro Urakawa
IPC分类号： G02B6/30 , G02B6/43 , G02B6/12 , G06F1/10
CPC分类号： G02B6/12002 , G02B6/43 , G02B2006/12104 , G06F1/105
摘要： A semiconductor integrated circuit according to an example of the present invention includes a chip substrate, first and second switches arranged on the chip substrate in which ON/OFF of an electrical signal path is directly controlled by an optical signal, a first light shielding layer arranged above the chip substrate, an optical waveguide layer arranged on the first light shielding layer, a second light shielding layer arranged on the optical waveguide layer, a reflecting plate arranged in the optical waveguide layer to change an advancing direction of the optical signal, and means for leading the optical signal to the first and second switches from an inside of the optical waveguide layer. The first and second light shielding layers reflect the optical signal, and the optical waveguide layer transmits the optical signal radially.
摘要翻译：根据本发明的实施例的半导体集成电路包括芯片基板，布置在芯片基板上的第一和第二开关，其中电信号路径的导通/截止由光信号直接控制，第一遮光层布置在芯片基板的上方配置有布置在第一遮光层上的光波导层，布置在光波导层上的第二遮光层，布置在光波导层中以改变光信号的前进方向的反射板，用于将光信号从光波导层的内部引导到第一和第二开关。第一和第二遮光层反射光信号，并且光波导层径向透射光信号。

2. 发明申请

US20100054025A1 SEMICONDUCTOR INTEGRATED MEMORY CIRCUIT AND TRIMMING METHOD THEREOF 有权
标题翻译：半导体集成存储器电路及其研制方法
公开(公告)号：US20100054025A1
公开(公告)日：2010-03-04
申请号：US12540022
申请日：2009-08-12
申请人： Atsushi Kawasumi , Yukihiro Urakawa
发明人： Atsushi Kawasumi , Yukihiro Urakawa
IPC分类号： G11C11/00 , G11C5/14 , G11C7/02
CPC分类号： G11C7/1045 , G11C7/065 , G11C11/412
摘要： A latch circuit includes first and second inverters connected in a cross-coupling manner at a first node and a second node. A voltage application circuit applies a hot carrier generation voltage for generating hot carrier at a transistor included in the first inverter or the second inverter. An inverting circuit generates an inversion signal as an inverted signal of an amplified signal provided from the latch circuit to the bit line pair to provide the inversion signal to the first node and the second node.
摘要翻译：锁存电路包括在第一节点和第二节点处以交叉耦合方式连接的第一和第二反相器。电压施加电路在包含在第一逆变器或第二逆变器中的晶体管上施加用于产生热载流子的热载流子产生电压。反相电路产生作为从锁存电路向位线对提供的放大信号的反相信号的反相信号，以向第一节点和第二节点提供反转信号。

3. 发明授权

US07501689B2 Upper-layer metal power standard cell 失效
标题翻译：上层金属电源标准电池
公开(公告)号：US07501689B2
公开(公告)日：2009-03-10
申请号：US11060727
申请日：2005-02-18
申请人： Takeshi Yoshida , Yukihiro Urakawa
发明人： Takeshi Yoshida , Yukihiro Urakawa
IPC分类号： H01L21/822
CPC分类号： H01L27/11807 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An upper-layer metal power standard cell comprises: a basic power metal layer which is disposed in an upper layer of a circuit and which supplies a power voltage from an outside of the upper-layer metal power standard cell; a transistor element layer which is formed in a predetermined arrangement on a circuit substrate under the basic power metal layer; and an inner wire layer which supplies the power voltage to the transistor element layer disposed under the basic power metal layer disposed in the upper layer from the basic power metal layer.
摘要翻译：上层金属电力标准电池包括：基本功率金属层，其设置在电路的上层中，并从上层金属电力标准电池的外部提供电力电压; 在基本功率金属层下的电路基板上以预定的布置形成的晶体管元件层; 以及内部电线层，其将功率电压提供到从基本功率金属层设置在上层中的基本功率金属层下方的晶体管元件层。

4. 发明授权

US07392152B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US07392152B2
公开(公告)日：2008-06-24
申请号：US11261536
申请日：2005-10-31
申请人： Takashi Inukai , Yukihiro Urakawa
发明人： Takashi Inukai , Yukihiro Urakawa
IPC分类号： G01K1/08
CPC分类号： G01K15/002 , G01K7/425
摘要： A semiconductor integrated circuit is applied to a system using a first power source voltage and a second power source voltage independent of the first power source voltage and that includes a first area to which the first power source voltage is supplied, a thermal sensor placed in the first area, and a first input path placed in the first area, for transferring trimming data that determine the control contents of the thermal sensor to the thermal sensor.
摘要翻译：半导体集成电路被应用于使用与第一电源电压无关的第一电源电压和第二电源电压的系统，并且包括提供第一电源电压的第一区域，放置在第一电源电压中的热传感器第一区域和放置在第一区域中的第一输入路径，用于将确定热传感器的控制内容的修整数据传送到热传感器。

5. 发明授权

US07251765B2 Semiconductor integrated circuit and method for testing a semiconductor integrated circuit 失效
标题翻译：半导体集成电路和半导体集成电路测试方法
公开(公告)号：US07251765B2
公开(公告)日：2007-07-31
申请号：US11001155
申请日：2004-12-02
申请人： Natsuki Kushiyama , Yukihiro Urakawa
发明人： Natsuki Kushiyama , Yukihiro Urakawa
IPC分类号： G01R31/28
CPC分类号： G01R31/31725 , G01R31/3016
摘要： A semiconductor integrated circuit includes a first delay circuit generating a first delay clock; a second delay circuit generating a second delay clock; a first register registering a value of a first delay of the first delay clock; a second register registering a value of a second delay of the second delay clock; a clock supplying circuit supplying a clock signal to the first and second delay circuits; a phase comparator detecting a phase difference between the first and second delay clocks; and a built-in test circuit configured to control the first and second registers so that the value of the first delay can be registered in the first register and the value of the second delay can be registered in the second register.
摘要翻译：半导体集成电路包括产生第一延迟时钟的第一延迟电路; 产生第二延迟时钟的第二延迟电路; 注册第一延迟时钟的第一延迟值的第一寄存器; 第二寄存器，其记录所述第二延迟时钟的第二延迟值; 时钟供给电路，向第一和第二延迟电路提供时钟信号; 相位比较器，检测第一和第二延迟时钟之间的相位差; 以及内置测试电路，被配置为控制第一和第二寄存器，使得可以将第一延迟的值登记在第一寄存器中，并且可以将第二延迟的值登记在第二寄存器中。

6. 发明申请

US20050110130A1 Semiconductor integrated circuit wiring design method and semiconductor integrated circuit 有权
标题翻译：半导体集成电路布线设计方法和半导体集成电路
公开(公告)号：US20050110130A1
公开(公告)日：2005-05-26
申请号：US10972463
申请日：2004-10-26
申请人： Shinji Kitabayashi , Yukihiro Urakawa
发明人： Shinji Kitabayashi , Yukihiro Urakawa
IPC分类号： H01L21/00 , G06F17/50 , H01L21/3205 , H01L21/768 , H01L21/82 , H01L21/822 , H01L23/52 , H01L23/522 , H01L23/528 , H01L27/04 , H01L21/4763
CPC分类号： G06F17/5077 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： The facility of operation in a manufacturing process and the reliability of the finished product can be improved by making a design based on two basic wiring pattern layers in which wiring traces are formed with regularity, and a basic via array layer inserted between the two basic wiring pattern layers, in which vias are formed with regularity
摘要翻译：可以通过基于布置有规则性的两个基本布线图案层进行设计来改进制造工艺中的操作设备和成品的可靠性，以及插入在两个基本布线之间的基本通孔阵列层图案层，其中通孔形成规则性

7. 发明授权

US06859070B2 Semiconductor integrated circuit device having flip-flops that can be reset easily 失效
标题翻译：具有能够容易复位的触发器的半导体集成电路器件
公开(公告)号：US06859070B2
公开(公告)日：2005-02-22
申请号：US10389876
申请日：2003-03-18
申请人： Koichi Kinoshita , Yukihiro Urakawa
发明人： Koichi Kinoshita , Yukihiro Urakawa
IPC分类号： G11C19/00 , G01R31/3185 , G11C29/10 , H01L21/822 , H01L27/04 , H03K3/037 , H03K19/00 , G01R31/28
CPC分类号： G01R31/318583 , G01R31/318544 , H03K3/0375
摘要： A semiconductor integrated circuit device includes a plurality of flip-flops, each of which has an external input terminal and external output terminal, the flip-flops being cascade-connected by having data output terminals respectively connected to data input terminals of the next-stage flip-flops. A reset signal is input via the external input terminal of the first-stage flip-flop and is sequentially transferred from the external output terminal thereof to the next-stage flip-flops. The reset signal is transferred via a transmission path different from the original data transmission path to reset all of the flip-flops.
摘要翻译：半导体集成电路器件包括多个触发器，每个触发器具有外部输入端和外部输出端，触发器通过分别连接到下一级的数据输入端的数据输出端级联连接人字拖。复位信号通过第一级触发器的外部输入端输入，并从其外部输出端依次传送到下一级触发器。复位信号经由与原始数据传输路径不同的传输路径传送，以复位所有触发器。

8. 发明授权

US06781805B1 Stacked MOSFET protection circuit 有权
标题翻译：堆叠MOSFET保护电路
公开(公告)号：US06781805B1
公开(公告)日：2004-08-24
申请号：US09667174
申请日：2000-09-21
申请人： Yukihiro Urakawa
发明人： Yukihiro Urakawa
IPC分类号： H02H900
CPC分类号： H03K17/102 , H01L27/0251 , H01L27/0255 , H01L27/0266 , H03F1/523 , H03K17/0822
摘要： Disclosed is a protection circuit capable of avoiding breakdown of a gate insulating film of a MOSFET and having an appropriate snap-back voltage in terms of reliability. In order to prevent breakdown of a gate insulating film of a MOSFET constituting a stacked protection circuit caused by application of a surge voltage between the gate and the drain of the MOSFET, a single or a plurality of diodes or a MOSFET switch is connected between the gate and the drain of the MOSFET for absorbing the surge voltage. The particular construction permits obtaining a large surge tolerance against the surge voltage entering through, for example, the external power source pad, making it possible to form a protection circuit used in I/O's tolerant to other power sources having an appropriate snap-back voltage against the external surge in assuring the reliability of the semiconductor device.
摘要翻译：公开了一种保护电路，其能够避免MOSFET的栅极绝缘膜的破坏，并且在可靠性方面具有适当的反冲电压。为了防止在MOSFET的栅极和漏极之间施加浪涌电压而构成堆叠保护电路的MOSFET的栅极绝缘膜的击穿，单个或多个二极管或MOSFET开关连接在栅极和漏极用于吸收浪涌电压。该特定结构允许针对通过例如外部电源焊盘进入的浪涌电压获得大的浪涌容限，使得可以形成用于I / O的保护电路，以使其具有适当的反馈电压的其他电源抵抗外部浪涌，确保半导体器件的可靠性。

9. 发明授权

US06429687B1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06429687B1
公开(公告)日：2002-08-06
申请号：US09489889
申请日：2000-01-24
申请人： Fujio Ishihara , Yukihiro Urakawa , Yukihiro Fujimoto
发明人： Fujio Ishihara , Yukihiro Urakawa , Yukihiro Fujimoto
IPC分类号： H03K1900
CPC分类号： H03K5/15026 , G06F1/10 , H03K5/088 , H03K5/13 , H03K19/00323 , H03K2005/00234
摘要： A semiconductor integrated circuit device comprises: a clock driver for outputting a clock signal; a clock wiring which is driven by the clock driver for transmitting the clock signal; a plurality of logic circuits which are connected to the clock wiring to be synchronously operated in response to the clock signal; and a plurality of delay circuits, each of which is provided between a corresponding one of the logic circuits and the clock wiring for delaying the clock signal, wherein a delay amount of each of the delay circuits is designed so that the delay amounts of the clock signal from the output of the clock driver to the inputs of the logic circuits are equal to each other. Thus, it is possible to reduce clock skew and to evade an increase in layout area.
摘要翻译：一种半导体集成电路器件，包括：用于输出时钟信号的时钟驱动器; 由时钟驱动器驱动的用于发送时钟信号的时钟布线; 连接到所述时钟布线的多个逻辑电路，以响应于所述时钟信号同步操作; 以及多个延迟电路，每个延迟电路设置在对应的一个逻辑电路和用于延迟时钟信号的时钟布线之间，其中每个延迟电路的延迟量被设计成使得时钟的延迟量从时钟驱动器的输出到逻辑电路的输入的信号彼此相等。因此，可以减少时钟偏移并避免布局区域的增加。

10. 发明授权

US06278300B1 I/O interface circuit, semiconductor chip and semiconductor system 失效
标题翻译： I / O接口电路，半导体芯片和半导体系统
公开(公告)号：US06278300B1
公开(公告)日：2001-08-21
申请号：US09146034
申请日：1998-09-02
申请人： Yukihiro Urakawa
发明人： Yukihiro Urakawa
IPC分类号： H03K190175
CPC分类号： H03K19/018592
摘要： A push-pull output buffer contained in an I/O interface circuit of the present invention comprises a P channel MOSFET and a N channel MOSFET. The P channel MOSFET is connected between an I/O node connected to an external circuit through a transmission path and a first potential node to which a first potential is applied. The N channel MOSFET is connected between a second potential node to which a second potential is applied and the I/O node. On/off status of the P channel MOSFET and N channel MOSFET are controlled depending on an input mode for inputting a signal from an external circuit and an output mode for outputting a signal to the external circuit through a transmission path. In this I/O interface circuit, the first and second potentials are terminating potentials, and when input mode is selected, out of the P channel MOSFET and N channel MOSFET, the MOSFET connected to a potential node to which a terminating potential is applied is controlled to be always on.
摘要翻译：包含在本发明的I / O接口电路中的推挽输出缓冲器包括P沟道MOSFET和N沟道MOSFET。 P沟道MOSFET连接在通过传输路径连接到外部电路的I / O节点和施加第一电位的第一电位节点之间。 N沟道MOSFET连接在施加第二电位的第二电位节点和I / O节点之间。根据用于输入来自外部电路的信号的输入模式和通过传输路径将信号输出到外部电路的输出模式来控制P沟道MOSFET和N沟道MOSFET的开/关状态。在该I / O接口电路中，第一和第二电位为终止电位，当选择输入模式时，从P沟道MOSFET和N沟道MOSFET中，连接到施加了终止电位的电位节点的MOSFET为控制着永远在上。

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