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41. 发明申请

US20050121688A1 Light emitting device 有权
标题翻译：发光装置
公开(公告)号：US20050121688A1
公开(公告)日：2005-06-09
申请号：US11001414
申请日：2004-12-02
申请人： Youichi Nagai , Makoto Kiyama , Takao Nakamura , Takashi Sakurada , Katsushi Akita , Koji Uematsu , Ayako Ikeda , Koji Katayama , Susumu Yoshimoto
发明人： Youichi Nagai , Makoto Kiyama , Takao Nakamura , Takashi Sakurada , Katsushi Akita , Koji Uematsu , Ayako Ikeda , Koji Katayama , Susumu Yoshimoto
IPC分类号： H01L33/12 , H01L33/32 , H01L33/42 , H01L33/50 , H01L33/56 , H01L33/60 , H01L33/62 , H01L33/00
CPC分类号： H01L33/02 , H01L33/0075 , H01L33/20 , H01L33/22 , H01L33/32 , H01L33/38 , H01L33/58 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/73265 , H01L2924/01004 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/12041 , H01L2924/19041 , H01L2924/00 , H01L2924/00014
摘要： A light emitting device includes a nitride semiconductor substrate with a resistivity of 0.5 Ω·cm or less, an n-type nitride semiconductor layer and a p-type nitride semiconductor layer placed more distantly from the nitride semiconductor substrate than the n-type nitride semiconductor layer at a first main surface side of the nitride semiconductor substrate, and a light emitting layer placed between the n-type nitride semiconductor layer and the p-type nitride semiconductor layer, wherein one of the nitride semiconductor substrate and the p-type nitride semiconductor layer is mounted at the top side which emits light and the other is placed at the down side, and a single electrode is placed at the top side. Therefore, there is provided a light emitting device which has a simple configuration thereby making it easy to fabricate, can provide a high light emission efficiency for a long time period, and can be easily miniaturized.
摘要翻译：发光器件包括电阻率为0.5Ω·cm以下的氮化物半导体衬底，与氮化物半导体衬底相比，n型氮化物半导体层和p型氮化物半导体层比n型氮化物半导体在氮化物半导体衬底的第一主表面侧的层和位于n型氮化物半导体层和p型氮化物半导体层之间的发光层，其中氮化物半导体衬底和p型氮化物半导体之一层安装在发光的顶侧，而另一个放置在下侧，并且在顶侧放置单个电极。因此，提供了一种发光装置，其具有简单的结构，从而易于制造，可以长时间提供高的发光效率，并且可以容易地小型化。

42. 发明授权

US08497185B2 Method of manufacturing semiconductor wafer, and composite base and composite substrate for use in that method 有权
标题翻译：制造半导体晶片的方法以及用于该方法的复合基板和复合基板
公开(公告)号：US08497185B2
公开(公告)日：2013-07-30
申请号：US13107286
申请日：2011-05-13
申请人： Yuki Seki , Issei Satoh , Koji Uematsu , Yoshiyuki Yamamoto
发明人： Yuki Seki , Issei Satoh , Koji Uematsu , Yoshiyuki Yamamoto
IPC分类号： H01L29/02 , H01L21/762 , H01L29/22
CPC分类号： H01L29/0684 , B32B2264/102 , B32B2307/704 , B32B2457/14 , H01L21/76254
摘要： A method of manufacturing a semiconductor wafer of the present invention includes the steps of: obtaining a composite base by forming a base surface flattening layer having a surface RMS roughness of not more than 1.0 nm on a base; obtaining a composite substrate by attaching a semiconductor crystal layer to a side of the composite base where the base surface flattening layer is located; growing at least one semiconductor layer on the semiconductor crystal layer of the composite substrate; and obtaining the semiconductor wafer including the semiconductor crystal layer and the semiconductor layer by removing the base surface flattening layer by wet etching and thereby separating the semiconductor crystal layer from the base. Thus, a method of manufacturing a semiconductor wafer capable of efficiently manufacturing the semiconductor wafer regardless of the type of a base, and a composite base and a composite substrate suitably used in that manufacturing method are provided to efficiently manufacture a semiconductor device.
摘要翻译：本发明的制造半导体晶片的方法包括以下步骤：通过在基底上形成表面RMS粗糙度不大于1.0nm的基面平坦化层来获得复合基底; 通过将半导体晶体层附着到所述复合基底的所述基面平坦化层所在的一侧来获得复合基板; 在复合衬底的半导体晶体层上生长至少一个半导体层; 以及通过湿法蚀刻去除基底表面平坦化层，从而将半导体晶体层与基底分离，从而获得包括半导体晶体层和半导体层的半导体晶片。因此，提供一种制造半导体晶片的方法，而不管基底的类型如何，以及适用于该制造方法的复合基底和复合基底都能有效地制造半导体晶片，以有效地制造半导体器件。

43. 发明申请

US20120329245A1 Group III Nitride Crystal and Method for Producing the Same 有权
标题翻译： III族氮化物晶体及其制造方法
公开(公告)号：US20120329245A1
公开(公告)日：2012-12-27
申请号：US13338263
申请日：2011-12-28
申请人： Koji Uematsu , Hideki Osada , Seiji Nakahata , Shinsuke Fujiwara
发明人： Koji Uematsu , Hideki Osada , Seiji Nakahata , Shinsuke Fujiwara
IPC分类号： H01L21/78 , C01B21/06
CPC分类号： H01L29/045 , C01B21/0632 , C01P2002/90 , C01P2006/12 , C30B29/403 , C30B29/406 , C30B33/06 , H01L21/02389 , H01L21/0243 , H01L21/02433 , H01L21/0254 , H01L21/02609 , H01L21/0262 , H01L21/02658 , H01L33/16 , H01L33/32
摘要： A method for producing a group III nitride crystal in the present invention includes the steps of cutting a plurality of group III nitride crystal substrates 10p and 10q having a main plane from a group III nitride bulk crystal 1, the main planes 10pm and 10qm having a plane orientation with an off-angle of five degrees or less with respect to a crystal-geometrically equivalent plane orientation selected from the group consisting of {20-21}, {20-2-1}, {22-41}, and {22-4-1}, transversely arranging the substrates 10p and 10q adjacent to each other such that the main planes 10pm and 10qm of the substrates 10p and 10q are parallel to each other and each [0001] direction of the substrates 10p and 10q coincides with each other, and growing a group III nitride crystal 20 on the main planes 10pm and 10qm of the substrates 10p and 10q.
摘要翻译：本发明的III族氮化物晶体的制造方法包括从III族氮化物本体晶体1切割出具有主面的多个III族氮化物晶体基板10p，10q，主平面10pm，10qm具有平面取向相对于从{20-21}，{20-2-1}，{22-41}和{22-41}组成的组中的晶体 - 几何等效平面取向具有5度或更小的偏离角度， 22-4-1}，使基板10p和10q彼此相邻地布置，使得基板10p和10q的主平面10pm和10qm彼此平行，并且基板10p和10q的每个[0001]方向与并且在基板10p和10q的主平面10pm和10qm上生长III族氮化物晶体20。

44. 发明授权

US08304334B2 III-V compound crystal and semiconductor electronic circuit element 有权
公开(公告)号：US08304334B2
公开(公告)日：2012-11-06
申请号：US13368329
申请日：2012-02-07
申请人： Seiji Nakahata , Koji Uematsu , Ryu Hirota
发明人： Seiji Nakahata , Koji Uematsu , Ryu Hirota
IPC分类号： H01L21/28
CPC分类号： C30B25/02 , C30B25/183 , C30B29/40 , C30B29/403 , C30B29/406 , H01L21/0237 , H01L21/0242 , H01L21/02455 , H01L21/02458 , H01L21/02538 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L21/02642 , H01L21/02647 , H01S5/323
摘要： Favorable-quality III-V crystals are easily obtained at low cost without causing cracks, even when using a variety of substrates, and can be used to manufacture semiconductor devices with good quality and at high yields. The III-V crystals are characterized by the following properties: the carrier concentration, resistivity, and dislocation density of the III-V compound crystal are uniform to within ±30% variation along the surface; the III-V compound crystal is misoriented from the c-plane such that the crystal surface does not include any region where its off-axis angle with the c-plane is 0°; and the full width at half-maximum in XRD at the crystal center of the III-V compound is not greater than 150 arcsec.

45. 发明授权

US08258051B2 Method of manufacturing III-nitride crystal, and semiconductor device utilizing the crystal 有权
标题翻译：制造III族氮化物晶体的方法以及利用晶体的半导体器件
公开(公告)号：US08258051B2
公开(公告)日：2012-09-04
申请号：US12467297
申请日：2009-05-17
申请人： Naho Mizuhara , Koji Uematsu , Michimasa Miyanaga , Keisuke Tanizaki , Hideaki Nakahata , Seiji Nakahata , Takuji Okahisa
发明人： Naho Mizuhara , Koji Uematsu , Michimasa Miyanaga , Keisuke Tanizaki , Hideaki Nakahata , Seiji Nakahata , Takuji Okahisa
IPC分类号： H01L21/20 , C30B19/12 , C30B25/18
CPC分类号： H01L29/045 , C30B19/02 , C30B23/025 , C30B25/20 , C30B29/403 , C30B29/406 , H01L21/02389 , H01L21/02433 , H01L21/0254 , H01L21/02658 , H01L29/2003 , Y10T428/24752
摘要： The present III-nitride crystal manufacturing method, a method of manufacturing a III-nitride crystal (20) having a major surface (20m) of plane orientation other than {0001}, designated by choice, includes: a step of slicing III-nitride bulk crystal (1) into a plurality of III-nitride crystal substrates (10p), (10q) having major surfaces (10pm), (10qm) of the designated plane orientation; a step of disposing the substrates (10p), (10q) adjoining each other sideways in such a way that the major surfaces (10pm), (10qm) of the substrates (10p), (10q) parallel each other and so that the [0001] directions in the substrates (10p), (10q) are oriented in the same way; and a step of growing III-nitride crystal (20) onto the major surfaces (10pm), (10qm) of the substrates (10p), (10q).
摘要翻译：本III-氮化物晶体制造方法，通过选择指定的具有除{0001}以外的面取向主面（20m）的III族氮化物晶体（20）的制造方法包括：将III族氮化物晶体大块晶体（1）分成多个具有指定平面取向的主表面（10pm），（10qm）的III族氮化物晶体基板（10p），（10q）将基板（10p），（10q），（10q）的主表面（10pm），（10qm）彼此平行的方式设置为彼此相邻的基板（10p），（10q）的步骤，（10p），（10q）的方向相同的方向取向; 以及在衬底（10p），（10q）的主表面（10μm），（10qm）上生长III族氮化物晶体（20）的步骤。

46. 发明授权

US07943964B2 AlxGayIn1−x−yN crystal substrate, semiconductor device, and method of manufacturing the same 有权
标题翻译： AlxGayIn1-x-yN晶体基板，半导体器件及其制造方法
公开(公告)号：US07943964B2
公开(公告)日：2011-05-17
申请号：US12096986
申请日：2006-10-16
申请人： Shinsuke Fujiwara , Tomoki Uemura , Takuji Okahisa , Koji Uematsu , Manabu Okui , Muneyuki Nishioka , Shin Hashimoto
发明人： Shinsuke Fujiwara , Tomoki Uemura , Takuji Okahisa , Koji Uematsu , Manabu Okui , Muneyuki Nishioka , Shin Hashimoto
IPC分类号： H01L33/30
CPC分类号： H01L21/02658 , C30B25/02 , C30B29/403 , H01L21/02389 , H01L21/0254
摘要： An AlxGayIn1-x-yN crystal substrate of the present invention has a main plane having an area of at least 10 cm2. The main plane has an outer region located within 5 mm from an outer periphery of the main plane, and an inner region corresponding to a region other than the outer region. The inner region has a total dislocation density of at least 1×102 cm−2 and at most 1×106 cm−2. It is thereby possible to provide an AlxGayIn1-x-yN crystal substrate having a large size and a suitable dislocation density for serving as a substrate for a semiconductor device, a semiconductor device including the AlxGayIn1-x-yN crystal substrate, and a method of manufacturing the same.
摘要翻译：本发明的Al x Ga y In 1-x-y N晶体基板具有面积为至少10cm 2的主平面。主平面具有位于与主平面的外周5mm以内的外部区域和与外部区域以外的区域对应的内部区域。内部区域的总位错密度为1×102cm 2以上且1×10 6 cm -2以下。由此，可以提供具有大尺寸和合适的位错密度的Al x Ga y In 1-x-y N晶体基板，用作半导体器件的基板，包括Al x Ga y In 1-x-y N晶体基板的半导体器件，以及制造相同。

47. 发明授权

US07869927B2 Retarder control device for working vehicle 有权
标题翻译：工作车辆减速器控制装置
公开(公告)号：US07869927B2
公开(公告)日：2011-01-11
申请号：US11994631
申请日：2006-07-07
申请人： Koji Uematsu
发明人： Koji Uematsu
IPC分类号： B60T7/12 , B60T10/00
CPC分类号： B60T10/00
摘要： A retarder control system for a working vehicle includes: an input shaft revolution speed detector (121) for detecting an input shaft revolution speed of a transmission; a running state acquirer (33) for acquiring a running state of the working vehicle; a threshold map storage (321) for storing a plurality of threshold maps of an input shaft revolution speed at which the retarder braking control starts or ends in accordance with a predetermined running state of the working vehicle; a threshold map selector (34) for selecting a threshold map from the threshold maps stored in the threshold map storage based on the running state acquired by the running state acquirer; and a braking controller (35) for retarder braking control based on the input shaft revolution speed of the transmission detected by the input revolution speed detector (121) and the threshold map selected by the threshold map selector (34).
摘要翻译：一种用于作业车辆的减速器控制系统包括：用于检测变速器的输入轴转速的输入轴转速检测器（121）用于获取作业车辆的行驶状态的运行状态获取器（33）; 阈值图存储装置，用于根据作业车辆的预定行驶状态来存储延迟器制动控制开始或结束的输入轴转速的多个阈值图; 阈值图选择器，用于根据由运行状态获取器获取的运行状态，从存储在阈值图存储器中的阈值图选择阈值图; 以及基于由输入转速检测器（121）检测到的变速器的输入轴转速和由阈值图选择器（34）选择的阈值图的用于延迟器制动控制的制动控制器（35）。

48. 发明授权

US07858502B2 Fabrication method and fabrication apparatus of group III nitride crystal substance 有权
标题翻译： III族氮化物晶体物质的制造方法和制造装置
公开(公告)号：US07858502B2
公开(公告)日：2010-12-28
申请号：US12540492
申请日：2009-08-13
申请人： Hitoshi Kasai , Takuji Okahisa , Shunsuke Fujita , Naoki Matsumoto , Hideyuki Ijiri , Fumitaka Sato , Kensaku Motoki , Seiji Nakahata , Koji Uematsu , Ryu Hirota
发明人： Hitoshi Kasai , Takuji Okahisa , Shunsuke Fujita , Naoki Matsumoto , Hideyuki Ijiri , Fumitaka Sato , Kensaku Motoki , Seiji Nakahata , Koji Uematsu , Ryu Hirota
IPC分类号： H01L21/00
CPC分类号： H01L21/02617 , C23C16/303 , C23C16/4405 , C23C16/4488 , C30B23/02 , C30B25/02 , C30B29/403
摘要： A fabrication method of a group III nitride crystal substance includes the steps of cleaning the interior of a reaction chamber by introducing HCl gas into the reaction chamber, and vapor deposition of a group III nitride crystal substance in the cleaned reaction chamber. A fabrication apparatus of a group III nitride crystal substance includes a configuration to introduce HCl gas into the reaction chamber, and a configuration to grow a group III nitride crystal substance by HVPE. Thus, a fabrication method of a group III nitride crystal substance including the method of effectively cleaning deposits adhering inside the reaction chamber during crystal growth, and a fabrication apparatus employed in the fabrication method are provided.
摘要翻译： III族氮化物晶体物质的制造方法包括以下步骤：通过将HCl气体引入反应室来清洗反应室的内部，并将III族氮化物结晶物质气相沉积在清洁的反应室中。 III族氮化物晶体物质的制造装置包括将HCl气体引入反应室的结构，以及通过HVPE生长III族氮化物结晶物质的结构。因此，提供了包括在晶体生长期间有效清洁附着在反应室内的沉积物的方法的III族氮化物晶体物质的制造方法以及制造方法中使用的制造装置。

49. 发明授权

US07834423B2 Method of producing a nitride semiconductor device and nitride semiconductor device 有权
标题翻译：氮化物半导体器件和氮化物半导体器件的制造方法
公开(公告)号：US07834423B2
公开(公告)日：2010-11-16
申请号：US12409752
申请日：2009-03-24
申请人： Seiji Nakahata , Koji Uematsu , Hideaki Nakahata
发明人： Seiji Nakahata , Koji Uematsu , Hideaki Nakahata
IPC分类号： H01L29/20
CPC分类号： H01L21/7813 , H01L21/02389 , H01L21/0254 , H01L21/02609 , H01L21/02647 , H01L29/2003 , H01L29/34 , H01L29/66462 , H01L29/7787 , H01L29/872 , H01L33/007 , H01L33/0079
摘要： AlxInyGa1-x-yN (0≦x≦1; 0≦x≦1; 0≦x+y≦1) layered device chips are produced by the steps of preparing a defect position controlled substrate of AlxInyGa1-x-yN (0≦x≦1; 0≦y≦1; 0≦x+y≦1) having a closed loop network defect accumulating region H of slow speed growth and low defect density regions ZY of high speed growth enclosed by the closed loop network defect accumulating region H, growing epitaxial upper layers B selectively on the low defect density regions ZY, harmonizing outlines and insides of device chips composed of the upper layers B with the defect accumulating region H and the low defect density regions ZY respectively, forming upper electrodes on the upper layers B or not forming the electrodes, dissolving bottom parts of the upper layers B by laser irradiation or mechanical bombardment, and separating the upper layer parts B as device chips C from each other and from the substrate S. Chip-separation is done instantly by the high power laser irradiation or mechanical shock without cutting the substrate S. The defect position controlled substrate S is repeatedly reused.
摘要翻译： AlxInyGa1-x-yN（0＆nlE; x＆nlE; 1; 0＆nlE; x＆nlE; 1; 0＆nlE; x + y＆nlE; 1）层状器件芯片是通过制备Al x In y Ga 1-x-y N的缺陷位置受控衬底（0＆具有由闭环网络缺陷累积区域包围的高速增长的低速增长的闭环网络缺陷累积区域H和低缺陷密度区域ZY的x＆lt; 1; 0＆nlE; y＆nlE; 1; 0＆nlE; x + y＆ H，选择性地在低缺陷密度区域ZY上生长外延上层B，分别与缺陷累积区域H和低缺陷密度区域ZY一起构成由上层B组成的器件芯片的外形和内部，在上部形成上部电极层B或不形成电极，通过激光照射或机械轰击溶解上层B的底部，并将上层部分B作为器件芯片C彼此分离，并从衬底S分离。芯片分离通过高宝激光照射或机械冲击而不切割基板S.缺陷位置控制的基板S被重复使用。

50. 发明授权

US07772585B2 Nitride semiconductor substrate and method of producing same 有权
标题翻译：氮化物半导体衬底及其制造方法
公开(公告)号：US07772585B2
公开(公告)日：2010-08-10
申请号：US11446955
申请日：2006-06-06
申请人： Koji Uematsu , Fumitaka Sato , Ryu Hirota , Seiji Nakahata , Hideaki Nakahata
发明人： Koji Uematsu , Fumitaka Sato , Ryu Hirota , Seiji Nakahata , Hideaki Nakahata
IPC分类号： H01L31/00 , C30B25/00 , H01L21/00
CPC分类号： C30B29/403 , C30B25/18 , C30B29/406 , H01L21/0237 , H01L21/02395 , H01L21/0242 , H01L21/02433 , H01L21/02458 , H01L21/0254 , H01L21/0262 , H01L21/02631 , H01L21/02639 , H01L21/02642 , H01L21/02647
摘要： A nitride semiconductor crystal substrate is produced by forming a network mask repeating a closed loop unit shape upon an undersubstrate, growing a nitride semiconductor crystal in vapor phase, producing convex facet hills covered with facets on exposed parts Π, forming outlining concavities on mask-covered parts , not burying the facets, maintaining the convex facet hills on Π and the network concavities on , excluding dislocations in the facet hills down to the outlining concavities on , forming a defect accumulating region H on , decreasing dislocations in the facet hills and improving the facet hills to low defect density single crystal regions Z, producing a rugged nitride crystal, and slicing and polishing the nitride crystal into mirror nitride crystal wafers. After the fabrication of devices on the nitride wafer, dry-etching or wet etching of hot KOH or NaOH divides the device-carrying wafer into chips by corroding the network defect accumulating region H.
摘要翻译：通过在下衬底上形成重复闭环单元形状的网络掩模，在气相中生长氮化物半导体晶体，产生在暴露部分“Pgr”上覆盖有小面的凸面小丘，从而形成氮化物半导体晶体衬底; 覆盖部分，不掩埋小面，保持凸面小丘在＆Pgr; 和网络凹面，不考虑小平面上的位错，形成凹陷凹陷，形成缺陷积聚区H，减小了小平面山丘的位错，改善了小丘到低缺陷密度单晶区Z，产生了坚固的氮化物晶体，并将氮化物晶体切割和研磨成镜状氮化物晶片。在氮化物晶片上的器件制造之后，通过腐蚀网络缺陷累积区域H将热的KOH或NaOH的干蚀刻或湿法蚀刻将装载的晶片分成芯片。

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