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41. 发明申请

US20080284477A1 ON-CHIP JITTER MEASUREMENT CIRCUIT 失效
标题翻译：片上抖动测量电路
公开(公告)号：US20080284477A1
公开(公告)日：2008-11-20
申请号：US12125730
申请日：2008-05-22
申请人： David F. Heidel , Keith A. Jenkins
发明人： David F. Heidel , Keith A. Jenkins
IPC分类号： H03L7/24
CPC分类号： H04L1/205 , G01R29/26 , G01R31/3016 , G01R31/31709 , G01R31/31725
摘要： An on-chip jitter measurement circuit and corresponding method are provided for receiving a reference clock and a signal of interest, including a latch for comparing the arrival time of the signal of interest to the reference clock, a delay chain in signal communication with the reference clock for varying the arrival time of the reference clock, the delay chain having a first stage, a middle stage, and a last stage, a voltage controller in signal communication with the middle stage of the delay chain for controlling the delay of the arrival time of the reference clock while permitting the first and last stages of the delay chain to retain a full voltage swing independent of the delay.
摘要翻译：提供片上抖动测量电路和相应的方法，用于接收参考时钟和感兴趣的信号，包括用于比较感兴趣信号的到达时间与参考时钟的锁存器，与参考时钟信号通信的延迟链用于改变参考时钟的到达时间的时钟，具有第一级，中级和最后级的延迟链，与延迟链的中间级信号通信的电压控制器，用于控制到达时间的延迟的参考时钟，同时允许延迟链的第一级和最后级保持独立于延迟的全电压摆幅。

42. 发明授权

US07439755B2 Electronic circuit for measurement of transistor variability and the like 有权
标题翻译：用于测量晶体管变化性的电子电路等
公开(公告)号：US07439755B2
公开(公告)日：2008-10-21
申请号：US11669250
申请日：2007-01-31
申请人： Keith A. Jenkins , Jae-Joon Kim , Rahul M. Rao
发明人： Keith A. Jenkins , Jae-Joon Kim , Rahul M. Rao
IPC分类号： G01R31/26
CPC分类号： G01R31/2621
摘要： An electronic circuit includes an output terminal and at least a first measuring FET. The second drain-source terminals of a plurality of FETS to be tested are interconnected with the first drain-source terminal of the first measuring FET and the output terminal. The second drain-source terminal of the first measuring FET is interconnected with a first biasing terminal. The first drain-source terminals of the FETS to be tested are interconnected with a second biasing terminal. A state machine is coupled to the gates of the FETS to be tested and the gate of the first measuring FET. The state machine is configured to energize the gate of the first measuring FET and to sequentially energize the gates of the FETS to be tested, so that an output voltage appears on the output terminal. Circuitry to compare the output voltage to a reference value is also provided.
摘要翻译：电子电路包括输出端子和至少第一测量FET。待测试的多个FET的第二漏极 - 源极端子与第一测量FET和输出端子的第一漏极 - 源极端子互连。第一测量FET的第二漏极 - 源极端子与第一偏置端子互连。要测试的FETS的第一漏极 - 源极端子与第二偏置端子互连。状态机耦合到要测试的FETs的栅极和第一测量FET的栅极。状态机被配置为对第一测量FET的栅极通电并且顺序地激励要测试的FETS的栅极，使得输出电压出现在输出端子上。还提供了将输出电压与参考值进行比较的电路。

43. 发明申请

US20080055036A1 Electrical component tuned by conductive layer deletion 失效
标题翻译：通过导电层删除调整的电气元件
公开(公告)号：US20080055036A1
公开(公告)日：2008-03-06
申请号：US11512014
申请日：2006-08-29
申请人： Keith A. Jenkins , Mounir Meghelli
发明人： Keith A. Jenkins , Mounir Meghelli
IPC分类号： H01F5/00
CPC分类号： H01F17/0013 , H01F21/12 , H01F41/045 , H01F2021/125 , H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/3011 , H05K1/165 , H01L2924/00
摘要： Techniques are disclosed for fabricating tunable electrical components in integrated circuits. For example, a method of tuning a value of an electrical component, such as a planar inductor, includes the steps of placing a conductive layer in proximity of the electrical component, and adjusting an amount of material that constitutes the conductive layer such that the value of the electrical component is tuned to a particular value. The adjustment step may be performed so as to select a frequency band with which the inductor is associated or to correct a manufacturing deviation in a frequency with which the inductor is associated.
摘要翻译：公开了用于在集成电路中制造可调电气部件的技术。例如，调整诸如平面电感器的电气部件的值的方法包括以下步骤：将导电层放置在电气部件附近，以及调整构成导电层的材料的量，使得值的电气元件被调谐到特定的值。可以执行调整步骤以便选择与电感器相关联的频带或者校正与电感器相关联的频率中的制造偏差。

44. 发明授权

US08890542B2 On-chip measurement of AC variability in individual transistor devices 有权
公开(公告)号：US08890542B2
公开(公告)日：2014-11-18
申请号：US13604090
申请日：2012-09-05
申请人： Karthik Balakrishnan , Keith A. Jenkins
发明人： Karthik Balakrishnan , Keith A. Jenkins
IPC分类号： G01R27/28 , G01R31/28 , G01R31/26
CPC分类号： G01R31/2621 , G01R31/2882
摘要： An apparatus for determining alternating current (AC) delay variation of a transistor device under test includes a ring oscillator, the ring oscillator having the transistor device under test configured within a feedback path of the ring oscillator; and circuitry configured to measure a difference between a first signal delay path and a second signal delay path, the first signal delay path being between a gate terminal and a drain terminal of the transistor device under test, and the second signal delay path being between a source terminal and the drain terminal of the transistor device under test.

45. 发明申请

US20130212414A1 REDUCING PERFORMANCE DEGRADATION IN BACKUP SEMICONDUCTOR CHIPS 有权
标题翻译：降低备用半导体芯片的性能降低
公开(公告)号：US20130212414A1
公开(公告)日：2013-08-15
申请号：US13396345
申请日：2012-02-14
申请人： Aditya Bansal , Manjul Bhushan , Keith A. Jenkins , Jae-Joon Kim , Barry P. Linder , Kai Zhao
发明人： Aditya Bansal , Manjul Bhushan , Keith A. Jenkins , Jae-Joon Kim , Barry P. Linder , Kai Zhao
IPC分类号： G06F1/32
CPC分类号： G06F11/004 , G06F1/206 , G06F1/3293 , G06F11/00 , G06F11/2041 , G06F11/2043 , G06F17/505 , G06F2217/70 , G06F2217/72 , G06F2217/80 , H04M15/00 , Y02D10/122 , Y02D10/16
摘要： A system has at least a first circuit portion and a second circuit portion. The first circuit portion is operated at normal AC frequency. The second circuit portion is operated in a back-up mode at low AC frequency, such that the second circuit portion can rapidly come-online but has limited temperature bias instability degradation. The second circuit portion can then be brought on-line and operated at the normal AC frequency. A system including first and second circuit portions and a control unit, as well as a computer program product, are also provided.
摘要翻译：系统具有至少第一电路部分和第二电路部分。第一电路部分以正常交流频率工作。第二电路部分以低AC频率在备用模式下操作，使得第二电路部分可以快速上线，但是温度偏差不稳定性降低有限。然后可以将第二电路部分在线并在正常交流频率下操作。还提供了包括第一和第二电路部分和控制单元以及计算机程序产品的系统。

46. 发明申请

US20130049791A1 On-Chip Delay Measurement Through a Transistor Array 审中-公开
标题翻译：通过晶体管阵列进行片上延迟测量
公开(公告)号：US20130049791A1
公开(公告)日：2013-02-28
申请号：US13601122
申请日：2012-08-31
申请人： Keith A. Jenkins , Jae-Joon Kim , Rahul M. Rao
发明人： Keith A. Jenkins , Jae-Joon Kim , Rahul M. Rao
IPC分类号： G01R31/26
CPC分类号： G11C29/023 , G01R31/31725 , G11C2029/5002
摘要： A delay is measured through an array of transistors by selecting one transistor in the array; and applying a clock signal to the selected transistor. An output of the selected transistor is applied to a first input of a logic gate and a second clock signal based on the clock signal is applied to a second input of the logic gate. An output of the logic gate indicates a difference in arrival times of the signals at the two inputs. A clock signal can be applied to the selected transistor and a variable delay circuit. An output of the selected transistor is applied to a data input of a latch while an output of the variable delay circuit is applied to a clock input of the latch. The delay applied by the variable delay circuit is adjusted until a predefined transition is detected. The delay variation among the transistors can be obtained.
摘要翻译：通过选择阵列中的一个晶体管，通过晶体管阵列来测量延迟; 以及将时钟信号施加到所选择的晶体管。所选择的晶体管的输出被施加到逻辑门的第一输入，并且基于时钟信号的第二时钟信号被施加到逻辑门的第二输入。逻辑门的输出表示两个输入端的信号的到达时间差。时钟信号可以施加到所选择的晶体管和可变延迟电路。所选择的晶体管的输出被施加到锁存器的数据输入，而可变延迟电路的输出被施加到锁存器的时钟输入。调整由可变延迟电路施加的延迟，直到检测到预定的转换。可以获得晶体管之间的延迟变化。

47. 发明授权

US08362477B2 High density memory device 有权
标题翻译：高密度存储器件
公开(公告)号：US08362477B2
公开(公告)日：2013-01-29
申请号：US12729856
申请日：2010-03-23
申请人： Tymon Barwicz , Keith A. Jenkins , Supratik Guha
发明人： Tymon Barwicz , Keith A. Jenkins , Supratik Guha
IPC分类号： H01L29/12
CPC分类号： G11C11/404 , G11C13/0007 , H01L28/40 , H01L49/003
摘要： A memory device and a method of forming the same are provided. The memory device includes a substrate; a set of electrodes disposed on the substrate; a dielectric layer formed between the set of electrodes; and a transition metal oxide layer formed between the set of electrodes, the transition metal oxide layer configured to undergo a metal-insulator transition (MIT) to perform a read or write operation.
摘要翻译：提供了一种存储器件及其形成方法。存储器件包括衬底; 设置在基板上的一组电极; 形成在该组电极之间的电介质层; 以及形成在所述电极组之间的过渡金属氧化物层，所述过渡金属氧化物层被配置为经历金属 - 绝缘体转变（MIT）以执行读取或写入操作。

48. 发明申请

US20120212238A1 ON-CHIP MEASUREMENT OF AC VARIABILITY IN INDIVIDUAL TRANSISTOR DEVICES 有权
公开(公告)号：US20120212238A1
公开(公告)日：2012-08-23
申请号：US13029214
申请日：2011-02-17
申请人： Karthik Balakrishnan , Keith A. Jenkins
发明人： Karthik Balakrishnan , Keith A. Jenkins
IPC分类号： G01R27/28
CPC分类号： G01R31/2621 , G01R31/2882
摘要： An apparatus for determining alternating current (AC) delay variation of a transistor device under test includes a ring oscillator, the ring oscillator having the transistor device under test configured within a feedback path of the ring oscillator; and circuitry configured to measure a difference between a first signal delay path and a second signal delay path, the first signal delay path being between a gate terminal and a drain terminal of the transistor device under test, and the second signal delay path being between a source terminal and the drain terminal of the transistor device under test.

49. 发明授权

US07780347B2 On chip temperature measuring and monitoring circuit and method 有权
标题翻译：片上温度测量和监测电路及方法
公开(公告)号：US07780347B2
公开(公告)日：2010-08-24
申请号：US12177311
申请日：2008-07-22
申请人： Robert L. Franch , Keith A. Jenkins
发明人： Robert L. Franch , Keith A. Jenkins
IPC分类号： G01K7/01 , H01L17/78
CPC分类号： H01L27/0251 , G01K7/01 , G01K7/015
摘要： A device temperature measurement circuit, an integrated circuit (IC) including a device temperature measurement circuit, a method of characterizing device temperature and a method of monitoring temperature. The circuit includes a constant current source and a clamping device. The clamping device selectively shunts current from the constant current source or allows the current to flow through a PN junction, which may be the body to source/drain junction of a field effect transistor (FET). Voltage measurements are taken directly from the PN junction. Junction temperature is determined from measured junction voltage.
摘要翻译：一种器件温度测量电路，包括器件温度测量电路的集成电路（IC），表征器件温度的方法和监测温度的方法。电路包括恒流源和夹紧装置。钳位装置选择性地从恒流源分流电流，或允许电流流过PN结，其可以是场效应晶体管（FET）的主体到源极/漏极结。电压测量直接来自PN结。结温从测量的结电压确定。

50. 发明授权

US07538652B2 Electrical component tuned by conductive layer deletion 失效
标题翻译：通过导电层删除调整的电气元件
公开(公告)号：US07538652B2
公开(公告)日：2009-05-26
申请号：US11512014
申请日：2006-08-29
申请人： Keith A. Jenkins , Mounir Meghelli
发明人： Keith A. Jenkins , Mounir Meghelli
IPC分类号： H01F5/00
CPC分类号： H01F17/0013 , H01F21/12 , H01F41/045 , H01F2021/125 , H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/3011 , H05K1/165 , H01L2924/00
摘要： Techniques are disclosed for fabricating tunable electrical components in integrated circuits. For example, a method of tuning a value of an electrical component, such as a planar inductor, includes the steps of placing a conductive layer in proximity of the electrical component, and adjusting an amount of material that constitutes the conductive layer such that the value of the electrical component is tuned to a particular value. The adjustment step may be performed so as to select a frequency band with which the inductor is associated or to correct a manufacturing deviation in a frequency with which the inductor is associated.
摘要翻译：公开了用于在集成电路中制造可调电气部件的技术。例如，调整诸如平面电感器的电气部件的值的方法包括以下步骤：将导电层放置在电气部件附近，并且调整构成导电层的材料的量，使得值的电气元件被调谐到特定的值。可以执行调整步骤以便选择与电感器相关联的频带或者校正与电感器相关联的频率中的制造偏差。

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