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41. 发明授权

US07645356B2 Method of processing wafers with resonant heating 失效
标题翻译：用共振加热处理晶片的方法
公开(公告)号：US07645356B2
公开(公告)日：2010-01-12
申请号：US10721657
申请日：2003-11-25
申请人： Siddhartha Panda , Richard S. Wise
发明人： Siddhartha Panda , Richard S. Wise
IPC分类号： C23F1/00
CPC分类号： H01J37/32339 , H01L21/3065 , H01L21/32136
摘要： A method of etching a wafer using resonant infrared energy and a filter to control non-uniformities during plasma etch processing. The filter includes a predetermined array or stacked arrangement of variable transmission regions that mirror the spatial etch distortions caused by the plasma etching process. By spatially attenuating the levels of IR energy that reach the wafer, the filter improves uniformity in the etching process. Filters may be designed to compensate for edge fast etching due to macro-loading, asymmetric pumping in a plasma chamber, and magnetic field cusping.
摘要翻译：使用谐振红外能量蚀刻晶片的方法和用于在等离子体蚀刻处理期间控制不均匀性的滤光器。滤波器包括可反映由等离子体蚀刻工艺引起的空间蚀刻失真的可变透射区域的预定阵列或堆叠布置。通过空间衰减到达晶片的IR能量的水平，滤波器改善了蚀刻工艺中的均匀性。滤波器可以被设计为补偿由于宏载荷，等离子体室中的不对称泵浦和磁场冲击造成的边缘快速蚀刻。

42. 发明授权

US07442618B2 Method to engineer etch profiles in Si substrate for advanced semiconductor devices 有权
标题翻译：在先进半导体器件的Si衬底中设计蚀刻轮廓的方法
公开(公告)号：US07442618B2
公开(公告)日：2008-10-28
申请号：US11182682
申请日：2005-07-16
申请人： Yung Fu Chong , Brian Joseph Greene , Siddhartha Panda , Nivo Rovedo
发明人： Yung Fu Chong , Brian Joseph Greene , Siddhartha Panda , Nivo Rovedo
IPC分类号： H01L21/44
CPC分类号： H01L29/7833 , H01L21/76232 , H01L29/165 , H01L29/6659 , H01L29/66628 , H01L29/7846 , H01L29/7848
摘要： Structures and methods for forming keyhole shaped regions for isolation and/or stressing the substrate are shown. In a first embodiment, we form an inverted keyhole shaped trench in the substrate in the first opening preferably using a two step etch. Next, we fill the inverted keyhole trench with a material that insulates and/or creates stress on the sidewalls of the inverted keyhole trench. In a second embodiment, we form a keyhole stressor region adjacent to the gate and isolation structures. The keyhole stressor region creates stress near the channel region of the FET to improve FET performance. The stressor region can be filled with an insulator or a semiconductor material.
摘要翻译：示出了用于形成用于隔离和/或应力衬底的键孔区域的结构和方法。在第一实施例中，我们在第一开口中的衬底中形成倒置的键孔形沟槽，优选地使用两步蚀刻。接下来，我们使用在倒置的键孔沟槽的侧壁上绝缘和/或产生应力的材料填充倒置的孔眼沟槽。在第二实施例中，我们形成与栅极和隔离结构相邻的键孔应力区域。键孔应力区域在FET的通道区域附近产生应力，以提高FET性能。应力区域可以用绝缘体或半导体材料填充。

43. 发明申请

US20080251817A1 STRESSED FIELD EFFECT TRANSISTORS ON HYBRID ORIENTATION SUBSTRATE 失效
标题翻译：混合定向衬底上的应力场效应晶体管
公开(公告)号：US20080251817A1
公开(公告)日：2008-10-16
申请号：US12144250
申请日：2008-06-23
申请人： Dureseti Chidambarrao , Judson R. Holt , Meikei Ieong , Qiqing C. Ouyang , Siddhartha Panda
发明人： Dureseti Chidambarrao , Judson R. Holt , Meikei Ieong , Qiqing C. Ouyang , Siddhartha Panda
IPC分类号： H01L29/04
CPC分类号： H01L29/045 , H01L21/823807 , H01L29/7843
摘要： A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device located on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel. The present invention also provides methods of fabricating the same. In general terms, the inventive method includes providing a hybrid oriented substrate having at least two planar surfaces of different crystallographic orientation, and forming at least one CMOS device on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel.
摘要翻译：提供了具有改进的载流子迁移率的半导体结构。半导体结构包括具有不同晶体取向的至少两个平坦表面的混合取向半导体衬底，以及位于不同结晶取向的每个平面上的至少一个CMOS器件，其中每个CMOS器件具有应力通道。本发明还提供了制造它们的方法。一般来说，本发明的方法包括提供具有至少两个具有不同晶体取向的平面表面的混合取向衬底，以及在不同结晶取向的每个平面上形成至少一个CMOS器件，其中每个CMOS器件具有受压沟道。

44. 发明授权

US07176481B2 In situ doped embedded sige extension and source/drain for enhanced PFET performance 有权
标题翻译：用于增强PFET性能的原位掺杂嵌入式扩展和源极/漏极
公开(公告)号：US07176481B2
公开(公告)日：2007-02-13
申请号：US10905598
申请日：2005-01-12
申请人： Huajie Chen , Dureseti Chidambarrao , Siddhartha Panda , Sang-Hyun Oh , Henry K. Utomo , Werner A. Rausch
发明人： Huajie Chen , Dureseti Chidambarrao , Siddhartha Panda , Sang-Hyun Oh , Henry K. Utomo , Werner A. Rausch
IPC分类号： H01L29/06
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823814 , H01L29/7848
摘要： Disclosed is an integrated circuit structure and a method of making such a structure that has a substrate and P-type and N-type transistors on the substrate. The N-type transistor extension and source/drain regions comprise dopants implanted into the substrate. The P-type transistor extension and source/drain regions partially include a strained epitaxial silicon germanium, wherein the strained silicon germanium comprises of two layers, with a top layer that is closer to the gate stack than the bottom layer. The strained silicon germanium is in-situ doped and creates longitudinal stress on the channel region.
摘要翻译：公开了一种集成电路结构以及在衬底上具有衬底和P型和N型晶体管的结构的方法。 N型晶体管延伸和源极/漏极区域包括注入到衬底中的掺杂剂。 P型晶体管延伸和源极/漏极区域部分地包括应变外延硅锗，其中应变硅锗包括两层，顶层比底层更靠近栅极堆叠。应变硅锗被原位掺杂并在沟道区域上产生纵向应力。

45. 发明申请

US20060292779A1 STRUCTURE AND METHOD FOR MAKING STRAINED CHANNEL FIELD EFFECT TRANSISTOR USING SACRIFICIAL SPACER 有权
标题翻译：使用真空间隔件制作应变通道场效应晶体管的结构和方法
公开(公告)号：US20060292779A1
公开(公告)日：2006-12-28
申请号：US11463777
申请日：2006-08-10
申请人： Huajie Chen , Dureseti Chidambarrao , Sang-Hyun Oh , Siddhartha Panda , Werner Rausch , Tsutomu Sato , Henry Utomo
发明人： Huajie Chen , Dureseti Chidambarrao , Sang-Hyun Oh , Siddhartha Panda , Werner Rausch , Tsutomu Sato , Henry Utomo
IPC分类号： H01L21/8234
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/28052 , H01L21/28079 , H01L21/7624 , H01L29/1045 , H01L29/165 , H01L29/4933 , H01L29/495 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.
摘要翻译：提供场效应晶体管（“FET”），其包括覆盖衬底的单晶半导体区域的栅极堆叠，设置在所述栅极堆叠的侧壁上的一对第一间隔区，以及基本上由单个晶体半导体合金，其设置在栅叠层的相对侧上。每个半导体合金区域与栅极叠层隔开第一距离。 FET的源极区域和漏极区域至少部分地设置在半导体合金区域的相应半导体合金区域中，使得源极区域和漏极区域之间的距离与栅极叠层间隔开第二距离，第一间隔物，第二距离与第一距离不同。

46. 发明申请

US20060068596A1 Formation of Controlled Sublithographic Structures 失效
标题翻译：控制亚光刻结构的形成
公开(公告)号：US20060068596A1
公开(公告)日：2006-03-30
申请号：US10711683
申请日：2004-09-30
申请人： David Dobuzinsky , Jochen Beintner , Siddhartha Panda
发明人： David Dobuzinsky , Jochen Beintner , Siddhartha Panda
IPC分类号： H01L21/44 , H01L21/302 , H01L21/461
CPC分类号： H01L21/3086 , H01L21/3081 , H01L21/3088 , H01L21/32139 , H01L29/66795 , H01L29/785
摘要： A process for forming sublithographic structures such as fins employs a hardmask protective layer above a hardmask to absorb damage during a dry etching step, thereby preserving symmetry in the hardmask and eliminating a source of defects.
摘要翻译：用于形成诸如翅片之类的亚光刻结构的工艺使用硬掩模上方的硬掩模保护层来在干蚀刻步骤期间吸收损伤，从而保持硬掩模中的对称性并消除缺陷源。

47. 发明授权

US06743727B2 Method of etching high aspect ratio openings 失效
标题翻译：蚀刻高纵横比开口的方法
公开(公告)号：US06743727B2
公开(公告)日：2004-06-01
申请号：US09874109
申请日：2001-06-05
申请人： Gangadhara S. Mathad , Siddhartha Panda , Rajiv M. Ranade
发明人： Gangadhara S. Mathad , Siddhartha Panda , Rajiv M. Ranade
IPC分类号： H01L2100
CPC分类号： H01L21/30655 , H01L21/3065 , H01L21/3081 , H01L21/76224
摘要： A method of etching a deep, high aspect ratio opening in a silicon substrate includes etching the substrate with a first plasma formed using a first gaseous mixture including a bromine containing gas, an oxygen containing gas and a first fluorine containing gas. The etching process with the first gaseous mixture produces a sidewall passivating deposit, which builds up near the opening entrance. To reduce this buildup, and to increase the average etching rate, the sidewall passivating deposit is periodically thinned by forming a second plasma using a mixture containing silane and a second fluorine containing gas. The substrate remains in the same plasma reactor chamber during the entire process and the plasma is continuously maintained during the thinning step. Holes of a depth greater than 40 times the width may be produced using repeated cycles of etching and thinning.
摘要翻译：在硅衬底中蚀刻深，高纵横比开口的方法包括使用包含含溴气体，含氧气体和第一含氟气体的第一气体混合物形成的第一等离子体蚀刻衬底。用第一气体混合物的蚀刻工艺产生侧壁钝化沉积物，其沉积在开口入口附近。为了减少这种积累并且为了提高平均蚀刻速率，通过使用含有硅烷和第二含氟气体的混合物形成第二等离子体来周期性地减薄侧壁钝化沉积物。在整个工艺期间，衬底保持在相同的等离子体反应器室中，并且在稀化步骤期间连续维持等离子体。可以使用重复的蚀刻和变薄循环来产生大于40倍宽度的孔。

48. 发明授权

US06709917B2 Method to increase the etch rate and depth in high aspect ratio structure 失效
标题翻译：在高纵横比结构中增加蚀刻速率和深度的方法
公开(公告)号：US06709917B2
公开(公告)日：2004-03-23
申请号：US10145230
申请日：2002-05-13
申请人： Siddhartha Panda , Rajiv M. Ranade , Gangadhara S. Mathad
发明人： Siddhartha Panda , Rajiv M. Ranade , Gangadhara S. Mathad
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L21/3065
摘要： A method of fabricating a high aspect ratio deep trench in a semiconductor substrate comprising reducing the formation of a passivation film during the etching of the trench by including a first step of contacting the substrate in which the deep trench is to be formed with a fluorine poor or low concentration of a fluorine gas in the plasma of etchant gases for etching the high aspect ratio deep trench, followed by a second step of increasing the concentration of the fluorine containing gas to create a fluorine-rich plasma while lowering the chamber pressure of the reactor and RF power. Preferably, the second step is introduced periodically during the etching of a deep trench in an alternating manner.
摘要翻译：一种在半导体衬底中制造高深宽比深沟槽的方法，包括在蚀刻蚀刻期间减少钝化膜的形成，包括使要形成深沟槽的衬底与氟差的接触的第一步骤或低浓度的蚀刻剂气体等离子体中的氟气，用于蚀刻高纵横比深沟槽，随后是增加含氟气体的浓度以产生富氟等离子体同时降低室内压力的第二步骤电抗器和RF功率。优选地，在以交替方式蚀刻深沟槽期间周期性地引入第二步骤。

49. 发明授权

US08783948B2 Flexible temperature sensor and sensor array 有权
标题翻译：灵活的温度传感器和传感器阵列
公开(公告)号：US08783948B2
公开(公告)日：2014-07-22
申请号：US13142843
申请日：2010-11-09
申请人： Siddhartha Panda , Hakeem Abrar Ahmed
发明人： Siddhartha Panda , Hakeem Abrar Ahmed
IPC分类号： G01K7/00
CPC分类号： G01K7/00 , G01K1/143 , G01K7/18 , Y10T29/49085 , Y10T29/49155
摘要： Techniques described herein generally relate to methods of manufacturing devices and systems including devices including a substrate with a surface, a conductive polymer film arranged on the surface of the substrate, wherein the conductive polymer film has one or more temperature reactive characteristics, and a pair of electrodes coupled to the polymer film, wherein the pair of electrodes are configured to communicate electrical signals to the conductive polymer film effective to measure the one or more temperature reactive characteristics. The conductive polymer film may be arranged on the surface of the substrate such that a thickness and dopant ratio of the conductive polymer film on the substrate is configurable.
摘要翻译：本文描述的技术通常涉及制造装置和系统的方法，包括包括具有表面的基板，布置在基板的表面上的导电聚合物膜的装置，其中导电聚合物膜具有一个或多个温度反应特性，以及一对耦合到聚合物膜的电极，其中该对电极被配置为将电信号传导到有效测量一个或多个温度反应特性的导电聚合物膜。导电聚合物膜可以布置在衬底的表面上，使得衬底上的导电聚合物膜的厚度和掺杂剂比例是可配置的。

50. 发明授权

US07977185B2 Method and apparatus for post silicide spacer removal 有权
标题翻译：后硅化物间隔物去除的方法和装置
公开(公告)号：US07977185B2
公开(公告)日：2011-07-12
申请号：US11164417
申请日：2005-11-22
申请人： Brian J. Greene , Chung Woh Lai , Yong Meng Lee , Wenhe Lin , Siddhartha Panda , Kern Rim , Young Way Teh
发明人： Brian J. Greene , Chung Woh Lai , Yong Meng Lee , Wenhe Lin , Siddhartha Panda , Kern Rim , Young Way Teh
IPC分类号： H01L21/33
CPC分类号： H01L21/31116 , H01L21/31144 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： A method (and apparatus) of post silicide spacer removal includes preventing damage to the silicide spacer through the use of at least one of an oxide layer and a nitride layer.
摘要翻译：后硅化物间隔物去除的方法（和装置）包括通过使用氧化物层和氮化物层中的至少一种来防止对硅化物间隔物的损害。

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