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1. 发明授权

US07645356B2 Method of processing wafers with resonant heating 失效
标题翻译：用共振加热处理晶片的方法
公开(公告)号：US07645356B2
公开(公告)日：2010-01-12
申请号：US10721657
申请日：2003-11-25
申请人： Siddhartha Panda , Richard S. Wise
发明人： Siddhartha Panda , Richard S. Wise
IPC分类号： C23F1/00
CPC分类号： H01J37/32339 , H01L21/3065 , H01L21/32136
摘要： A method of etching a wafer using resonant infrared energy and a filter to control non-uniformities during plasma etch processing. The filter includes a predetermined array or stacked arrangement of variable transmission regions that mirror the spatial etch distortions caused by the plasma etching process. By spatially attenuating the levels of IR energy that reach the wafer, the filter improves uniformity in the etching process. Filters may be designed to compensate for edge fast etching due to macro-loading, asymmetric pumping in a plasma chamber, and magnetic field cusping.
摘要翻译：使用谐振红外能量蚀刻晶片的方法和用于在等离子体蚀刻处理期间控制不均匀性的滤光器。滤波器包括可反映由等离子体蚀刻工艺引起的空间蚀刻失真的可变透射区域的预定阵列或堆叠布置。通过空间衰减到达晶片的IR能量的水平，滤波器改善了蚀刻工艺中的均匀性。滤波器可以被设计为补偿由于宏载荷，等离子体室中的不对称泵浦和磁场冲击造成的边缘快速蚀刻。

2. 发明授权

US07256399B2 Non-destructive in-situ elemental profiling 失效
标题翻译：非破坏性原位元素分析
公开(公告)号：US07256399B2
公开(公告)日：2007-08-14
申请号：US10907591
申请日：2005-04-07
申请人： Siddhartha Panda , Michael R. Sievers , Richard S. Wise
发明人： Siddhartha Panda , Michael R. Sievers , Richard S. Wise
IPC分类号： G01N23/227
CPC分类号： G01N23/2273
摘要： A non-destructive in-situ elemental profiling of a layer in a set of layers method and system are disclosed. In one embodiment, a first emission of a plurality of photoelectrons is caused from the layer to be elementally profiled. An elemental profile of the layer is determined based on the emission. In another embodiment, a second emission of a plurality of photoelectrons is also received from the layer, and an elemental profile is determined by comparison of the resulting signals. A process that is altering the layer can then be controlled “on-the-fly” to obtain a desired material composition. Since the method can be employed in-situ and is non-destructive, it reduces turn around time and lowers wafer consumption. The invention also records the composition of all processed wafers, hence, removing the conventional statistical sampling problem.
摘要翻译：公开了一组层中的层的非破坏性原位元素分析方法和系统。在一个实施例中，多个光电子的第一次发射是从该层进行元素分析。基于发射确定层的元素分布。在另一个实施例中，也从该层接收多个光电子的第二次发射，并且通过比较所得到的信号来确定元素分布。然后可以“即时”控制改变层的方法以获得所需的材料组成。由于该方法可以原位使用并且是非破坏性的，所以可以减少周转时间并降低晶片消耗。本发明还记录了所有加工晶片的组成，因此，去除了常规统计抽样问题。

3. 发明申请

US20080118955A1 METHOD FOR PRECISE TEMPERATURE CYCLING IN CHEMICAL / BIOCHEMICAL PROCESSES 审中-公开
标题翻译：化学/生化过程中精确循环的方法
公开(公告)号：US20080118955A1
公开(公告)日：2008-05-22
申请号：US11858280
申请日：2007-09-20
申请人： Siddhartha Panda , Richard S. Wise
发明人： Siddhartha Panda , Richard S. Wise
IPC分类号： C12P19/34 , B01J19/12
CPC分类号： C12Q1/686 , B01L7/52 , B01L7/5255 , B01L2300/1872 , C12Q2523/313
摘要： A method for implementing a temperature cycling operation for a biochemical sample to be reacted includes applying an infrared (IR) heating source to the biochemical sample to be reacted at a first infrared wavelength selected so as to generate a first desired temperature for a first duration and produce a first desired reaction within the biochemical sample; following the first desired reaction, applying the infrared (IR) heating source to the biochemical sample at a second infrared wavelength selected so as to generate a second desired temperature for a second duration and produce a second desired reaction within the biochemical sample; and wherein the first and second wavelengths generated by the IR source are selected to be coincident with corresponding absorptive wavelengths of the biochemical sample so as to heat the biochemical sample without directly heating a fluid medium containing the biochemical sample.
摘要翻译：用于实施待反应的生物化学样品的温度循环操作的方法包括将红外（IR）加热源施加到生物化学样品以在被选择的第一红外波长处反应，以便产生第一期望的第一期望温度，以及在生物化学样品中产生第一个所需的反应; 在第一期望的反应之后，以选择的第二红外波长将红外（IR）加热源施加到生物化学样品，以产生第二期望的第二期望温度，并在生化试样中产生第二所需反应; 并且其中由IR源产生的第一和第二波长被选择为与生物化学样品的相应吸收波长一致，以便加热生化样品而不直接加热含有生物化学样品的流体介质。

4. 发明申请

US20090104776A1 METHODS FOR FORMING NESTED AND ISOLATED LINES IN SEMICONDUCTOR DEVICES 审中-公开
标题翻译：在半导体器件中形成嵌套和隔离线的方法
公开(公告)号：US20090104776A1
公开(公告)日：2009-04-23
申请号：US11874392
申请日：2007-10-18
申请人： David M. Dobuzinsky , Johnathan E. Faltermeier , Naoyoshi Kusaba , Joyce C. Liu , Munir D. Naeem , Siddhartha Panda , Richard S. Wise , Hongwen Yan
发明人： David M. Dobuzinsky , Johnathan E. Faltermeier , Naoyoshi Kusaba , Joyce C. Liu , Munir D. Naeem , Siddhartha Panda , Richard S. Wise , Hongwen Yan
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , H01L21/0337 , H01L21/0338 , H01L21/32137 , H01L21/32139
摘要： A method for forming lines for semiconductor devices including, depositing a shallow trench isolation (STI) film stack on a silicon substrate, depositing a layer of polysilicon on the STI film stack, depositing a layer of antireflective coating on the layer of polysilicon, developing a phototoresist on the antireflective coating, wherein the photoresist defines a line, etching the layer of antireflective coating and the layer of polysilicon using RIE with a low bias power, removing the photoresist, removing the layer of antireflective coating, etching the STI film stack to form the line, wherein the layer of polysilicon further defines the line.
摘要翻译：一种用于形成用于半导体器件的线的方法，包括：在硅衬底上沉积浅沟槽隔离（STI）膜堆叠，在所述STI膜堆叠上沉积多晶硅层，在所述多晶硅层上沉积一层抗反射涂层，在抗反射涂层上光致抗蚀剂，其中光致抗蚀剂限定线，使用具有低偏压功率的RIE蚀刻抗反射涂层和多晶硅层，去除光致抗蚀剂，去除抗反射涂层，蚀刻STI膜叠层以形成所述线，其中所述多晶硅层进一步限定所述线。

5. 发明授权

US07186660B2 Silicon precursors for deep trench silicon etch processes 失效
标题翻译：用于深沟槽硅蚀刻工艺的硅前体
公开(公告)号：US07186660B2
公开(公告)日：2007-03-06
申请号：US10338964
申请日：2003-01-08
申请人： Siddhartha Panda , Richard S. Wise
发明人： Siddhartha Panda , Richard S. Wise
IPC分类号： H01L21/302
CPC分类号： H01L21/3065 , H01L27/10861
摘要： The present invention relates to etch chemistry and methods for the etching of silicon substrates. The method is particularly useful for deep trench etching of silicon substrates and produces a trench having a high aspect ratio. In this type of deep trench etching, control of the profile of the trench is addressed by the etch chemistry disclosed herein. The etchant described in the present invention comprises silicon and a halogen component, and may be gaseous, liquid or solid. The etchant disclosed is also substantially free of hydrogen and carbon.
摘要翻译：本发明涉及用于蚀刻硅衬底的蚀刻化学和方法。该方法对于硅衬底的深沟槽蚀刻特别有用，并且产生具有高纵横比的沟槽。在这种类型的深沟槽蚀刻中，通过本文公开的蚀刻化学处理对沟槽轮廓的控制。本发明中描述的蚀刻剂包括硅和卤素组分，并且可以是气态，液态或固体。所公开的蚀刻剂也基本上不含氢和碳。

6. 发明申请

US20130200471A1 ALIGNMENT TOLERANT SEMICONDUCTOR CONTACT AND METHOD 有权
标题翻译：对准耐磨半导体接触和方法
公开(公告)号：US20130200471A1
公开(公告)日：2013-08-08
申请号：US13364976
申请日：2012-02-02
申请人： André P. Labonté , Richard S. Wise
发明人： André P. Labonté , Richard S. Wise
IPC分类号： H01L29/78 , H01L21/768
CPC分类号： H01L21/28247 , H01L21/76814 , H01L21/76888 , H01L21/76897 , H01L29/66545
摘要： An alignment tolerant electrical contact is formed by providing a substrate on which is a first electrically conductive region (e.g., a MOSFET gate) having an upper surface, the first electrically conductive region being laterally bounded by a first dielectric region, applying a mask having an opening extending partly over a contact region (e.g., for the MOSFET source or drain) on the substrate and over a part of the upper surface, forming a passage through the first dielectric region extending to the contact region and the part of the upper surface, thereby exposing the contact region and the part of the upper surface, converting the part of the upper surface to a second dielectric region and filling the opening with a conductor making electrical contact with the contact region but electrically insulated from the electrically conductive region by the second dielectric region.
摘要翻译：通过提供其上具有上表面的第一导电区域（例如，MOSFET栅极）的衬底来形成对准容限的电接触，所述第一导电区域被第一介电区域横向界定，施加具有部分地覆盖在衬底上并在上表面的一部分上的接触区域（例如，用于MOSFET源极或漏极）上的开口，形成通过延伸到接触区域和上表面的部分的第一介电区域的通道，从而暴露接触区域和上表面的一部分，将上表面的一部分转换成第二电介质区域，并且用与接触区域电接触但与导电区域电绝缘的导体填充开口电介质区域。

7. 发明授权

US08492280B1 Method for simultaneously forming features of different depths in a semiconductor substrate 失效
标题翻译：同时形成半导体衬底中不同深度的特征的方法
公开(公告)号：US08492280B1
公开(公告)日：2013-07-23
申请号：US13465050
申请日：2012-05-07
申请人： Habib Hichri , Xi Li , Richard S. Wise
发明人： Habib Hichri , Xi Li , Richard S. Wise
IPC分类号： H01L21/311
CPC分类号： H01L21/3065 , H01L21/76229 , H01L21/84 , H01L27/1087 , H01L29/66181
摘要： Embodiments of the invention may include first providing a stack of layers including a semiconductor substrate, a buried oxide layer on the semiconductor substrate, a semiconductor-on-insulator layer on the buried-oxide layer, a nitride layer on the semiconductor-on-insulator layer, and a silicon oxide layer on the nitride layer. A first opening and second opening with a smaller cross-sectional area than the first opening are then formed in the silicon oxide layer, the nitride layer, the semiconductor-on-insulator layer, and the buried-oxide layer. The first opening and the second opening are then etched with a first etching gas. The first opening and the second opening are then etched with a second etching gas, which includes the first etching gas and a halogenated silicon compound, for example, silicon tetrafluoride or silicon tetrachloride. In one embodiment, the first etching gas includes hydrogen bromide, nitrogen trifluoride, and oxygen.
摘要翻译：本发明的实施例可以包括首先提供包括半导体衬底，半导体衬底上的掩埋氧化物层，掩埋氧化物层上的绝缘体上半导体层，绝缘体上半导体上的氮化物层层和氮化物层上的氧化硅层。然后在氧化硅层，氮化物层，绝缘体上半导体层和掩埋氧化物层上形成具有比第一开口更小的横截面面积的第一开口和第二开口。然后用第一蚀刻气体蚀刻第一开口和第二开口。然后用第二蚀刻气体蚀刻第一开口和第二开口，第二蚀刻气体包括第一蚀刻气体和卤化硅化合物，例如四氟化硅或四氯化硅。在一个实施方案中，第一蚀刻气体包括溴化氢，三氟化氮和氧。

8. 发明申请

US20120139061A1 Self-Aligned Contact For Replacement Gate Devices 有权
标题翻译：用于替代门装置的自对准触点
公开(公告)号：US20120139061A1
公开(公告)日：2012-06-07
申请号：US12958607
申请日：2010-12-02
申请人： Ravikumar Ramachandran , Ying Li , Richard S. Wise
发明人： Ravikumar Ramachandran , Ying Li , Richard S. Wise
IPC分类号： H01L29/772 , H01L21/283
CPC分类号： H01L29/78 , H01L21/76895 , H01L21/76897 , H01L21/823842 , H01L21/823871 , H01L29/49 , H01L29/51 , H01L29/66545 , H01L29/66606 , H01L29/7833 , H01L29/7843
摘要： A conductive top surface of a replacement gate stack is recessed relative to a top surface of a planarization dielectric layer by at least one etch. A dielectric capping layer is deposited over the planarization dielectric layer and the top surface of the replacement gate stack so that the top surface of a portion of the dielectric capping layer over the replacement gate stack is vertically recessed relative to another portion of the dielectric layer above the planarization dielectric layer. The vertical offset of the dielectric capping layer can be employed in conjunction with selective via etch processes to form a self-aligned contact structure.
摘要翻译：替代栅极堆叠的导电顶表面通过至少一个蚀刻相对于平坦化介电层的顶表面凹陷。介电覆盖层沉积在平坦化电介质层和替代栅极堆叠的顶表面上，使得替代栅极堆叠上的介电顶盖层的一部分的顶表面相对于上述电介质层的另一部分垂直凹陷平坦化介电层。电介质覆盖层的垂直偏移可以与选择性通孔蚀刻工艺结合使用以形成自对准接触结构。

9. 发明授权

US07943457B2 Dual metal and dual dielectric integration for metal high-k FETs 有权
标题翻译：金属高k FET的双金属和双电介质集成
公开(公告)号：US07943457B2
公开(公告)日：2011-05-17
申请号：US12423236
申请日：2009-04-14
申请人： Michael P. Chudzik , Wiliam K. Henson , Rashmi Jha , Yue Liang , Ravikumar Ramachandran , Richard S. Wise
发明人： Michael P. Chudzik , Wiliam K. Henson , Rashmi Jha , Yue Liang , Ravikumar Ramachandran , Richard S. Wise
IPC分类号： H01L21/336
CPC分类号： H01L29/517 , H01L21/28185 , H01L21/823842 , H01L21/823857 , H01L29/49 , H01L29/7833
摘要： The present invention, in one embodiment, provides a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity type region; forming a gate stack including a gate dielectric atop the first conductivity type region and the second conductivity type region of the substrate and a first metal gate conductor overlying the high-k gate dielectric; removing a portion of the first metal gate conductor that is present in the first conductivity type region to expose the gate dielectric present in the first conductivity type region; applying a nitrogen based plasma to the substrate, wherein the nitrogen based plasma nitrides the gate dielectric that is present in the first conductivity type region and nitrides the first metal gate conductor that is present in the second conductivity type region; and forming a second metal gate conductor overlying at least the gate dielectric that is present in the first conductivity type region.
摘要翻译：在一个实施例中，本发明提供一种形成半导体器件的方法，该半导体器件包括提供包括第一导电类型区域和第二导电类型区域的衬底; 在所述基板的第一导电类型区域和所述第二导电类型区域之上形成包括栅极电介质的栅极堆叠和覆盖所述高k栅极电介质的第一金属栅极导体; 去除存在于第一导电类型区域中的第一金属栅极导体的一部分以暴露存在于第一导电类型区域中的栅极电介质; 将氮基等离子体施加到所述基板，其中所述氮基等离子体氮化存在于所述第一导电类型区域中的所述栅极电介质，并且氮化所述第二导电类型区域中存在的所述第一金属栅极导体; 以及形成覆盖存在于第一导电类型区域中的至少栅极电介质的第二金属栅极导体。

10. 发明申请

US20110104426A1 EDGE PROTECTION SEAL FOR BONDED SUBSTRATES 失效
标题翻译：贴边基板的边缘保护密封
公开(公告)号：US20110104426A1
公开(公告)日：2011-05-05
申请号：US12608363
申请日：2009-10-29
申请人： Mukta G. Farooq , Emily Kinser , Richard S. Wise , Hakeem B.S. Akinmade-Yusuff
发明人： Mukta G. Farooq , Emily Kinser , Richard S. Wise , Hakeem B.S. Akinmade-Yusuff
IPC分类号： B32B1/04 , B32B38/00
CPC分类号： H01L21/02263 , H01L21/187 , H01L21/76898 , H01L25/074 , H01L25/50 , H01L2924/0002 , H01L2924/00
摘要： A dielectric material layer is deposited on exposed surfaces of a bonded structure that includes a first substrate and a second substrate. The dielectric material layer is formed on an exposed planar surface of a second substrate and the entirety of peripheral sidewalls of the first and second substrates. The dielectric material layer can be formed by chemical vapor deposition, atomic layer deposition, or plasma induced deposition. Further, the dielectric material layer seals the entire periphery of the interface between the first and second substrates. If a planar portion of the dielectric material layer can be removed by planarization to facilitate thinning of the bonded structure, the remaining portion of the dielectric material layer can form a dielectric ring.
摘要翻译：介电材料层沉积在包括第一基板和第二基板的接合结构的暴露表面上。介电材料层形成在第二基板的暴露的平坦表面和第一和第二基板的整个周边侧壁上。介电材料层可以通过化学气相沉积，原子层沉积或等离子体诱导沉积形成。此外，介电材料层密封第一和第二基板之间的界面的整个周边。如果可以通过平坦化去除电介质材料层的平面部分以便于键合结构的薄化，则介电材料层的剩余部分可以形成介电环。

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