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41. 发明申请

US20080123432A1 Flash memory device and method of reading data from flash memory device 失效
标题翻译：闪存设备和从闪存设备读取数据的方法
公开(公告)号：US20080123432A1
公开(公告)日：2008-05-29
申请号：US11606932
申请日：2006-12-01
申请人： Ho-jung Kim
发明人： Ho-jung Kim
IPC分类号： G11C16/06
CPC分类号： G11C16/26
摘要： A method of reading data from a flash memory device that includes a multiple block memory cell array, each block having a cell string connected to a bit line and comprising a string select transistor connected to a string select line, a memory cell connected to a wordline and a global select transistor connected to a global select line and having a source connected to a common source line. The method includes pre-charging the bit lines to a first voltage in a standby state, discharging a selected bit line connected to a selected memory cell to a second voltage in response to a read command, and reading data stored in the selected memory cell in response to the read command.
摘要翻译：一种从包括多块存储单元阵列的闪速存储器件读取数据的方法，每个块具有连接到位线的单元串，并且包括连接到串选择线的串选择晶体管，连接到字线的存储单元以及连接到全局选择线并具有连接到公共源极线的源极的全局选择晶体管。该方法包括将待机状态下的位线预充电到第一电压，响应于读取命令将连接到所选择的存储器单元的选定位线放电到第二电压，以及读取存储在所选存储单元中的数据对读命令的响应。

42. 发明申请

US20070008806A1 Word line decoder suitable for low operating voltage of flash memory device 有权
标题翻译：字线解码器适用于闪存器件的低工作电压
公开(公告)号：US20070008806A1
公开(公告)日：2007-01-11
申请号：US11481363
申请日：2006-07-05
申请人： Ho-jung Kim
发明人： Ho-jung Kim
IPC分类号： G11C8/00
CPC分类号： G11C16/08 , G11C8/08 , G11C8/10
摘要： Provided is a word line decoder suitable to a low operating voltage of a flash memory device. The word line decoder generates a block word line driving signal of a high voltage in response to a block selection signal. The word line decoder includes a first inverter receiving the block selection signal, a second inverter receiving an output of the first inverter, and first and second serially connected transistors receiving an output of the second inverter and outputting the block word line driving signal. The gates of the first and second transistors are connected to a supply voltage terminal. The word line decoder includes a third transistor having a source connected to a high voltage terminal and a gate connected to a line transmitting the block word line driving signal, a fourth transistor connected between the drain of the third transistor and the block word line driving signal line, a fifth transistor connected between the drain of the third transistor and the gate of the fourth transistor and having a gate connected to the block word line driving signal line, and a sixth transistor connected between the output of the first inverter and the gate of the second transistor and having a gate connected to the supply voltage terminal.
摘要翻译：提供了适用于闪存器件的低工作电压的字线解码器。字线解码器响应于块选择信号产生高电压的块字线驱动信号。字线解码器包括接收块选择信号的第一反相器，接收第一反相器的输出的第二反相器和接收第二反相器的输出的第一和第二串联连接的晶体管，并输出块字线驱动信号。第一和第二晶体管的栅极连接到电源电压端子。字线解码器包括具有连接到高电压端子的源极和连接到发送块字线驱动信号的线路的栅极的第三晶体管，连接在第三晶体管的漏极和块字线驱动信号之间的第四晶体管连接在第三晶体管的漏极和第四晶体管的栅极之间并且具有连接到块字线驱动信号线的栅极的第五晶体管，以及连接在第一反相器的输出和第一反相器的栅极之间的第六晶体管第二晶体管并且具有连接到电源电压端子的栅极。

43. 发明申请

US20110286275A1 Stacked Memory Devices And Method Of Manufacturing The Same 有权
标题翻译：堆叠式存储器件及其制造方法
公开(公告)号：US20110286275A1
公开(公告)日：2011-11-24
申请号：US13112443
申请日：2011-05-20
申请人： Sang-hun Jeon , Ho-jung Kim
发明人： Sang-hun Jeon , Ho-jung Kim
IPC分类号： G11C16/04 , H01L21/28
CPC分类号： H01L27/11551 , G11C16/0483 , H01L27/11519 , H01L27/11526 , H01L27/11556 , H01L27/11565 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L29/7889 , H01L29/7926
摘要： A stacked memory device may include at least one memory unit and at least one peripheral circuit unit arranged either above or below the at least one memory unit. The at least one memory unit may include a memory string array, a plurality of bit lines, and a plurality of string selection pads. The memory string may include a plurality of memory strings arranged in a matrix and each of the memory strings may include a plurality of memory cells and a string selection device arranged perpendicular to a substrate. The plurality of bit lines may extend in a first direction and may be connected to ends of the plurality of memory strings. The plurality of string selection pads may be arrayed in a single line along the first direction and may be connected to the string selection devices included in the plurality of memory strings.
摘要翻译：堆叠式存储器件可以包括至少一个存储器单元和布置在至少一个存储器单元的上方或下方的至少一个外围电路单元。所述至少一个存储器单元可以包括存储器串阵列，多个位线以及多个串选择焊盘。存储器串可以包括排列成矩阵的多个存储器串，并且每个存储器串可以包括多个存储单元和垂直于衬底布置的串选择装置。多个位线可以在第一方向上延伸并且可以连接到多个存储器串的端部。多个串选择板可以沿着第一方向排列成单行，并且可以连接到包括在多个存储器串中的串选择装置。

44. 发明申请

US20110273221A1 Driving circuits, power devices and electronic devices including the same 有权
标题翻译：驱动电路，功率器件和包括它们的电子器件
公开(公告)号：US20110273221A1
公开(公告)日：2011-11-10
申请号：US13064264
申请日：2011-03-15
申请人： Ho-jung Kim , Jae-kwang Shin , Jae-Joon Oh , Jong-seob Kim , Hyuk-soon Choi , In-jun Hwang , Ki-ha Hong
发明人： Ho-jung Kim , Jae-kwang Shin , Jae-Joon Oh , Jong-seob Kim , Hyuk-soon Choi , In-jun Hwang , Ki-ha Hong
IPC分类号： H03K17/284 , H03K17/687
CPC分类号： H03K17/163 , H03K17/284
摘要： A power device includes a switching device having a control terminal and an output terminal; and a driving circuit configured to provide a driving voltage to the control terminal such that a voltage between the control terminal and the output terminal remains less than or equal to a critical voltage. A rise time required for the driving voltage to reach a target level is determined according to current-voltage characteristics of the switching device. And, when the voltage between the control terminal and the output terminal exceeds the critical voltage, leakage current is generated between the control terminal and the output terminal.
摘要翻译：功率器件包括具有控制端子和输出端子的开关器件; 以及驱动电路，被配置为向控制端子提供驱动电压，使得控制端子和输出端子之间的电压保持小于或等于临界电压。根据开关装置的电流 - 电压特性来确定驱动电压达到目标电平所需的上升时间。而且，当控制端子与输出端子之间的电压超过临界电压时，控制端子与输出端子之间产生漏电流。

45. 发明申请

US20080112227A1 Non-volatile memory device and programming, reading and erasing methods thereof 失效
标题翻译：非易失性存储器件及其编程，读取和擦除方法
公开(公告)号：US20080112227A1
公开(公告)日：2008-05-15
申请号：US11606246
申请日：2006-11-30
申请人： Ho-jung Kim
发明人： Ho-jung Kim
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/28
摘要： A non-volatile memory device includes a memory cell array and a voltage control unit. The memory cell array includes a plurality of memory blocks each including a plurality of cell strings. Each of the cell strings includes a first selection transistor, a second selection transistor, and at least one memory cell transistor serially connected between the first selection transistor and the second selection transistor. The voltage control unit provides first selection line voltages and word line voltages to first selection lines connected to the first selection transistors and word lines connected to the memory cell transistors, respectively, in response to a plurality of block selection signals corresponding to the plurality of memory blocks, and provides a second selection line voltage directly to second selection lines connected to the second selection transistors independently of the block selection signals
摘要翻译：非易失性存储器件包括存储单元阵列和电压控制单元。存储单元阵列包括多个存储块，每个存储块包括多个单元串。每个单元串包括第一选择晶体管，第二选择晶体管和串联连接在第一选择晶体管和第二选择晶体管之间的至少一个存储单元晶体管。电压控制单元响应于对应于多个存储器的多个块选择信号，分别向连接到第一选择晶体管的第一选择线和连接到存储单元晶体管的字线提供第一选择线电压和字线电压并且独立于块选择信号，直接向连接到第二选择晶体管的第二选择线提供第二选择线电压

46. 发明申请

US20080101128A1 Nonvolatile memory device and method of reading information from the same 失效
标题翻译：非易失性存储器件和从其读取信息的方法
公开(公告)号：US20080101128A1
公开(公告)日：2008-05-01
申请号：US11605225
申请日：2006-11-29
申请人： Ho-jung Kim
发明人： Ho-jung Kim
IPC分类号： G11C11/34
CPC分类号： G11C16/26 , G11C16/24
摘要： A nonvolatile memory device includes a memory cell array and a voltage controller. The memory cell array includes a plurality of memory blocks each including a plurality of cell strings, where each of the cell strings includes a first selection transistor, a second selection transistor, and at least one memory cell transistor connected in series between the first and second selection transistors. The voltage controller applies a first selection voltage to first selection lines connected to the first selection transistors, a second selection voltage to second selection lines connected to the second selection transistors, and a word line voltage to word lines connected to the memory cell transistors, in response to a plurality of block selection signals corresponding to the memory blocks. The voltage controller precharges the second selection lines to a precharge voltage by applying the second selection line voltage to the second selection lines in a standby state, where the second selection line voltage is equal to the precharge voltage.
摘要翻译：非易失性存储器件包括存储单元阵列和电压控制器。存储单元阵列包括多个存储块，每个存储块包括多个单元串，其中每个单元串包括第一选择晶体管，第二选择晶体管和串联连接在第一和第二单元串之间的至少一个存储单元晶体管选择晶体管。电压控制器对连接到第一选择晶体管的第一选择线，连接到第二选择晶体管的第二选择线的第二选择电压和连接到存储单元晶体管的字线的字线电压施加第一选择电压，响应于对应于存储块的多个块选择信号。电压控制器通过在第二选择线电压等于预充电电压的待机状态下将第二选择线电压施加到第二选择线，将第二选择线预充电到预充电电压。

47. 发明申请

US20070285186A1 Oscillator reducing clock signal variations due to variations in voltage or temperature 有权
标题翻译：振荡器减少由于电压或温度变化引起的时钟信号变化
公开(公告)号：US20070285186A1
公开(公告)日：2007-12-13
申请号：US11790012
申请日：2007-04-23
申请人： Ho-jung Kim
发明人： Ho-jung Kim
IPC分类号： H03L1/00
CPC分类号： H03L1/00 , H03K3/011 , H03K3/354
摘要： Provided is an oscillator including a logic signal generator and a clock generator. The logic signal generator generates a first logic signal and a second logic signal that have the same period but have different logic level transition timing. The clock generator generates a clock signal in response to the first logic signal and the second logic signal. The oscillator compensates for an amount of variation of a reference current using a compensation current, thereby maintaining a constant period of the clock signal.
摘要翻译：提供了包括逻辑信号发生器和时钟发生器的振荡器。逻辑信号发生器产生具有相同周期但具有不同逻辑电平转换时序的第一逻辑信号和第二逻辑信号。时钟发生器响应于第一逻辑信号和第二逻辑信号产生时钟信号。振荡器使用补偿电流来补偿参考电流的变化量，从而保持时钟信号的恒定周期。

48. 发明授权

US09059808B2 Microprocessor chip, data center, and computing system 有权
标题翻译：微处理器芯片，数据中心和计算系统
公开(公告)号：US09059808B2
公开(公告)日：2015-06-16
申请号：US13611839
申请日：2012-09-12
申请人： Ho-jung Kim , Young-soo Park
发明人： Ho-jung Kim , Young-soo Park
IPC分类号： H04B10/00 , H04B10/80
CPC分类号： H04B10/801
摘要： A microprocessor chip includes a plurality of processors; at least one first optical input/output unit configured to receive optical signals from an external device and transmit optical signals to the external device; and an optical system bus that is connected between the plurality of processors and the at least one first optical input/output unit.
摘要翻译：微处理器芯片包括多个处理器; 至少一个第一光输入/输出单元，被配置为从外部设备接收光信号并将光信号传输到所述外部设备; 以及连接在所述多个处理器与所述至少一个第一光学输入/输出单元之间的光学系统总线。

49. 发明授权

US08611121B2 Stacked memory devices 有权
标题翻译：堆叠式存储器件
公开(公告)号：US08611121B2
公开(公告)日：2013-12-17
申请号：US12662785
申请日：2010-05-04
申请人： Seung-eon Ahn , Ho-jung Kim , Chul-woo Park , Sang-beom Kang , Hyun-ho Choi
发明人： Seung-eon Ahn , Ho-jung Kim , Chul-woo Park , Sang-beom Kang , Hyun-ho Choi
IPC分类号： G11C5/02
CPC分类号： G11C5/025 , G11C5/02 , G11C8/10 , G11C13/0004 , G11C13/0023 , G11C13/0028 , G11C2213/71 , G11C2213/72
摘要： A stacked memory device may include a substrate, a plurality of memory groups sequentially stacked on the substrate, each memory group including at least one memory layer, a plurality of X-decoder layers, at least one of the plurality of X-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups, and a plurality of Y-decoder layers disposed alternately with the plurality of X-decoder layers, at least one of the plurality of Y-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups.
摘要翻译：层叠的存储器件可以包括衬底，顺序地堆叠在衬底上的多个存储器组，每个存储器组包括至少一个存储器层，多个X译码器层，所述多个X译码器层中的至少一个是设置在所述多个存储器组中的每个相邻的两个存储器组之间，以及与所述多个X解码器层交替布置的多个Y译码器层，所述多个Y译码器层中的至少一个设置在每个相邻的两个存储器组之间的多个存储器组。

50. 发明申请

US20120326748A1 LOGIC DEVICE AND SEMICONDUCTOR PACKAGE HAVING THE SAME 有权
标题翻译：具有相同功能的逻辑器件和半导体封装
公开(公告)号：US20120326748A1
公开(公告)日：2012-12-27
申请号：US13494477
申请日：2012-06-12
申请人： Ho-jung Kim , Jae-kwang Shin , Hyun-sik Choi , Hyun-su Jeong
发明人： Ho-jung Kim , Jae-kwang Shin , Hyun-sik Choi , Hyun-su Jeong
IPC分类号： H03K19/173
CPC分类号： H03K19/17704 , H03K19/17728 , H03K19/17736 , H03K19/1776
摘要： According to example embodiments, a logic device includes a first functional block configured to perform a first operation according to first operation information and a second operation according to second operation information, and a second functional block configured to perform a third operation according to the first operation information and a fourth operation according to the second operation information. The first functional block is configured to receive configuration information, to select one of the first operation information and the second operation information based on the configuration information, and to perform the first or second operation based on the selected first or second operation information. The second functional block is configured to receive the configuration information, to select one of the first operation information and the second operation information based on the configuration information, and to perform the third or fourth operation based on the selected first or second operation information.
摘要翻译：根据示例性实施例，逻辑设备包括：第一功能块，被配置为根据第一操作信息执行第一操作，并且根据第二操作信息进行第二操作;以及第二功能块，被配置为根据第一操作执行第三操作信息和根据第二操作信息的第四操作。第一功能块被配置为接收配置信息，基于配置信息选择第一操作信息和第二操作信息之一，并且基于所选择的第一或第二操作信息执行第一或第二操作。第二功能块被配置为接收配置信息，基于配置信息选择第一操作信息和第二操作信息之一，并且基于所选择的第一或第二操作信息来执行第三或第四操作。

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