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1. 发明授权

US08754670B2 Real time reconfigurable logic device and semiconductor package having the same 有权
标题翻译：具有相同功能的实时可重构逻辑器件和半导体封装
公开(公告)号：US08754670B2
公开(公告)日：2014-06-17
申请号：US13494477
申请日：2012-06-12
申请人： Ho-jung Kim , Jae-kwang Shin , Hyun-sik Choi , Hyun-su Jeong
发明人： Ho-jung Kim , Jae-kwang Shin , Hyun-sik Choi , Hyun-su Jeong
IPC分类号： H03K19/173
CPC分类号： H03K19/17704 , H03K19/17728 , H03K19/17736 , H03K19/1776
摘要： According to example embodiments, a logic device includes a first functional block configured to perform a first operation according to first operation information and a second operation according to second operation information, and a second functional block configured to perform a third operation according to the first operation information and a fourth operation according to the second operation information. The first functional block is configured to receive configuration information, to select one of the first operation information and the second operation information based on the configuration information, and to perform the first or second operation based on the selected first or second operation information. The second functional block is configured to receive the configuration information, to select one of the first operation information and the second operation information based on the configuration information, and to perform the third or fourth operation based on the selected first or second operation information.
摘要翻译：根据示例性实施例，逻辑设备包括：第一功能块，被配置为根据第一操作信息执行第一操作，并且根据第二操作信息进行第二操作;以及第二功能块，被配置为根据第一操作执行第三操作信息和根据第二操作信息的第四操作。第一功能块被配置为接收配置信息，基于配置信息选择第一操作信息和第二操作信息之一，并且基于所选择的第一或第二操作信息执行第一或第二操作。第二功能块被配置为接收配置信息，基于配置信息选择第一操作信息和第二操作信息之一，并且基于所选择的第一或第二操作信息来执行第三或第四操作。

2. 发明申请

US20120326748A1 LOGIC DEVICE AND SEMICONDUCTOR PACKAGE HAVING THE SAME 有权
标题翻译：具有相同功能的逻辑器件和半导体封装
公开(公告)号：US20120326748A1
公开(公告)日：2012-12-27
申请号：US13494477
申请日：2012-06-12
申请人： Ho-jung Kim , Jae-kwang Shin , Hyun-sik Choi , Hyun-su Jeong
发明人： Ho-jung Kim , Jae-kwang Shin , Hyun-sik Choi , Hyun-su Jeong
IPC分类号： H03K19/173
CPC分类号： H03K19/17704 , H03K19/17728 , H03K19/17736 , H03K19/1776
摘要： According to example embodiments, a logic device includes a first functional block configured to perform a first operation according to first operation information and a second operation according to second operation information, and a second functional block configured to perform a third operation according to the first operation information and a fourth operation according to the second operation information. The first functional block is configured to receive configuration information, to select one of the first operation information and the second operation information based on the configuration information, and to perform the first or second operation based on the selected first or second operation information. The second functional block is configured to receive the configuration information, to select one of the first operation information and the second operation information based on the configuration information, and to perform the third or fourth operation based on the selected first or second operation information.
摘要翻译：根据示例性实施例，逻辑设备包括：第一功能块，被配置为根据第一操作信息执行第一操作，并且根据第二操作信息进行第二操作;以及第二功能块，被配置为根据第一操作执行第三操作信息和根据第二操作信息的第四操作。第一功能块被配置为接收配置信息，基于配置信息选择第一操作信息和第二操作信息之一，并且基于所选择的第一或第二操作信息执行第一或第二操作。第二功能块被配置为接收配置信息，基于配置信息选择第一操作信息和第二操作信息之一，并且基于所选择的第一或第二操作信息来执行第三或第四操作。

3. 发明申请

US20120326747A1 RECONFIGURABLE LOGIC DEVICE 审中-公开
标题翻译：可重构逻辑器件
公开(公告)号：US20120326747A1
公开(公告)日：2012-12-27
申请号：US13449778
申请日：2012-04-18
申请人： Hyun-su Jeong , Ho-jung Kim , Jai-kwang Shin , Hyun-sik Choi
发明人： Hyun-su Jeong , Ho-jung Kim , Jai-kwang Shin , Hyun-sik Choi
IPC分类号： H03K19/173
CPC分类号： G11C13/003 , G11C13/0007 , G11C2213/79 , G11C2213/82
摘要： A logic device that includes a plurality of non-volatile memory cells configured to store possible output results related to the input signal. The logic device generating an output signal by selecting and accessing one of the plurality of non-volatile memory cells based on the input signal.
摘要翻译：一种逻辑设备，包括多个非易失性存储器单元，其被配置为存储与输入信号有关的可能的输出结果。逻辑装置通过基于输入信号选择和访问多个非易失性存储器单元之一来产生输出信号。

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