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41. 发明授权

US07312136B2 Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance 有权
标题翻译：制造具有应变通道层的晶片以提高电子和空穴迁移率以提高器件性能的方法
公开(公告)号：US07312136B2
公开(公告)日：2007-12-25
申请号：US10899270
申请日：2004-07-26
申请人： Chien-Chao Huang , Yee-Chia Yeo , Kuo-Nan Yang , Chun-Chieh Lin , Chenming Hu
发明人： Chien-Chao Huang , Yee-Chia Yeo , Kuo-Nan Yang , Chun-Chieh Lin , Chenming Hu
IPC分类号： H01L21/20
CPC分类号： H01L21/3247 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02658 , H01L21/02664 , H01L21/324 , H01L21/76259 , H01L29/1054
摘要： A method for making a SOI wafer with a strained silicon layer for increased electron and hole mobility is achieved. The method forms a porous silicon layer on a seed wafer. A H2 anneal is used to form a smooth surface on the porous silicon. A strain free (relaxed) epitaxial SixGe1-x layer is deposited and a bonding layer is formed. The seed wafer is then bonded to a handle wafer having an insulator on the surface. A spray etch is used to etch the porous Si layer resulting in a SOI handle wafer having portions of the porous Si layer on the relaxed SixGe1-x. The handle wafer is then annealed in H2 to convert the porous Si to a smooth strained Si layer on the relaxed SiGe layer of the SOI wafer.
摘要翻译：实现了制造具有用于增加电子和空穴迁移率的应变硅层的SOI晶片的方法。该方法在种子晶片上形成多孔硅层。使用H 2 H 2退火在多孔硅上形成光滑表面。沉积无应变的（松弛的）外延的Si 1 x 1-x层，并形成结合层。然后将种子晶片结合到在表面上具有绝缘体的手柄晶片。使用喷涂蚀刻来蚀刻多孔Si层，导致SOI处理晶片，其具有在松弛的Si 1 x 1-x x上的多孔Si层的部分。然后将手柄晶片在H 2 2中退火以将多孔Si转化为SOI晶片的松弛SiGe层上的平滑应变Si层。

42. 发明申请

US20060138557A1 Novel CMOS device 审中-公开
标题翻译：新型CMOS器件
公开(公告)号：US20060138557A1
公开(公告)日：2006-06-29
申请号：US11356865
申请日：2006-02-17
申请人： Chien-Chao Huang , Chao-Hsing Wang , Chung-Hu Ge , Chenming Hu
发明人： Chien-Chao Huang , Chao-Hsing Wang , Chung-Hu Ge , Chenming Hu
IPC分类号： H01L29/76
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823828
摘要： A method comprising providing a substrate having an NMOS device adjacent a PMOS device and forming a first stress layer over the NMOS and PMOS devices, wherein the first stress layer comprises a first tensile-stress layer or a compression-stress layer. An etch stop layer is formed over the first stress layer, and portions of the first stress layer and the etch stop layer are removed from over the NMOS device, leaving the first stress layer and the etch stop layer over the PMOS device. A second tensile-stress layer is formed over the NMOS device and over the first stress layer and the etch stop layer, and portions of the second tensile-stress layer and the etch stop layer are removed from over the PMOS device, leaving the second tensile-stress layer over the NMOS device.
摘要翻译：一种方法，包括提供具有邻近PMOS器件的NMOS器件的衬底，并在所述NMOS和PMOS器件上形成第一应力层，其中所述第一应力层包括第一拉伸应力层或压缩应力层。在第一应力层上形成蚀刻停止层，并且从NMOS器件上去除第一应力层和蚀刻停止层的部分，留下PMOS器件上的第一应力层和蚀刻停止层。第二拉伸应力层形成在NMOS器件上并且在第一应力层和蚀刻停止层上方，并且第二拉伸应力层和蚀刻停止层的部分从PMOS器件上除去，留下第二拉伸在NMOS器件上的应力层。

43. 发明授权

US07022561B2 CMOS device 有权
标题翻译： CMOS器件
公开(公告)号：US07022561B2
公开(公告)日：2006-04-04
申请号：US10307619
申请日：2002-12-02
申请人： Chien-Chao Huang , Chao-Hsing Wang , Chung-Hu Ge , Chenming Hu
发明人： Chien-Chao Huang , Chao-Hsing Wang , Chung-Hu Ge , Chenming Hu
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823828
摘要： A method comprising providing a substrate having an NMOS device adjacent a PMOS device and forming a first stress layer over the NMOS and PMOS devices, wherein the first stress layer comprises a first tensile-stress layer or a compression-stress layer. An etch stop layer is formed over the first stress layer, and portions of the first stress layer and the etch stop layer are removed from over the NMOS device, leaving the first stress layer and the etch stop layer over the PMOS device. A second tensile-stress layer is formed over the NMOS device and over the first stress layer and the etch stop layer, and portions of the second tensile-stress layer and the etch stop layer are removed from over the PMOS device, leaving the second tensile-stress layer over the NMOS device.
摘要翻译：一种方法，包括提供具有邻近PMOS器件的NMOS器件的衬底，并在所述NMOS和PMOS器件上形成第一应力层，其中所述第一应力层包括第一拉伸应力层或压缩应力层。在第一应力层上形成蚀刻停止层，并且从NMOS器件上去除第一应力层和蚀刻停止层的部分，留下PMOS器件上的第一应力层和蚀刻停止层。第二拉伸应力层形成在NMOS器件上并且在第一应力层和蚀刻停止层上方，并且第二拉伸应力层和蚀刻停止层的部分从PMOS器件上除去，留下第二拉伸在NMOS器件上的应力层。

44. 发明授权

US06812116B2 Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance 有权
标题翻译：制造具有应变通道层的晶片以提高电子和空穴迁移率以提高器件性能的方法
公开(公告)号：US06812116B2
公开(公告)日：2004-11-02
申请号：US10318454
申请日：2002-12-13
申请人： Chien-Chao Huang , Yee-Chia Yeo , Kuo-Nan Yang , Chun-Chieh Lin , Chenming Hu
发明人： Chien-Chao Huang , Yee-Chia Yeo , Kuo-Nan Yang , Chun-Chieh Lin , Chenming Hu
IPC分类号： H01L21301
CPC分类号： H01L21/3247 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02658 , H01L21/02664 , H01L21/324 , H01L21/76259 , H01L29/1054
摘要： A method for making a SOI wafer with a strained silicon layer for increased electron and hole mobility is achieved. The method forms a porous silicon layer on a seed wafer. A H2 anneal is used to form a smooth surface on the porous silicon. A strain free (relaxed) epitaxial SixGe1−x layer is deposited and a bonding layer is formed. The seed wafer is then bonded to a handle wafer having an insulator on the surface. A spray etch is used to etch the porous Si layer resulting in a SOI handle wafer having portions of the porous Si layer on the relaxed SixGe1−x. The handle wafer is then annealed in H2 to convert the porous Si to a smooth strained Si layer on the relaxed SiGe layer of the SOI wafer.
摘要翻译：实现了制造具有用于增加电子和空穴迁移率的应变硅层的SOI晶片的方法。该方法在种子晶片上形成多孔硅层。使用H2退火在多孔硅上形成光滑表面。沉积无应变的（松弛的）外延六面体Ge-x层并形成结合层。然后将种子晶片结合到在表面上具有绝缘体的手柄晶片。使用喷涂蚀刻来蚀刻多孔Si层，导致SOI处理晶片，其具有在松弛的SixGe1-x上的多孔Si层的部分。然后将处理晶片在H 2中退火以将多孔Si转化为SOI晶片的松弛SiGe层上的平滑应变Si层。

45. 发明申请

US20060286740A1 A METHOD FOR FORMING A DEVICE HAVING MULTIPLE SILICIDE TYPES 有权
标题翻译：一种形成具有多种硅酮类型的装置的方法
公开(公告)号：US20060286740A1
公开(公告)日：2006-12-21
申请号：US11467980
申请日：2006-08-29
申请人： Chun-Chieh LIN , Wen-Chin Lee , Yee-Chia Yeo , Chuan-Yi Lin , Chenming Hu
发明人： Chun-Chieh LIN , Wen-Chin Lee , Yee-Chia Yeo , Chuan-Yi Lin , Chenming Hu
IPC分类号： H01L21/8238 , H01L29/76
CPC分类号： H01L21/28052 , H01L21/823835 , H01L21/823842 , H01L29/458 , H01L29/4908 , H01L29/665 , H01L29/66795 , H01L29/785 , H01L29/78648
摘要： Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the second silicide. The first silicide and the second silicide may be an alloy silicide.
摘要翻译：提供一种半导体器件及其制造方法。该器件包括半导体衬底，衬底的第一区域中的第一硅化物和衬底的第二区域中的第二硅化物。第一硅化物可能与第二硅化物不同。第一硅化物和第二硅化物可以是合金硅化物。

46. 发明申请

US20060189056A1 Strained channel complementary field-effect transistors and methods of manufacture 有权
公开(公告)号：US20060189056A1
公开(公告)日：2006-08-24
申请号：US11407633
申请日：2006-04-20
申请人： Chih-Hsin Ko , Yee-Chia Yeo , Wen-Chin Lee , Chenming Hu
发明人： Chih-Hsin Ko , Yee-Chia Yeo , Wen-Chin Lee , Chenming Hu
IPC分类号： H01L21/8234
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/66636 , H01L29/7848
摘要： A transistor includes a gate dielectric overlying a channel region. A source region and a drain region are located on opposing sides of the channel region. The channel region is formed from a first semiconductor material and the source and drain regions are formed from a second semiconductor material. A gate electrode overlies the gate dielectric. A pair of spacers is formed on sidewalls of the gate electrode. Each of the spacers includes a void adjacent the channel region. A high-stress film can overlie the gate electrode and spacers.

47. 发明申请

US20050156274A1 Strained channel transistor and methods of manufacture 有权
标题翻译：应变通道晶体管及其制造方法
公开(公告)号：US20050156274A1
公开(公告)日：2005-07-21
申请号：US11081919
申请日：2005-03-16
申请人： Yee-Chia Yeo , Chih-Hsin Ko , Wen-Chin Lee , Chenming Hu
发明人： Yee-Chia Yeo , Chih-Hsin Ko , Wen-Chin Lee , Chenming Hu
IPC分类号： H01L21/762 , H01L21/8238 , H01L27/12 , H01L29/00
CPC分类号： H01L29/7842 , H01L21/76229 , H01L21/76237 , H01L21/76283 , H01L21/823807 , H01L21/823878 , H01L27/1203
摘要： A semiconductor device includes a region of semiconductor material with first and second isolation trenches formed therein. The first isolation trench is lined with a first material having a low oxygen diffusion rate and is filled with an insulating material. The second isolation trench is not lined with the first material but is filled with an insulating material. A first transistor is formed adjacent the first isolation region and a second transistor formed adjacent the second isolation region.
摘要翻译：半导体器件包括其中形成有第一和第二隔离沟槽的半导体材料区域。第一隔离槽衬有具有低氧扩散速率的第一材料并填充绝缘材料。第二隔离槽不是衬有第一材料，而是用绝缘材料填充。形成在第一隔离区域附近的第一晶体管和邻近第二隔离区域形成的第二晶体管。

48. 发明申请

US20050045969A1 Silicide/semiconductor structure and method of fabrication 有权
标题翻译：硅化物/半导体结构及其制造方法
公开(公告)号：US20050045969A1
公开(公告)日：2005-03-03
申请号：US10880992
申请日：2004-06-30
申请人： Wen-Chin Lee , Chung-Hu Ge , Chenming Hu
发明人： Wen-Chin Lee , Chung-Hu Ge , Chenming Hu
IPC分类号： H01L21/336 , H01L23/31 , H01L23/485 , H01L23/62 , H01L27/088 , H01L27/105 , H01L29/161 , H01L29/165 , H01L29/47 , H01L29/78
CPC分类号： H01L23/3192 , H01L23/485 , H01L29/161 , H01L29/165 , H01L29/47 , H01L29/665 , H01L29/66628 , H01L29/7834 , H01L2924/0002 , H01L2924/19041 , H01L2924/3025 , H01L2924/00
摘要： A preferred embodiment of the present invention comprises a dielectric/metal/2nd energy bandgap (Eg) semiconductor/1st Eg substrate structure. In order to reduce the contact resistance, a semiconductor with a lower energy bandgap (2nd Eg) is put in contact with metal. The energy bandgap of the 2nd Eg semiconductor is lower than the energy bandgap of the 1st Eg semiconductor and preferably lower than 1.1 eV. In addition, a layer of dielectric may be deposited on the metal. The dielectric layer has built-in stress to compensate for the stress in the metal, 2nd Eg semiconductor and 1st Eg substrate. A process of making the structure is also disclosed.
摘要翻译：本发明的优选实施例包括介电/金属/第二能带隙（Eg）半导体/第一基板结构。为了降低接触电阻，将具有较低能带隙（2Egg）的半导体与金属接触。第二半导体元件的能量带隙低于第一半导体器件的能带隙，优选低于1.1eV。此外，可以在金属上沉积介电层。电介质层具有内置的应力，以补偿金属，第二半导体和第一基板中的应力。还公开了制造该结构的过程。

49. 发明申请

US20050045965A1 Device having multiple silicide types and a method for its fabrication 有权
标题翻译：具有多种硅化物类型的器件及其制造方法
公开(公告)号：US20050045965A1
公开(公告)日：2005-03-03
申请号：US10831021
申请日：2004-04-23
申请人： Chun-Chieh Lin , Wen-Chin Lee , Yee-Chia Yeo , Chuan-Yi Lin , Chenming Hu
发明人： Chun-Chieh Lin , Wen-Chin Lee , Yee-Chia Yeo , Chuan-Yi Lin , Chenming Hu
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/768 , H01L21/8238 , H01L27/092 , H01L29/43 , H01L29/45 , H01L29/49 , H01L29/78 , H01L29/786
CPC分类号： H01L21/28052 , H01L21/823835 , H01L21/823842 , H01L29/458 , H01L29/4908 , H01L29/665 , H01L29/66795 , H01L29/785 , H01L29/78648
摘要： Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the second silicide. The first silicide and the second silicide may be an alloy silicide.
摘要翻译：提供一种半导体器件及其制造方法。该器件包括半导体衬底，衬底的第一区域中的第一硅化物和衬底的第二区域中的第二硅化物。第一硅化物可能与第二硅化物不同。第一硅化物和第二硅化物可以是合金硅化物。

50. 发明申请

US20050035345A1 Semiconductor device with high-k gate dielectric 有权
标题翻译：具有高k栅极电介质的半导体器件
公开(公告)号：US20050035345A1
公开(公告)日：2005-02-17
申请号：US10832020
申请日：2004-04-26
申请人： Chun-Chieh Lin , Wen-Chin Lee , Chenming Hu , Shang-Chih Chen , Chih-Hao Wang , Fu-Liang Yang , Yee-Chia Yeo
发明人： Chun-Chieh Lin , Wen-Chin Lee , Chenming Hu , Shang-Chih Chen , Chih-Hao Wang , Fu-Liang Yang , Yee-Chia Yeo
IPC分类号： H01L21/28 , H01L21/8234 , H01L29/51 , H01L29/06
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/823462 , H01L29/513 , H01L29/517 , H01L29/518
摘要： An integrated circuit includes a substrate, a first transistor, and a second transistor. The first transistor has a first gate dielectric portion located between a first gate electrode and the substrate. The first gate dielectric portion includes a first high-permittivity dielectric material and/or a second high-permittivity dielectric material. The first gate dielectric portion has a first equivalent silicon oxide thickness. The second transistor has a second gate dielectric portion located between a second gate electrode and the substrate. The second gate dielectric portion includes the first high-permittivity dielectric material and/or the second high-permittivity dielectric material. The second gate dielectric portion has a second equivalent silicon oxide thickness. The second equivalent silicon oxide thickness may be different than the first equivalent silicon oxide thickness.
摘要翻译：集成电路包括衬底，第一晶体管和第二晶体管。第一晶体管具有位于第一栅电极和衬底之间的第一栅电介质部分。第一栅介质部分包括第一高介电常数电介质材料和/或第二高介电常数介电材料。第一栅介质部分具有第一等效氧化硅厚度。第二晶体管具有位于第二栅电极和衬底之间的第二栅介质部分。第二栅介质部分包括第一高介电常数电介质材料和/或第二高介电常数介电材料。第二栅介质部分具有第二等效氧化硅厚度。第二等效氧化硅厚度可以不同于第一等效氧化硅厚度。

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