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1. 发明申请

US20050045969A1 Silicide/semiconductor structure and method of fabrication 有权
标题翻译：硅化物/半导体结构及其制造方法
公开(公告)号：US20050045969A1
公开(公告)日：2005-03-03
申请号：US10880992
申请日：2004-06-30
申请人： Wen-Chin Lee , Chung-Hu Ge , Chenming Hu
发明人： Wen-Chin Lee , Chung-Hu Ge , Chenming Hu
IPC分类号： H01L21/336 , H01L23/31 , H01L23/485 , H01L23/62 , H01L27/088 , H01L27/105 , H01L29/161 , H01L29/165 , H01L29/47 , H01L29/78
CPC分类号： H01L23/3192 , H01L23/485 , H01L29/161 , H01L29/165 , H01L29/47 , H01L29/665 , H01L29/66628 , H01L29/7834 , H01L2924/0002 , H01L2924/19041 , H01L2924/3025 , H01L2924/00
摘要： A preferred embodiment of the present invention comprises a dielectric/metal/2nd energy bandgap (Eg) semiconductor/1st Eg substrate structure. In order to reduce the contact resistance, a semiconductor with a lower energy bandgap (2nd Eg) is put in contact with metal. The energy bandgap of the 2nd Eg semiconductor is lower than the energy bandgap of the 1st Eg semiconductor and preferably lower than 1.1 eV. In addition, a layer of dielectric may be deposited on the metal. The dielectric layer has built-in stress to compensate for the stress in the metal, 2nd Eg semiconductor and 1st Eg substrate. A process of making the structure is also disclosed.
摘要翻译：本发明的优选实施例包括介电/金属/第二能带隙（Eg）半导体/第一基板结构。为了降低接触电阻，将具有较低能带隙（2Egg）的半导体与金属接触。第二半导体元件的能量带隙低于第一半导体器件的能带隙，优选低于1.1eV。此外，可以在金属上沉积介电层。电介质层具有内置的应力，以补偿金属，第二半导体和第一基板中的应力。还公开了制造该结构的过程。

2. 发明授权

US07183593B2 Heterostructure resistor and method of forming the same 有权
标题翻译：异质结构电阻及其形成方法
公开(公告)号：US07183593B2
公开(公告)日：2007-02-27
申请号：US10745831
申请日：2003-12-24
申请人： Yee-Chia Yeo , Wen-Chin Lee , Chih-Hsin Ko , Chung-Hu Ge , Chun-Chieh Lin , Chenming Hu
发明人： Yee-Chia Yeo , Wen-Chin Lee , Chih-Hsin Ko , Chung-Hu Ge , Chun-Chieh Lin , Chenming Hu
IPC分类号： H01L29/86 , H01L29/205
CPC分类号： H01L27/0629 , H01L29/165 , H01L29/8605
摘要： A heterostructure resistor comprises a doped region formed in a portion of a semiconductor substrate, the substrate comprising a first semiconductor material having a first natural lattice constant. The doped region comprises a semiconductor layer overlying the semiconductor substrate. The semiconductor layer comprises a second semiconductor material with a second natural lattice constant.
摘要翻译：异质结构电阻器包括形成在半导体衬底的一部分中的掺杂区域，该衬底包括具有第一自然晶格常数的第一半导体材料。掺杂区域包括覆盖半导体衬底的半导体层。半导体层包括具有第二自然晶格常数的第二半导体材料。

3. 发明申请

US20050116360A1 Complementary field-effect transistors and methods of manufacture 审中-公开
标题翻译：互补场效应晶体管及其制造方法
公开(公告)号：US20050116360A1
公开(公告)日：2005-06-02
申请号：US10896270
申请日：2004-07-21
申请人： Chien-Chao Huang , Fu-Liang Yang , Mickey Ken , Chenming Hu , Chung-Hu Ge , Wen-Chin Lee , Chih-Hsin Ko
发明人： Chien-Chao Huang , Fu-Liang Yang , Mickey Ken , Chenming Hu , Chung-Hu Ge , Wen-Chin Lee , Chih-Hsin Ko
IPC分类号： H01L21/336 , H01L21/76 , H01L21/8238 , H01L27/092 , H01L29/78 , H01L31/0328
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/045 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7845
摘要： A complementary FET and a method of manufacture is provided. The complementary FET utilizes a substrate having a surface layer with a crystal orientation. Tensile stress, which increases performance of the NMOS FETs, is added by silicided source/drain regions, tensile-stress film, shallow trench isolations, inter-layer dielectric, or the like.
摘要翻译：提供互补的FET和制造方法。互补FET使用具有<100>晶体取向的表面层的衬底。通过硅化源极/漏极区域，拉伸应力膜，浅沟槽隔离层，层间电介质等添加了提高NMOS FET的性能的拉伸应力。

4. 发明申请

US20050093018A1 STRAINED SILICON STRUCTURE 有权
标题翻译：应变硅结构
公开(公告)号：US20050093018A1
公开(公告)日：2005-05-05
申请号：US10699574
申请日：2003-10-31
申请人： Chung-Hu Ge , Wen-Chin Lee , Chenming Hu
发明人： Chung-Hu Ge , Wen-Chin Lee , Chenming Hu
IPC分类号： H01L21/02 , H01L21/20 , H01L21/336 , H01L21/338 , H01L21/762 , H01L21/8238 , H01L29/08 , H01L29/10 , H01L29/74 , H01L29/78 , H01L31/0328 , H01L31/072
CPC分类号： H01L29/0847 , H01L21/823807 , H01L21/823878 , H01L29/1054 , H01L29/6659 , H01L29/7833 , H01L29/7842
摘要： A semiconductor device includes a substrate, a first epitaxial layer, a second epitaxial layer, a third epitaxial layer, a first trench, and a second trench. The first epitaxial layer is formed on the substrate. The first layer has lattice mismatch relative to the substrate. The second epitaxial layer is formed on the first layer, and the second layer has lattice mismatch relative to the first layer. The third epitaxial layer is formed on the second layer, and the third layer has lattice mismatch relative to the second layer. Hence, the third layer may be strained silicon. The first trench extends through the first layer. The second trench extends through the third layer and at least partially through the second layer. At least part of the second trench is aligned with at least part of the first trench, and the second trench is at least partially filled with an insulating material.
摘要翻译：半导体器件包括衬底，第一外延层，第二外延层，第三外延层，第一沟槽和第二沟槽。第一外延层形成在基板上。第一层相对于衬底具有晶格失配。第二外延层形成在第一层上，第二层相对于第一层具有晶格失配。第三外延层形成在第二层上，第三层相对于第二层具有晶格失配。因此，第三层可以是应变硅。第一沟槽延伸穿过第一层。第二沟槽延伸穿过第三层并且至少部分地穿过第二层。所述第二沟槽的至少一部分与所述第一沟槽的至少一部分对准，并且所述第二沟槽至少部分地填充有绝缘材料。

5. 发明授权

US07453133B2 Silicide/semiconductor structure and method of fabrication 有权
标题翻译：硅化物/半导体结构及其制造方法
公开(公告)号：US07453133B2
公开(公告)日：2008-11-18
申请号：US10880992
申请日：2004-06-30
申请人： Wen-Chin Lee , Chung-Hu Ge , Chenming Hu
发明人： Wen-Chin Lee , Chung-Hu Ge , Chenming Hu
IPC分类号： H01L27/095
CPC分类号： H01L23/3192 , H01L23/485 , H01L29/161 , H01L29/165 , H01L29/47 , H01L29/665 , H01L29/66628 , H01L29/7834 , H01L2924/0002 , H01L2924/19041 , H01L2924/3025 , H01L2924/00
摘要： A preferred embodiment of the present invention comprises a dielectric/metal/2nd energy bandgap (Eg) semiconductor/1st Eg substrate structure. In order to reduce the contact resistance, a semiconductor with a lower energy bandgap (2nd Eg) is put in contact with metal. The energy bandgap of the 2nd Eg semiconductor is lower than the energy bandgap of the 1st Eg semiconductor and preferably lower than 1.1eV. In addition, a layer of dielectric may be deposited on the metal. The dielectric layer has built-in stress to compensate for the stress in the metal, 2nd Eg semiconductor and 1st Eg substrate. A process of making the structure is also disclosed.
摘要翻译：本发明的优选实施方案包括介电/金属/第二能带隙（E />）半导体/第一电极 g 衬底结构。为了降低接触电阻，将具有较低能量带隙（2Ω）的半导体与金属接触。第二个和第二个半导体的能带隙比第一个第二半导体的能量带隙低，半导体，优选低于1.1eV。此外，可以在金属上沉积介电层。电介质层具有内置应力以补偿金属，第二和第二半导体中的应力， g 衬底。还公开了制造该结构的过程。

6. 发明授权

US07342289B2 Strained silicon MOS devices 有权
标题翻译：应变硅MOS器件
公开(公告)号：US07342289B2
公开(公告)日：2008-03-11
申请号：US10637351
申请日：2003-08-08
申请人： Chien-Chao Huang , Chung-Hu Ge , Wen-Chin Lee , Chenming Hu , Carlos H. Diaz , Fu-Liang Yang
发明人： Chien-Chao Huang , Chung-Hu Ge , Wen-Chin Lee , Chenming Hu , Carlos H. Diaz , Fu-Liang Yang
IPC分类号： H01L29/76
CPC分类号： H01L29/6659 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L29/665 , H01L29/6656 , H01L29/7833 , H01L29/7842 , H01L29/7843
摘要： A structure to improve carrier mobility of a MOS device in an integrated circuit. The structure comprises a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a conformal stress film covering the source region, the drain region, and the conductive gate. In addition, the structure may comprise a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a plurality of stress films covering the source region, the drain region, and the conductive gate. Moreover, the structure may comprise a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a spacer disposed adjacent to the conductive gate, the spacer having a width less than 550 angstroms; a stress film covering the source region, the drain region, the conductive gate, and the spacer.
摘要翻译：一种提高集成电路中MOS器件的载流子迁移率的结构。该结构包括含有源区和漏区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 覆盖源极区域，漏极区域和导电栅极的共形应力膜。此外，该结构可以包括含有源极区和漏极区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 覆盖源极区域，漏极区域和导电栅极的多个应力膜。此外，该结构可以包括含有源极区和漏极区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 间隔件设置成与导电栅极相邻，间隔物具有小于550埃的宽度; 覆盖源极区域，漏极区域，导电栅极和间隔物的应力膜。

7. 发明授权

US07045836B2 Semiconductor structure having a strained region and a method of fabricating same 有权
公开(公告)号：US07045836B2
公开(公告)日：2006-05-16
申请号：US10657616
申请日：2003-09-08
申请人： Wen-Chin Lee , Chung-Hu Ge , Chenming Hu
发明人： Wen-Chin Lee , Chung-Hu Ge , Chenming Hu
IPC分类号： H01L21/00
CPC分类号： H01L21/02381 , H01L21/02447 , H01L21/0245 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/76232 , H01L21/823412 , H01L29/1054 , H01L29/66651
摘要： A semiconductor structure including a highly strained selective epitaxial top layer suitable for use in fabricating a strained channel transistor. The top layer is deposited on the uppermost of a series of one or more lower layers. The lattice of each layer is mismatched with the lattice of its subjacent layer by an amount not less than the lattice mismatch between the lowest layer of the series and a substrate on which it resides. A trench is formed in the uppermost series layer. The trench has rounded corners so that a dielectric material filling the trench conforms to the round corners. The rounded corners are produced by heating the uppermost series layer after trench formation.

8. 发明授权

US06902965B2 Strained silicon structure 有权
标题翻译：应变硅结构
公开(公告)号：US06902965B2
公开(公告)日：2005-06-07
申请号：US10699574
申请日：2003-10-31
申请人： Chung-Hu Ge , Wen-Chin Lee , Chenming Hu
发明人： Chung-Hu Ge , Wen-Chin Lee , Chenming Hu
IPC分类号： H01L21/02 , H01L21/20 , H01L21/336 , H01L21/338 , H01L21/762 , H01L21/8238 , H01L29/08 , H01L29/10 , H01L29/74 , H01L29/78 , H01L31/0328 , H01L31/072
CPC分类号： H01L29/0847 , H01L21/823807 , H01L21/823878 , H01L29/1054 , H01L29/6659 , H01L29/7833 , H01L29/7842
摘要： A semiconductor device includes a substrate, a first epitaxial layer, a second epitaxial layer, a third epitaxial layer, a first trench, and a second trench. The first epitaxial layer is formed on the substrate. The first layer has lattice mismatch relative to the substrate. The second epitaxial layer is formed on the first layer, and the second layer has lattice mismatch relative to the first layer. The third epitaxial layer is formed on the second layer, and the third layer has lattice mismatch relative to the second layer. Hence, the third layer may be strained silicon. The first trench extends through the first layer. The second trench extends through the third layer and at least partially through the second layer. At least part of the second trench is aligned with at lease part of the first trench, and the second trench is at least partially filled with an insulating material.
摘要翻译：半导体器件包括衬底，第一外延层，第二外延层，第三外延层，第一沟槽和第二沟槽。第一外延层形成在基板上。第一层相对于基底具有晶格失配。第二外延层形成在第一层上，第二层相对于第一层具有晶格失配。第三外延层形成在第二层上，第三层相对于第二层具有晶格失配。因此，第三层可以是应变硅。第一沟槽延伸穿过第一层。第二沟槽延伸穿过第三层并且至少部分地穿过第二层。第二沟槽的至少一部分与第一沟槽的至少部分对准，并且第二沟槽至少部分地填充有绝缘材料。

9. 发明授权

US06900502B2 Strained channel on insulator device 有权
标题翻译：应变绝缘体上的通道
公开(公告)号：US06900502B2
公开(公告)日：2005-05-31
申请号：US10407761
申请日：2003-04-03
申请人： Chung-Hu Ge , Chao-Hsuing Wang , Chien-Chao Huang , Wen-Chin Lee , Chenming Hu
发明人： Chung-Hu Ge , Chao-Hsuing Wang , Chien-Chao Huang , Wen-Chin Lee , Chenming Hu
IPC分类号： H01L21/00 , H01L21/30 , H01L21/762 , H01L21/84 , H01L27/01 , H01L27/12 , H01L29/02 , H01L29/72 , H01L29/772
CPC分类号： H01L21/823807 , H01L21/76264 , H01L21/84 , H01L27/1203 , H01L29/7848
摘要： A semiconductor device 10 includes a substrate 12 (e.g., a silicon substrate) with an insulating layer 14 (e.g., an oxide such as silicon dioxide) disposed thereon. A first semiconducting material layer 16 (e.g., SiGe) is disposed on the insulating layer 14 and a second semiconducting material layer 18 (e.g., Si) is disposed on the first semiconducting material layer 16. The first and second semiconducting material layers 16 and 18 preferably have different lattice constants such that the first semiconducting material layer 16 is compressive and the second semiconducting material layer is tensile 18.
摘要翻译：半导体器件10包括其上设置有绝缘层14（例如氧化物如二氧化硅）的衬底12（例如，硅衬底）。第一半导体材料层16（例如，SiGe）设置在绝缘层14上，并且第二半导体材料层18（例如，Si）设置在第一半导体材料层16上。第一和第二半导体材料层16和18优选地具有不同的晶格常数，使得第一半导体材料层16是压缩的，并且第二半导体材料层是拉伸18。

10. 发明授权

US07029994B2 Strained channel on insulator device 失效
标题翻译：应变绝缘体上的通道
公开(公告)号：US07029994B2
公开(公告)日：2006-04-18
申请号：US11083537
申请日：2005-03-18
申请人： Chung-Hu Ge , Chao-Hsiung Wang , Chien-Chao Huang , Wen-Chin Lee , Chenming Hu
发明人： Chung-Hu Ge , Chao-Hsiung Wang , Chien-Chao Huang , Wen-Chin Lee , Chenming Hu
IPC分类号： H01L21/20
CPC分类号： H01L21/823807 , H01L21/76264 , H01L21/84 , H01L27/1203 , H01L29/7848
摘要： A semiconductor device 10 includes a substrate 12 (e.g., a silicon substrate) with an insulating layer 14 (e.g., an oxide such as silicon dioxide) disposed thereon. A first semiconducting material layer 16 (e.g., SiGe) is disposed on the insulating layer 14 and a second semiconducting material layer 18 (e.g., Si) is disposed on the first semiconducting material layer 16. The first and second semiconducting material layers 16 and 18 preferably have different lattice constants such that the first semiconducting material layer 16 is compressive and the second semiconducting material layer is tensile 18.
摘要翻译：半导体器件10包括其上设置有绝缘层14（例如氧化物如二氧化硅）的衬底12（例如，硅衬底）。第一半导体材料层16（例如，SiGe）设置在绝缘层14上，并且第二半导体材料层18（例如，Si）设置在第一半导体材料层16上。第一和第二半导体材料层16和18优选地具有不同的晶格常数，使得第一半导体材料层16是压缩的，并且第二半导体材料层是拉伸18。

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