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1. 发明申请

US20100187670A1 On-Chip Heat Spreader 有权
标题翻译：片上散热器
公开(公告)号：US20100187670A1
公开(公告)日：2010-07-29
申请号：US12617500
申请日：2009-11-12
申请人： Chuan-Yi Lin , Ching-Chen Hao , Chen Cheng Chou , Sheng-Yuan Lin
发明人： Chuan-Yi Lin , Ching-Chen Hao , Chen Cheng Chou , Sheng-Yuan Lin
IPC分类号： H01L23/36 , H01L23/48 , H01L23/52
CPC分类号： H01L23/34 , H01L21/4814 , H01L21/76898 , H01L23/055 , H01L23/3677 , H01L23/42 , H01L23/481 , H01L24/80 , H01L25/0657 , H01L2224/05001 , H01L2224/05009 , H01L2224/05109 , H01L2224/05111 , H01L2224/05116 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05184 , H01L2224/05568 , H01L2224/05609 , H01L2224/05611 , H01L2224/05616 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05684 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2225/06589 , H01L2924/14 , H01L2924/19105 , H01L2924/00 , H01L2924/00014 , H01L2924/0105 , H01L2924/01079
摘要： A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.
摘要翻译：描述了具有片上散热器和成形方法的芯片的三维（3D）堆叠芯片结构。 3D堆叠芯片结构包括具有形成在前表面上的电介质层的第一基板的第一裸片。可以在电介质层中同时形成一个或多个接合焊盘和散热器。第一管芯与第二管芯的表面上的相应的接合焊盘接合以形成堆叠的芯片结构。堆叠的芯片结构中产生的热可以通过散热器扩散到堆叠的芯片结构的边缘。

2. 发明授权

US07645973B2 Sun-tracking power generating apparatus 失效
标题翻译：太阳跟踪发电装置
公开(公告)号：US07645973B2
公开(公告)日：2010-01-12
申请号：US11872265
申请日：2007-10-15
申请人： Chien-Feng Lin , Chuan-Yi Lin , Cheng-Min Chen
发明人： Chien-Feng Lin , Chuan-Yi Lin , Cheng-Min Chen
IPC分类号： G01J1/20
CPC分类号： G05D3/105 , F24S50/20 , G01S3/7861 , H02S20/10 , H02S20/32 , H02S40/22 , Y02E10/52
摘要： A solar-tracking power generating apparatus includes a plurality of sensing units having a directional light-extraction member each, a plurality of solar batteries associated with a light-gathering device each, and a solar trajectory simulation unit. Therefore, the solar-tracking power generating apparatus enables more accurate tracking of solar position and focusing of more sunlight on the solar batteries, so that the solar batteries could absorb more sunlight and convert the same into an increased amount of electric power.
摘要翻译：太阳跟踪发电装置包括多个感测单元，每个感测单元具有定向光取出构件，每个都具有与各个聚光装置相关联的多个太阳能电池以及太阳能轨迹模拟单元。因此，太阳能跟踪发电装置能够更准确地跟踪太阳能位置并且将太阳光聚焦在太阳能电池上，使得太阳能电池可以吸收更多的太阳光并将其转换成增加的电力。

3. 发明申请

US20060286740A1 A METHOD FOR FORMING A DEVICE HAVING MULTIPLE SILICIDE TYPES 有权
标题翻译：一种形成具有多种硅酮类型的装置的方法
公开(公告)号：US20060286740A1
公开(公告)日：2006-12-21
申请号：US11467980
申请日：2006-08-29
申请人： Chun-Chieh LIN , Wen-Chin Lee , Yee-Chia Yeo , Chuan-Yi Lin , Chenming Hu
发明人： Chun-Chieh LIN , Wen-Chin Lee , Yee-Chia Yeo , Chuan-Yi Lin , Chenming Hu
IPC分类号： H01L21/8238 , H01L29/76
CPC分类号： H01L21/28052 , H01L21/823835 , H01L21/823842 , H01L29/458 , H01L29/4908 , H01L29/665 , H01L29/66795 , H01L29/785 , H01L29/78648
摘要： Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the second silicide. The first silicide and the second silicide may be an alloy silicide.
摘要翻译：提供一种半导体器件及其制造方法。该器件包括半导体衬底，衬底的第一区域中的第一硅化物和衬底的第二区域中的第二硅化物。第一硅化物可能与第二硅化物不同。第一硅化物和第二硅化物可以是合金硅化物。

4. 发明申请

US20050045965A1 Device having multiple silicide types and a method for its fabrication 有权
标题翻译：具有多种硅化物类型的器件及其制造方法
公开(公告)号：US20050045965A1
公开(公告)日：2005-03-03
申请号：US10831021
申请日：2004-04-23
申请人： Chun-Chieh Lin , Wen-Chin Lee , Yee-Chia Yeo , Chuan-Yi Lin , Chenming Hu
发明人： Chun-Chieh Lin , Wen-Chin Lee , Yee-Chia Yeo , Chuan-Yi Lin , Chenming Hu
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/768 , H01L21/8238 , H01L27/092 , H01L29/43 , H01L29/45 , H01L29/49 , H01L29/78 , H01L29/786
CPC分类号： H01L21/28052 , H01L21/823835 , H01L21/823842 , H01L29/458 , H01L29/4908 , H01L29/665 , H01L29/66795 , H01L29/785 , H01L29/78648
摘要： Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the second silicide. The first silicide and the second silicide may be an alloy silicide.
摘要翻译：提供一种半导体器件及其制造方法。该器件包括半导体衬底，衬底的第一区域中的第一硅化物和衬底的第二区域中的第二硅化物。第一硅化物可能与第二硅化物不同。第一硅化物和第二硅化物可以是合金硅化物。

5. 发明授权

US07271431B2 Integrated circuit structure and method of fabrication 有权
标题翻译：集成电路结构及制作方法
公开(公告)号：US07271431B2
公开(公告)日：2007-09-18
申请号：US10877441
申请日：2004-06-25
申请人： Chuan-Yi Lin , Shien-Yang Wu , Yee-Chia Yeo
发明人： Chuan-Yi Lin , Shien-Yang Wu , Yee-Chia Yeo
IPC分类号： H01L29/76
CPC分类号： H01L21/823481 , H01L21/823475
摘要： According to the present invention, the integrated circuit includes isolation field regions on a semiconductor substrate. Gate dielectrics are formed on a surface of a substrate. Gate electrodes are formed on the gate dielectrics. A photo resist is formed covering the active regions. Dummy patterns are selectively etched. A dummy substrate is selectively etched. The photo resist is then removed. A pair of spacers is formed along opposite sidewalls of the gate electrode and the gate dielectric. The source and drain are formed on the surface of said substrate and on opposite sides of the gate. Silicide is formed on the gate electrode, source, and drain. A layer of inter-level dielectric is then formed. A contact opening and metal wiring are then formed.
摘要翻译：根据本发明，集成电路包括半导体衬底上的隔离场区域。栅极电介质形成在衬底的表面上。栅电极形成在栅极电介质上。形成覆盖有源区的光致抗蚀剂。虚拟图案被有选择地蚀刻。选择性地蚀刻虚设衬底。然后去除光刻胶。在栅电极和栅极电介质的相对侧壁上形成一对间隔物。源极和漏极形成在所述衬底的表面上和栅极的相对侧上。在栅电极，源极和漏极上形成硅化物。然后形成层间电介质层。然后形成接触开口和金属布线。

6. 发明授权

US07112483B2 Method for forming a device having multiple silicide types 有权
标题翻译：用于形成具有多种硅化物类型的器件的方法
公开(公告)号：US07112483B2
公开(公告)日：2006-09-26
申请号：US10831021
申请日：2004-04-23
申请人： Chun-Chieh Lin , Wen-Chin Lee , Yee-Chia Yeo , Chuan-Yi Lin , Chenming Hu
发明人： Chun-Chieh Lin , Wen-Chin Lee , Yee-Chia Yeo , Chuan-Yi Lin , Chenming Hu
IPC分类号： H01L21/8238 , H01L21/44
CPC分类号： H01L21/28052 , H01L21/823835 , H01L21/823842 , H01L29/458 , H01L29/4908 , H01L29/665 , H01L29/66795 , H01L29/785 , H01L29/78648
摘要： Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the second silicide. The first silicide and the second silicide may be an alloy silicide.
摘要翻译：提供一种半导体器件及其制造方法。该器件包括半导体衬底，衬底的第一区域中的第一硅化物和衬底的第二区域中的第二硅化物。第一硅化物可能与第二硅化物不同。第一硅化物和第二硅化物可以是合金硅化物。

7. 发明申请

US20050224897A1 High-K gate dielectric stack with buffer layer to improve threshold voltage characteristics 审中-公开
标题翻译：具有缓冲层的高K栅介质叠层，以提高阈值电压特性
公开(公告)号：US20050224897A1
公开(公告)日：2005-10-13
申请号：US10809974
申请日：2004-03-26
申请人： Shang-Chih Chen , Chih-Hao Wang , Yee-Chia Yeo , Feng-Der Chin , Chuan-Yi Lin
发明人： Shang-Chih Chen , Chih-Hao Wang , Yee-Chia Yeo , Feng-Der Chin , Chuan-Yi Lin
IPC分类号： H01L21/28 , H01L21/336 , H01L29/51 , H01L29/78 , H01L39/22
CPC分类号： H01L29/517 , H01L21/28202 , H01L29/513 , H01L29/518 , H01L29/6656 , H01L29/78
摘要： A high-K gate dielectric stack for a MOSFET gate structure to reduce Voltage threshold (Vth) shifts and method for forming the same, the method including providing a high-K gate dielectric layer over a semiconductor substrate; forming a buffer dielectric layer on the high-K gate dielectric including a dopant selected from the group consisting of a metal, a semiconductor, and nitrogen; forming a gate electrode layer on the buffer dielectric layer; and, lithographically patterning the gate electrode layer and etching to form a gate structure.
摘要翻译：用于降低电压阈值（V SUB）的MOSFET栅极结构的高K栅极电介质叠层及其形成方法，所述方法包括在半导体衬底上提供高K栅介质层 ; 在包括选自金属，半导体和氮的掺杂剂的高K栅极电介质上形成缓冲介电层; 在所述缓冲电介质层上形成栅电极层; 并且平版印刷图案化栅极电极层和蚀刻以形成栅极结构。

8. 发明授权

US08314483B2 On-chip heat spreader 有权
标题翻译：片上散热器
公开(公告)号：US08314483B2
公开(公告)日：2012-11-20
申请号：US12617500
申请日：2009-11-12
申请人： Chuan-Yi Lin , Ching-Chen Hao , Chen Cheng Chou , Sheng-Yuan Lin
发明人： Chuan-Yi Lin , Ching-Chen Hao , Chen Cheng Chou , Sheng-Yuan Lin
IPC分类号： H01L23/36
CPC分类号： H01L23/34 , H01L21/4814 , H01L21/76898 , H01L23/055 , H01L23/3677 , H01L23/42 , H01L23/481 , H01L24/80 , H01L25/0657 , H01L2224/05001 , H01L2224/05009 , H01L2224/05109 , H01L2224/05111 , H01L2224/05116 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05184 , H01L2224/05568 , H01L2224/05609 , H01L2224/05611 , H01L2224/05616 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05684 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2225/06589 , H01L2924/14 , H01L2924/19105 , H01L2924/00 , H01L2924/00014 , H01L2924/0105 , H01L2924/01079
摘要： A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.
摘要翻译：描述了具有片上散热器和成形方法的芯片的三维（3D）堆叠芯片结构。 3D堆叠芯片结构包括具有形成在前表面上的电介质层的第一基板的第一裸片。可以在电介质层中同时形成一个或多个接合焊盘和散热器。第一管芯与第二管芯的表面上的相应的接合焊盘接合以形成堆叠的芯片结构。堆叠的芯片结构中产生的热可以通过散热器扩散到堆叠的芯片结构的边缘。

9. 发明授权

US08168529B2 Forming seal ring in an integrated circuit die 有权
标题翻译：在集成电路模具中形成密封圈
公开(公告)号：US08168529B2
公开(公告)日：2012-05-01
申请号：US12618412
申请日：2009-11-13
申请人： Chuan-Yi Lin , Ching-Chen Hao , Chen Cheng Chou , Sheng-Yuan Lin
发明人： Chuan-Yi Lin , Ching-Chen Hao , Chen Cheng Chou , Sheng-Yuan Lin
IPC分类号： H01L21/4763
CPC分类号： H01L21/76898 , H01L23/585 , H01L25/0657 , H01L2224/05109 , H01L2224/05116 , H01L2224/05144 , H01L2224/05147 , H01L2224/05573 , H01L2224/05609 , H01L2224/05611 , H01L2224/05616 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05684 , H01L2224/16 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/0105 , H01L2924/01079
摘要： The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs.
摘要翻译：描述在半导体集成电路（IC）裸片中形成密封环。通常在半导体IC芯片中形成通硅通孔（TSV），以便于形成三维（3D）堆叠管芯结构。 TSV可用于在3D堆叠模具结构的不同模具中的组件之间提供电连接。密封环形成在IC管芯的金属间电介质（IMD）层中，其包围有源电路区域。真正的环在形成TSV之前形成，防止在随后的TSV形成过程中，水分或其它不期望的化学试剂扩散到有源电路区域。

10. 发明申请

US20110253194A1 PHOTOELECTRIC CONVERSION 审中-公开
标题翻译：光电转换
公开(公告)号：US20110253194A1
公开(公告)日：2011-10-20
申请号：US12760000
申请日：2010-04-14
申请人： Chien-Feng LIN , Cheng-Yu Huang , Te-Kai Ku , Chuan-Yi Lin
发明人： Chien-Feng LIN , Cheng-Yu Huang , Te-Kai Ku , Chuan-Yi Lin
IPC分类号： H01L31/052
CPC分类号： H01L31/052 , H01L31/048 , H01L31/0543 , H02S40/42 , Y02E10/52
摘要： A photoelectric conversion is capable of converting the light energy into electrical power, comprising a tempered glass layer, a lens module, a substrate and a heat sink unit, wherein the lens module is formed from a plurality of lens units, which locate at one side of the tempered glass layer. A gap is formed via a plurality of protruding poles located between the lens units and the tempered glass layer. The gap is filled with transparent rubbers. A plurality of receiving units is located one side of the substrate for dissipating heat energy from the receiving units. The light energy is converted through the receiving units into the electrical energy by focusing the light to the receiving units via the tempered glass layer and the lens module.
摘要翻译：光电转换能够将光能转换成电力，包括钢化玻璃层，透镜模块，基板和散热单元，其中透镜模块由位于一侧的多个透镜单元形成的钢化玻璃层。通过位于透镜单元和强化玻璃层之间的多个突出极形成间隙。间隙充满透明橡胶。多个接收单元位于基板的一侧，用于从接收单元散发热能。通过经由强化玻璃层和透镜模块将光聚焦到接收单元，将光能量通过接收单元转换成电能。

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