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41. 发明授权

US5463529A High power dissipating packages with matched heatspreader heatsink assemblies 失效
标题翻译：具有匹配散热器散热器组件的大功率消散封装
公开(公告)号：US5463529A
公开(公告)日：1995-10-31
申请号：US317968
申请日：1994-10-04
申请人： Chok J. Chia , Manian Alagaratnam , Qwai H. Low , Seng-Sooi Lim
发明人： Chok J. Chia , Manian Alagaratnam , Qwai H. Low , Seng-Sooi Lim
IPC分类号： F02F7/00 , H01L23/367 , H01L23/40 , H05K7/20
CPC分类号： H01L23/40 , F02F7/00 , H01L23/3675 , H01L2924/0002 , Y10T29/4913
摘要： A removable heatsink assembly comprised of a heatsink unit and a heatspreader is provided. The heatsink unit has at least one fin and a coupling collar for radiating heat away from a packaged electronic device. The heatspreader includes a platform attached to an inner collar in thermal contact with the packaged electronic device. The platform has one or more tabs suitable for mating with one or more flanges located on the coupling collar of the heatsink unit. Coupling grooves within the flanges engage the platform of the heatspreader when the flanges are mated with the heatspreader tabs and the heatsink is turned. The heatsink can therefore be quickly and conveniently attached to or removed from the heatspreader. The present invention thus permits a wide variety of different heatsinks to be interchangeably used with a single heatspreader attached to an electronic device package.
摘要翻译：提供了由散热器单元和散热器组成的可拆卸的散热器组件。散热器单元具有至少一个翅片和用于从封装的电子设备辐射热量的联接套环。散热器包括附接到与封装的电子设备热接触的内部套环的平台。该平台具有一个或多个适合于与位于散热器单元的联接环上的一个或多个凸缘相配合的凸片。当凸缘与散热片接头配合并且散热片转动时，凸缘内的耦合凹槽接合散热器的平台。因此，散热器可以快速方便地附接到散热器或从散热器移除。因此，本发明允许各种不同的散热器与附接到电子设备封装的单个散热器可互换地使用。

42. 发明授权

US5262927A Partially-molded, PCB chip carrier package 失效
标题翻译：部分成型，PCB芯片载体封装
公开(公告)号：US5262927A
公开(公告)日：1993-11-16
申请号：US834182
申请日：1992-02-07
申请人： Chok J. Chia , Seng-Sooi Lim
发明人： Chok J. Chia , Seng-Sooi Lim
IPC分类号： H01L23/12 , G03F7/20 , H01L23/31 , H01L23/495 , H01L23/498 , H01L23/50 , H01L29/06 , H05K1/11
CPC分类号： G03F7/70433 , H01L23/3121 , H01L23/49517 , H01L23/49541 , H01L23/49861 , H01L2224/48091 , H01L2224/48247 , H01L2224/49109 , H01L24/48 , H01L24/49 , H01L29/0657 , H01L2924/00014 , H01L2924/01014 , H01L2924/01078 , H01L2924/14 , H01L2924/15151 , H01L2924/15153 , H01L2924/1517 , H01L2924/1532 , H01L2924/181 , H01L2924/18301
摘要： A dambar-less leadframe is sandwiched between two printed circuit boards (PCBs). The PCBs form a major portion of the package body, and isolate the leadframe leads from plastic molding compound. In one embodiment, an upper PCB (substrate) is formed as a square ring, having an opening containing a heat sink element. A lower PCB is also formed as a square ring, and has a smaller opening for receiving a die. The back face of the die is mounted to the heat sink. The exposed front face of the die is wire bonded to inner ends of conductive traces on the exposed face of the lower PCB. The outer ends of the traces are electrically connected to the leadframe leads by plated-through vias extending through the two PCBs. The plated-through vias additionally secure the sandwich structure together. Plastic molding compound is injection/transfer molded over the front face of the die and the bond wires, forming a partially-molded package. In another embodiment, the upper PCB is a solid planar element, and is not provided with an opening for a heat sink. The back face of the die is mounted to the inside surface of the upper PCB.

43. 发明授权

US5197183A Modified lead frame for reducing wire wash in transfer molding of IC packages 失效
标题翻译：改进的引线框架，用于减少IC封装的传输成型中的电线清洗
公开(公告)号：US5197183A
公开(公告)日：1993-03-30
申请号：US787848
申请日：1991-11-05
申请人： Chok J. Chia , Seng-Sooi Lim
发明人： Chok J. Chia , Seng-Sooi Lim
IPC分类号： B29C45/14 , H01L21/56 , H01L23/495
CPC分类号： B29C45/14655 , H01L21/565 , H01L23/49551 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/181 , H01L2924/3025 , Y10T29/49121
摘要： In a leadframe supporting a semiconductor device, the tiebar adjacent the mold gate is kinked, or cut and bent, to form a baffle shielding bond wires connecting the semiconductor device to the leadframe from damage by a jet of incoming molding compound. Whether kinked or cut/bent, the baffle extends out of the plane of the leadframe so as to be disposed more-or-less directly in front of the gate.
摘要翻译：在支撑半导体器件的引线框架中，与模具门相邻的连接杆被扭结或切割和弯曲，以形成将半导体器件与引线框架连接的挡板屏蔽接合线，以免由入射的模塑料的射流造成损坏。无论是弯曲还是切割/弯曲，挡板延伸出引线框架的平面，以便直接在门的前方多或少地设置。

44. 发明授权

US06861343B2 Buffer metal layer 失效
标题翻译：缓冲金属层
公开(公告)号：US06861343B2
公开(公告)日：2005-03-01
申请号：US10267410
申请日：2002-10-09
申请人： Chok J. Chia , Qwai H. Low , Ramaswamy Ranganathan
发明人： Chok J. Chia , Qwai H. Low , Ramaswamy Ranganathan
IPC分类号： H01L23/367 , H01L23/373 , H01L23/522 , H01L23/552 , H01L21/44
CPC分类号： H01L23/552 , H01L23/367 , H01L23/3735 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit having a top passivation layer and bonding pads, where the improvement is a metal layer overlying all of the integrated circuit. The metal layer overlies the top passivation layer and is not in electrical contact with any of the bonding pads. In this manner, there is a structure that is added to the integrated circuit which has a relatively high thermal conductivity, and which also has a relatively high structural strength. With these two added properties, the occurrence of stress cracks, such as those induced by plastic molded packages, is reduced, and hot spots tend to be dissipated. Thus, the overlying metal layer tends to improve the reliability of the integrated circuit.
摘要翻译：具有顶部钝化层和接合焊盘的集成电路，其中改进是覆盖所有集成电路的金属层。金属层覆盖在顶部钝化层上，并且不与任何焊盘焊接。以这种方式，具有添加到具有相对较高导热性并且还具有相对较高的结构强度的集成电路的结构。通过这两个添加的性质，减少了由塑料模制包装引起的应力裂纹的发生，并且热点趋于消散。因此，上覆金属层倾向于提高集成电路的可靠性。

45. 发明授权

US06519844B1 Overmold integrated circuit package 有权
标题翻译：封装集成电路封装
公开(公告)号：US06519844B1
公开(公告)日：2003-02-18
申请号：US09940130
申请日：2001-08-27
申请人： Kumar Nagarajan , Seng Sooi Lim , Chok J. Chia
发明人： Kumar Nagarajan , Seng Sooi Lim , Chok J. Chia
IPC分类号： H05K330
CPC分类号： H01L24/32 , H01L23/13 , H01L23/3128 , H01L2224/16225 , H01L2224/27013 , H01L2224/32225 , H01L2224/73204 , H01L2224/83051 , H01L2224/83385 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/14 , H01L2924/15151 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , Y10T29/49144 , Y10T29/49146 , H01L2924/00
摘要： An integrated circuit package manufacturing process is described which reduces or eliminates the formation of voids in a molding compound between a die and an underlying substrate. The process includes providing the substrate, which has an upper surface and an air space above the upper surface. Electrically conductive vias are formed through the upper surface of the substrate which extend at least partially through the substrate, and fluid communication is provided between the vias and the overlying air space. The process includes attaching the integrated circuit die to the upper surface of the substrate over at least a portion of the vias, while leaving a gap between the die and the upper surface of the substrate. The process further includes flowing the molding compound into the gap between the die and the upper surface of the substrate while maintaining fluid communication between the vias and the air space. In this manner, air trapped between the molding compound and the upper surface of the substrate is urged to flow into the vias rather than forming a void in the molding compound. Fluid communication between the plurality of vias and the air space may be provided by not tenting the vias with a solder mask layer, or by removing any solder mask or other material which may have filled or tented over the vias during processing of the substrate.
摘要翻译：描述了一种集成电路封装制造工艺，其减少或消除了在管芯和下层衬底之间的模塑料中形成空隙。该方法包括提供在上表面上方具有上表面和空气空间的基底。导电孔通过衬底的上表面形成，其至少部分延伸通过衬底，并且在通孔和上覆空气空间之间提供流体连通。该过程包括在集成电路管芯的至少一部分通孔之上附接集成电路管芯到衬底的上表面，同时在管芯和衬底的上表面之间留下间隙。该方法还包括使模塑料流动到模具和衬底的上表面之间的间隙中，同时保持通孔和空气空间之间的流体连通。以这种方式，被迫在模塑料和衬底的上表面之间被捕获的空气被迫流入通孔，而不是在模塑料中形成空隙。多个通孔和空气空间之间的流体连通可以通过不用通孔焊接掩模层来提供，或者通过在衬底的处理期间移除可能已经填充或覆盖过孔的任何焊接掩模或其他材料来提供。

46. 发明授权

US06429534B1 Interposer tape for semiconductor package 有权
标题翻译：用于半导体封装的插入式磁带
公开(公告)号：US06429534B1
公开(公告)日：2002-08-06
申请号：US09478972
申请日：2000-01-06
申请人： Qwai H. Low , Chok J. Chia , Maniam Alagaratnam
发明人： Qwai H. Low , Chok J. Chia , Maniam Alagaratnam
IPC分类号： H01L2348
CPC分类号： H01L23/49827 , H01L23/49833 , H01L23/4985 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/05599 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/4911 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/10162 , H01L2924/14 , H01L2924/15173 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： Provided is an interposer tape which provides electrical communication between a die and a packaging substrate. The dimensions of the interposer tape may vary to accommodate a variety of die sizes for the same packaging substrate. The interposer tape includes an array of traces. A first set of wire bonds is formed between the array of traces and the die. A second set of wire bonds is formed between the array of traces and the packaging substrate.
摘要翻译：提供了一种提供管芯和封装衬底之间的电连通的插入器带。插入器带的尺寸可以变化以适应相同封装基板的各种管芯尺寸。插入器带包括一列迹线。在迹线阵列和模具之间形成第一组引线键合。在迹线阵列和封装衬底之间形成第二组线接合。

47. 发明授权

US06425179B1 Method for assembling tape ball grid arrays 有权
标题翻译：胶带球栅阵列组装方法
公开(公告)号：US06425179B1
公开(公告)日：2002-07-30
申请号：US09417255
申请日：1999-10-12
申请人： Qwai H. Low , Chok J. Chia , Ramaswamy Ranganathan
发明人： Qwai H. Low , Chok J. Chia , Ramaswamy Ranganathan
IPC分类号： H01L21/60 , H01L23/00 , H05K3/34
CPC分类号： H01L24/86 , H01L23/562 , H01L2924/01029 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/181 , Y10T29/49144 , Y10T29/49146 , Y10T29/49147 , Y10T29/49155 , H01L2924/00
摘要： According to the present invention, a method for creating a package for a semiconductor die, the package comprising a flexible tape, comprises the following steps. A support with an opening has a plurality of arms extending through at a portion of the opening. For example, for a square opening, there may be eight arms, two extending from each side of the opening. The arms preferably form a “z” shape or some other shape with a transverse component. The flexible tape is then attached to the ends of the arms within the opening such that the flexible tape is supported by the arms. A die is attached to the flexible tape, the die is preferably covered with a molding compound, and the die/flexible tape assembly is scribed from the support, thereby creating an individual package.
摘要翻译：根据本发明，一种用于制造用于半导体管芯的封装的方法，包括柔性带的封装包括以下步骤。具有开口的支撑件具有在开口的一部分延伸穿过的多个臂。例如，对于方形开口，可以有八个臂，两个从开口的每一侧延伸。臂优选地形成具有横向分量的“z”形或一些其它形状。然后将柔性带附接到开口内的臂的端部，使得柔性带由臂支撑。将模具附接到柔性带上，模具优选用模制化合物覆盖，并且模具/柔性带组件从支撑件划刻，从而形成单独的包装。

48. 发明授权

US6114189A Molded array integrated circuit package 失效
标题翻译：成型阵列集成电路封装
公开(公告)号：US6114189A
公开(公告)日：2000-09-05
申请号：US927704
申请日：1997-09-10
申请人： Chok J. Chia , Seng-Sooi Lim , Qwai H. Low
发明人： Chok J. Chia , Seng-Sooi Lim , Qwai H. Low
IPC分类号： H01L21/56 , H01L23/31 , H01L21/44
CPC分类号： H01L21/565 , H01L23/3128 , H01L2224/05599 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/85399 , H01L24/48 , H01L24/73 , H01L2924/00014 , H01L2924/01039 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181
摘要： One aspect of the invention relates to a semiconductor substrate. In one version of the invention, a semiconductor substrate includes a package substrate having first and second surfaces with conductive traces formed thereon and structures for providing electrical connection between selected conductive traces, a die attach area on the first surface of the package substrate adapted to provide physical connection to a semiconductor die, the die attach area having conductive contacts for providing electrical connection between the die and conductive traces on the first surface, a package frame, at least one substrate strap which connects the package substrate to the package frame, the substrate strap being formed integrally with the package substrate and the package frame.
摘要翻译：本发明的一个方面涉及一种半导体衬底。在本发明的一个实施例中，半导体衬底包括具有形成在其上的导电迹线的第一和第二表面的封装衬底，以及用于在所选择的导电迹线之间提供电连接的结构，适于提供包装衬底的第一表面上的管芯附着区域与半导体管芯的物理连接，管芯附接区域具有用于在管芯和第一表面上的导电迹线之间提供电连接的导电触点，封装框架，将封装衬底连接到封装框架的至少一个衬底带，衬底带子与封装基板和封装框架整体形成。

49. 发明授权

US6081997A System and method for packaging an integrated circuit using encapsulant injection 失效
标题翻译：使用密封剂注射包装集成电路的系统和方法
公开(公告)号：US6081997A
公开(公告)日：2000-07-04
申请号：US911418
申请日：1997-08-14
申请人： Chok J. Chia , Seng Sooi Lim , Maniam Alagaratnam
发明人： Chok J. Chia , Seng Sooi Lim , Maniam Alagaratnam
IPC分类号： H01L21/56 , H05K3/30
CPC分类号： H01L21/565 , H01L2224/16 , H01L2924/10253 , H01L2924/15151 , H01L2924/15311 , H01L2924/18161 , Y10T29/49121 , Y10T29/49144 , Y10T29/49146
摘要： A system and method are presented for forming a grid array device package around an integrated circuit. The integrated circuit includes multiple I/O pads on an underside surface, and an upper surface of a substrate includes a corresponding set of bonding pads. The substrate also has an opening (i.e., a hole) extending therethrough and preferably substantially in the center of the set of bonding pads. Solder bumps formed upon the I/O pads of the integrated circuit are placed in direct contact with corresponding members of the set of bonding pads, then heated until they flow in a C4 connection method. Following C4 connection of the I/O and bonding pads, the substrate and the attached integrated circuit are positioned within a mold cavity formed between two mold sections, and a liquid encapsulant material is injected through the opening of the substrate such that the encapsulant fills the mold cavity. The coupled I/O and bonding pads are enveloped by the liquid encapsulant. The liquid encapsulant is preferably a C4 underfill material. By injecting the liquid encapsulant under pressure, the amount of time required to dispense the liquid encapsulant is reduced as well as the number of voids present in the liquid encapsulant. Following at least partial curing of the encapsulant, the mold sections are separated, and the packaged semiconductor device is removed. When fully cured and hardened, the encapsulant adheres to the adjacent surfaces of the integrated circuit and the substrate, essentially interlocking the surfaces.
摘要翻译：提出了一种用于在集成电路周围形成网格阵列器件封装的系统和方法。集成电路包括在下表面上的多个I / O焊盘，并且衬底的上表面包括相应的一组焊盘。衬底还具有延伸穿过其中并且优选地基本上在该组焊盘的中心的开口（即，孔）。形成在集成电路的I / O焊盘上的焊料凸块被放置成与该组接合焊盘的相应部件直接接触，然后被加热直到它们以C4连接方式流动。在I / O和接合焊盘的C4连接之后，衬底和附接的集成电路位于形成在两个模具部分之间的模具腔内，并且通过衬底的开口注入液体密封剂材料，使得密封剂填充模腔。耦合的I / O和接合焊盘被液体密封剂包围。液体密封剂优选为C4底部填充材料。通过在压力下注入液体密封剂，减少了分配液体密封剂所需的时间以及存在于液体密封剂中的空隙数。在密封剂至少部分固化之后，分离模具部分，并且去除封装的半导体器件。当完全固化和硬化时，密封剂粘附到集成电路和基板的相邻表面，基本上使表面互锁。

50. 发明授权

US6057594A High power dissipating tape ball grid array package 失效
标题翻译：大功率消磁带球栅阵列封装
公开(公告)号：US6057594A
公开(公告)日：2000-05-02
申请号：US842379
申请日：1997-04-23
申请人： Chok J. Chia , Qwai H. Low , Maniam Alagaratnam
发明人： Chok J. Chia , Qwai H. Low , Maniam Alagaratnam
IPC分类号： H01L23/433 , H01L23/495 , H01L23/498 , H01L23/34 , H01L23/48
CPC分类号： H01L23/4334 , H01L23/49572 , H01L23/49816 , H01L2924/0002
摘要： A molded tape ball grid array package has a base structure including a heat conductive substrate and flex tape extending from opposing regions on a surface of the substrate with molded plastic material between the flex tape and the substrate. The flex tape has at least one conductive metal lead pattern which can be positioned on a side of the tape facing the substrate with a plurality of apertures exposing the conductive lead pattern from an opposing side of the tape for solder ball bonding. A semiconductor integrated circuit chip is mounted to a central portion of the substrate between the opposing regions of the flex tape with wire bonding interconnecting bond pads on the chip to the metal lead pattern. The chip and wire bonding are then encapsulated on the substrate. The structure is economical and permits high power dissipation from an integrated circuit. The molding process in fabricating the integrated circuit package is economical and readily implemented using injection molding.
摘要翻译：模制的带状球栅阵列封装具有基底结构，其包括导热基底和柔性带，该柔性带从柔性带和基底之间的模制塑料材料的表面上的相对区域延伸。柔性带具有至少一个导电金属引线图案，其可以被定位在面向基板的带的一侧，并具有多个孔，用于将导电引线图案从带的相对侧暴露以进行焊球接合。半导体集成电路芯片通过引线将芯片上的接合焊盘互连到金属引线图案，在柔性带的相对区域之间的基板的中心部分上安装。然后将芯片和引线接合封装在基板上。该结构是经济的并且允许来自集成电路的高功率耗散。在制造集成电路封装中的成型工艺是经济的，并且易于使用注塑成型。

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