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41. 发明授权

US06779163B2 Voltage island design planning 有权
公开(公告)号：US06779163B2
公开(公告)日：2004-08-17
申请号：US10065202
申请日：2002-09-25
申请人： Thomas R. Bednar , Scott W. Gould , David E. Lackey , Douglas W. Stout , Paul S. Zuchowski
发明人： Thomas R. Bednar , Scott W. Gould , David E. Lackey , Douglas W. Stout , Paul S. Zuchowski
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5068
摘要： A method and structure for designing an integrated circuit chip is disclosed. The method supplies a chip design, partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands, creates a floorplan of the voltage islands, assesses the floorplan, repeats the partitioning and the creating of the floorplan depending upon a result of the assessing process, and outputs a voltage island specification list.

42. 发明授权

US06300809B1 Double-edge-triggered flip-flop providing two data transitions per clock cycle 有权
标题翻译：双边沿触发器，每个时钟周期提供两个数据转换
公开(公告)号：US06300809B1
公开(公告)日：2001-10-09
申请号：US09616551
申请日：2000-07-14
申请人： Roger Paul Gregor , David James Hathaway , David E. Lackey , Steven Frederick Oakland
发明人： Roger Paul Gregor , David James Hathaway , David E. Lackey , Steven Frederick Oakland
IPC分类号： H03K312
CPC分类号： H03K3/012 , H03K3/037 , H03K3/0375
摘要： An apparatus comprising a clock for providing a clock signal, means for providing a delayed version of the clock signal, two transparent latches having clock inputs controlled by opposite polarities of the delayed clock signal, a multiplexer having (i) inputs fed by outputs of the latches, and (ii) a select input fed by the clock signal, and means for providing a select signal for selecting the latch whose clock is inactive. Preferably, each of the latches has a scan input gate and a scan output gate, and the scan output of the first latch is applied to the scan input of the second latch to form a scannable latch pair. Also, preferably, the apparatus further comprises a data port for applying data to the first and second latches, and an exclusive OR gate at the data port, whereby the apparatus produces a gated clock signal. Also disclosed is a method of operating this apparatus.
摘要翻译：一种包括用于提供时钟信号的时钟的装置，用于提供时钟信号的延迟版本的装置，具有由延迟的时钟信号的相反极性控制的时钟输入的两个透明锁存器，多路复用器具有（i）由锁存器和（ii）由时钟信号馈送的选择输入，以及用于提供用于选择时钟不活动的锁存器的选择信号的装置。优选地，每个锁存器具有扫描输入栅极和扫描输出栅极，并且第一锁存器的扫描输出被施加到第二锁存器的扫描输入以形成可扫描锁存器对。此外，优选地，该装置还包括用于将数据应用于第一和第二锁存器的数据端口和数据端口处的异或门，由此该装置产生门控时钟信号。还公开了一种操作该装置的方法。

43. 发明授权

US5146460A Logic simulation using a hardware accelerator together with an automated error event isolation and trace facility 失效
标题翻译：使用硬件加速器与自动错误事件隔离和跟踪设备进行逻辑仿真
公开(公告)号：US5146460A
公开(公告)日：1992-09-08
申请号：US481145
申请日：1990-02-16
申请人： Dennis F. Ackerman , David R. Bender , Salina S. Chu , George R. Deibert , Gary G. Hallock , David E. Lackey , Robert G. Sheldon , Thomas A. Stranko
发明人： Dennis F. Ackerman , David R. Bender , Salina S. Chu , George R. Deibert , Gary G. Hallock , David E. Lackey , Robert G. Sheldon , Thomas A. Stranko
IPC分类号： G06F11/25 , G06F11/26 , G06F11/34 , G06F17/50
CPC分类号： G06F17/5022 , G06F11/261 , G06F11/34
摘要： Software simulators of logic design circuits run slowly but are capable of providing very finely detailed error trace analyses. On the other hand, hardware accelerators operating to perform similar functions are very fast in their execution but are not capable of practically isolating error states or other critical conditions. Accordingly, the present invention provides an interactive system combining software simulators and hardware accelerators so that when desired test results do not favorably compare with simulated results, a mechanism is provided for storing the current hardware accelerator state and restoring the accelerator to a previous checkpoint state which has been saved as a result of a prior periodic interruption. The hardware accelerator is then operated for a time sufficient to bring it up to a state that occurs just before the detected miscomparison. At this point, state information from the hardware accelerator is supplied to a software simulator for detailed error analysis and fault tracing. The hardware accelerator may then be restarted where it left off or with a different task. In this way, optimal utilization is made of expensive hardware accelerator resources while nonetheless providing error event isolation and the ability to generate detailed traces of the simulated behavior.

44. 发明授权

US08205124B2 Microcontroller for logic built-in self test (LBIST) 有权
标题翻译：用于逻辑的微控制器内置自检（LBIST）
公开(公告)号：US08205124B2
公开(公告)日：2012-06-19
申请号：US12268583
申请日：2008-11-11
申请人： Gary D. Grise , David E. Lackey , Steven F. Oakland , Donald L. Wheater
发明人： Gary D. Grise , David E. Lackey , Steven F. Oakland , Donald L. Wheater
IPC分类号： G01R31/28
CPC分类号： G01R31/31724 , G01R31/31727
摘要： Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches adapted to store a plurality of values corresponding to a behavioral profile of a test clock.
摘要翻译：内置自检（BIST）微控制器集成电路，适用于逻辑验证。微控制器包括表示微控制器的分层描述的多个硬件描述语言文件，所述多个硬件描述语言文件包括电路设计元素库，多个库设计电路元件，适于存储唯一定义的输入和输出集合用于启用逻辑BIST的信号，以及适于存储对应于测试时钟的行为轮廓的多个值的多个锁存器。

45. 发明授权

US08122409B2 Method and device for selectively adding timing margin in an integrated circuit 有权
标题翻译：用于在集成电路中选择性地添加定时裕度的方法和装置
公开(公告)号：US08122409B2
公开(公告)日：2012-02-21
申请号：US11869306
申请日：2007-10-09
申请人： David E. Lackey , Chandramouli Visweswariah , Paul S. Zuchowski
发明人： David E. Lackey , Chandramouli Visweswariah , Paul S. Zuchowski
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031 , G01R31/318307 , G01R31/318364
摘要： A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested “at speed” during manufacturing test, running statistical timing to calculate a margin to be applied to the paths, updating design specifications for margin to be applied to the paths, and optimizing chip logic based on updated design specifications.
摘要翻译：一种方法，系统和集成电路，包括选择性地添加定时裕度。用于集成统计时序和自动测试模式生成（ATPG）以在集成电路中选择性地添加时序裕度的方法包括在芯片设计时识别在制造测试期间“以速度”无法被鲁棒测试的路径，运行统计计时，计算要应用于路径的余量，更新要应用于路径的余量的设计规范，以及基于更新的设计规范优化芯片逻辑。

46. 发明授权

US08117579B2 LSSD compatibility for GSD unified global clock buffers 有权
标题翻译： LSSD兼容GSD统一全局时钟缓冲区
公开(公告)号：US08117579B2
公开(公告)日：2012-02-14
申请号：US12023337
申请日：2008-01-31
申请人： James Douglas Warnock , Wendel Dieter , David E. Lackey , William Vincent Huott , Leon Jacob Sigal , Louis Bernard Bushard , Sang Hoo Dhong
发明人： James Douglas Warnock , Wendel Dieter , David E. Lackey , William Vincent Huott , Leon Jacob Sigal , Louis Bernard Bushard , Sang Hoo Dhong
IPC分类号： G06F17/50
CPC分类号： G01R31/318594 , G01R31/318552
摘要： A method, system and program are provided for generating level sensitive scan design (LSSD) clock signals from a general scan design (GSD) clock buffer using an intermediate clock signal and one or more first mode control signals to generate a plurality of LSSD clock signals from an output section of the GSD clock buffer that receives the intermediate clock signal and the first mode control signal(s), where the GSD clock buffer is also configured to generate a plurality of GSD clock signals in response to receiving a GSD mode, generating an intermediate clock signal from the input section of the GSD clock buffer in response receiving a GSD mode signal.
摘要翻译：提供了一种方法，系统和程序，用于使用中间时钟信号和一个或多个第一模式控制信号从一般扫描设计（GSD）时钟缓冲器产生电平敏感扫描设计（LSSD）时钟信号，以产生多个LSSD时钟信号从GSD时钟缓冲器的输出部分接收中间时钟信号和第一模式控制信号，其中GSD时钟缓冲器还被配置为响应于接收到GSD模式产生多个GSD时钟信号，产生来自GSD时钟缓冲器的输入部分的中间时钟信号响应于接收GSD模式信号。

47. 发明申请

US20110066904A1 AVOIDING RACE CONDITIONS AT CLOCK DOMAIN CROSSINGS IN AN EDGE BASED SCAN DESIGN 有权
标题翻译：在基于边缘扫描设计的时钟域交叉处避开条件
公开(公告)号：US20110066904A1
公开(公告)日：2011-03-17
申请号：US12557623
申请日：2009-09-11
申请人： David E. Lackey
发明人： David E. Lackey
IPC分类号： G01R31/28
CPC分类号： G01R31/318594
摘要： A structure, system, and method block clock inputs to clock domains (using a computer). While the clock domain inputs are blocked, the structure, system, and method perform a first timing test only of signals that are transmitted within the clock domains (using the computer) by only observing latches that receive signals from sources within the clock domains. The structure, system, and method also unblock the clock inputs to the clock domains (using the computer). While the clock domain inputs are unblocked, the structure, system, and method perform a second timing test only of signals that are transmitted between the clock domains by only observing latches that receive signals from other clock domains.
摘要翻译：一种结构，系统和方法将时钟域的时钟输入（使用计算机）。当时钟域输入被阻塞时，结构，系统和方法仅通过仅观察从时钟域内的源接收信号的锁存器来执行在时钟域（使用计算机）内发送的信号的第一定时测试。结构，系统和方法还可以解除对时钟域的时钟输入（使用计算机）。当时钟域输入被解除阻塞时，结构，系统和方法仅通过仅观察从其它时钟域接收信号的锁存器来执行在时钟域之间传输的信号的第二定时测试。

48. 发明申请

US20110055650A1 Hold Transition Fault Model and Test Generation Method 有权
标题翻译：保持过渡故障模型和测试生成方法
公开(公告)号：US20110055650A1
公开(公告)日：2011-03-03
申请号：US12548977
申请日：2009-08-27
申请人： Vikram Iyengar , Pamela S. Gillis , David E. Lackey , Steven F. Oakland
发明人： Vikram Iyengar , Pamela S. Gillis , David E. Lackey , Steven F. Oakland
IPC分类号： G06F11/263 , G01R31/28
CPC分类号： G01R31/318357 , G01R31/318328
摘要： A method of hold fault modeling and test generation. The method includes first modeling a fast-to-rise and a fast-to-fall hold fault for a plurality of circuit nets. Testing a fast-to-rise hold fault is accomplished by: setting up a logic value on each of the plurality of circuit nodes to 0; transitioning each of the plurality of circuit nodes from 0 to 1 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 0 to 1. Testing a fast-to-fall hold is accomplished by: setting up a logic value on each of the plurality circuit nodes to 1; transitioning each of the plurality of circuit nodes from 1 to 0 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 1 to 0.
摘要翻译：一种保持故障建模和测试生成的方法。该方法包括首先建模多个电路网络的快速上升和快速降档保持故障。测试快速上升保持故障通过以下方式实现：将多个电路节点中的每一个上的逻辑值设置为0; 使用单个时钟脉冲将多个电路节点中的每一个从0转换到1; 以及确定至少一个下游节点是否被从0变为1的不期望的影响。通过以下方式来实现快速降档保持：通过在多个电路节点中的每一个上设置逻辑值到1; 使用单个时钟脉冲将多个电路节点中的每一个从1转换到0; 以及确定至少一个下游节点是否被从1到0的过渡中无意地影响。

49. 发明授权

US07721170B2 Apparatus and method for selectively implementing launch off scan capability in at speed testing 失效
标题翻译：用于在速度测试中选择性地实施发射扫描能力的装置和方法
公开(公告)号：US07721170B2
公开(公告)日：2010-05-18
申请号：US11874972
申请日：2007-10-19
申请人： Gary D. Grise , Vikram Iyengar , David E. Lackey , Mark R. Taylor
发明人： Gary D. Grise , Vikram Iyengar , David E. Lackey , Mark R. Taylor
IPC分类号： G01R31/28
CPC分类号： G01R31/318594 , G01R31/318541
摘要： An apparatus for selectively implementing launch-off-scan capability in at-speed testing of integrated circuit devices includes a control device configured to selectively disable a master clock signal of a latch structure under test such that a pulse sequence of a system clock signal results in a slave-master-slave clock pulse sequence in the latch structure under test; wherein the control device utilizes the system clock signal as an input thereto and operates in a self-resetting fashion that is timing independent with respect to a scan chain.
摘要翻译：一种用于在集成电路装置的高速测试中选择性地实施发射扫描能力的装置包括控制装置，其被配置为选择性地禁用被测闩锁结构的主时钟信号，使得系统时钟信号的脉冲序列导致被锁存结构中的从主从主时钟脉冲序列; 其中所述控制装置利用所述系统时钟信号作为其输入，并以相对于扫描链定时无关的自复位方式操作。

50. 发明申请

US20090055696A1 MICROCONTROLLER FOR LOGIC BUILT-IN SELF TEST (LBIST) 有权
标题翻译：用于逻辑内置自检的微控制器（LBIST）
公开(公告)号：US20090055696A1
公开(公告)日：2009-02-26
申请号：US12268583
申请日：2008-11-11
申请人： Gary D. Grise , David E. Lackey , Steven F. Oakland , Donald L. Wheater
发明人： Gary D. Grise , David E. Lackey , Steven F. Oakland , Donald L. Wheater
IPC分类号： G01R31/3177 , G01R31/319 , G01R31/3187 , G06F11/07
CPC分类号： G01R31/31724 , G01R31/31727
摘要： Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches adapted to store a plurality of values corresponding to a behavioral profile of a test clock.
摘要翻译：内置自检（BIST）微控制器集成电路，适用于逻辑验证。微控制器包括表示微控制器的分层描述的多个硬件描述语言文件，所述多个硬件描述语言文件包括电路设计元素库，多个库设计电路元件，适于存储唯一定义的输入和输出集合用于启用逻辑BIST的信号，以及适于存储对应于测试时钟的行为轮廓的多个值的多个锁存器。

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