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1. 发明授权

US08181135B2 Hold transition fault model and test generation method 有权
标题翻译：保持转换故障模型和测试生成方法
公开(公告)号：US08181135B2
公开(公告)日：2012-05-15
申请号：US12548977
申请日：2009-08-27
申请人： Vikram Iyengar , Pamela S. Gillis , David E. Lackey , Steven F. Oakland
发明人： Vikram Iyengar , Pamela S. Gillis , David E. Lackey , Steven F. Oakland
IPC分类号： G06F17/50
CPC分类号： G01R31/318357 , G01R31/318328
摘要： A method of hold fault modeling and test generation. The method includes first modeling a fast-to-rise and a fast-to-fall hold fault for a plurality of circuit nets. Testing a fast-to-rise hold fault is accomplished by: setting up a logic value on each of the plurality of circuit nodes to 0; transitioning each of the plurality of circuit nodes from 0 to 1 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 0 to 1. Testing a fast-to-fall hold is accomplished by: setting up a logic value on each of the plurality circuit nodes to 1; transitioning each of the plurality of circuit nodes from 1 to 0 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 1 to 0.
摘要翻译：一种保持故障建模和测试生成的方法。该方法包括首先建模多个电路网络的快速上升和快速降档保持故障。测试快速上升保持故障通过以下方式实现：将多个电路节点中的每一个上的逻辑值设置为0; 使用单个时钟脉冲将多个电路节点中的每一个从0转换到1; 以及确定至少一个下游节点是否被从0变为1的不期望的影响。通过以下方式来实现快速降档保持：通过在多个电路节点中的每一个上设置逻辑值到1; 使用单个时钟脉冲将多个电路节点中的每一个从1转换到0; 以及确定至少一个下游节点是否被从1到0的过渡中无意地影响。

2. 发明申请

US20110055650A1 Hold Transition Fault Model and Test Generation Method 有权
标题翻译：保持过渡故障模型和测试生成方法
公开(公告)号：US20110055650A1
公开(公告)日：2011-03-03
申请号：US12548977
申请日：2009-08-27
申请人： Vikram Iyengar , Pamela S. Gillis , David E. Lackey , Steven F. Oakland
发明人： Vikram Iyengar , Pamela S. Gillis , David E. Lackey , Steven F. Oakland
IPC分类号： G06F11/263 , G01R31/28
CPC分类号： G01R31/318357 , G01R31/318328
摘要： A method of hold fault modeling and test generation. The method includes first modeling a fast-to-rise and a fast-to-fall hold fault for a plurality of circuit nets. Testing a fast-to-rise hold fault is accomplished by: setting up a logic value on each of the plurality of circuit nodes to 0; transitioning each of the plurality of circuit nodes from 0 to 1 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 0 to 1. Testing a fast-to-fall hold is accomplished by: setting up a logic value on each of the plurality circuit nodes to 1; transitioning each of the plurality of circuit nodes from 1 to 0 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 1 to 0.
摘要翻译：一种保持故障建模和测试生成的方法。该方法包括首先建模多个电路网络的快速上升和快速降档保持故障。测试快速上升保持故障通过以下方式实现：将多个电路节点中的每一个上的逻辑值设置为0; 使用单个时钟脉冲将多个电路节点中的每一个从0转换到1; 以及确定至少一个下游节点是否被从0变为1的不期望的影响。通过以下方式来实现快速降档保持：通过在多个电路节点中的每一个上设置逻辑值到1; 使用单个时钟脉冲将多个电路节点中的每一个从1转换到0; 以及确定至少一个下游节点是否被从1到0的过渡中无意地影响。

3. 发明申请

US20110154141A1 METHOD TO TEST HOLD PATH FAULTS USING FUNCTIONAL CLOCKING 失效
标题翻译：使用功能时钟测试保持路径故障的方法
公开(公告)号：US20110154141A1
公开(公告)日：2011-06-23
申请号：US12641456
申请日：2009-12-18
申请人： Pamela S. Gillis , Vikram Iyengar , Steven F. Oakland
发明人： Pamela S. Gillis , Vikram Iyengar , Steven F. Oakland
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31858 , G01R31/31725
摘要： A system and method for detecting hold path faults in an integrated circuit is provided in exemplary embodiments. These exemplary embodiments introduce a method of identifying data paths within an integrated circuit with statistically the highest timing slack among the data paths within the integrated circuit that cover the entire process space of the circuit. By identifying these paths (i.e., shortest data paths), a robust test pattern can be generated that directly tests for hold path faults on short data paths within the integrated circuit using one functional clock pulse.
摘要翻译：在示例性实施例中提供了用于检测集成电路中的保持路径故障的系统和方法。这些示例性实施例引入了一种识别集成电路内的数据路径的方法，统计上覆盖电路的整个处理空间的集成电路内的数据路径中的最高定时松弛。通过识别这些路径（即，最短数据路径），可以生成鲁棒的测试模式，其使用一个功能时钟脉冲直接测试集成电路内的短数据路径上的保持路径故障。

4. 发明授权

US08230283B2 Method to test hold path faults using functional clocking 失效
标题翻译：使用功能时钟测试保持路径故障的方法
公开(公告)号：US08230283B2
公开(公告)日：2012-07-24
申请号：US12641456
申请日：2009-12-18
申请人： Pamela S. Gillis , Vikram Iyengar , Steven F. Oakland
发明人： Pamela S. Gillis , Vikram Iyengar , Steven F. Oakland
IPC分类号： G01R31/28
CPC分类号： G01R31/31858 , G01R31/31725
摘要： A system and method for detecting hold path faults in an integrated circuit is provided in exemplary embodiments. These exemplary embodiments introduce a method of identifying data paths within an integrated circuit with statistically the highest timing slack among the data paths within the integrated circuit that cover the entire process space of the circuit. By identifying these paths (i.e., shortest data paths), a robust test pattern can be generated that directly tests for hold path faults on short data paths within the integrated circuit using one functional clock pulse.
摘要翻译：在示例性实施例中提供了用于检测集成电路中的保持路径故障的系统和方法。这些示例性实施例引入了一种识别集成电路内的数据路径的方法，统计上覆盖电路的整个处理空间的集成电路内的数据路径中的最高定时松弛。通过识别这些路径（即，最短数据路径），可以生成鲁棒的测试模式，其使用一个功能时钟脉冲直接测试集成电路内的短数据路径上的保持路径故障。

5. 发明授权

US08423844B2 Dense register array for enabling scan out observation of both L1 and L2 latches 有权
标题翻译：密码寄存器阵列，用于扫描L1和L2锁存器的观察
公开(公告)号：US08423844B2
公开(公告)日：2013-04-16
申请号：US13004104
申请日：2011-01-11
申请人： Pamela S. Gillis , David E. Lackey , Steven F. Oakland , Jeffery H. Oppold
发明人： Pamela S. Gillis , David E. Lackey , Steven F. Oakland , Jeffery H. Oppold
IPC分类号： G01R31/28
CPC分类号： G01R31/318541
摘要： A scannable register array structure includes a plurality of individual latches, each configured to hold one bit of array data in a normal mode of operation. The plurality of individual latches operate in scannable latch pairs in a test mode of operation, with first latches of the scannable latch pairs comprising L1 latches and second latches of the scannable latch pairs comprising L2 latches. A test clock signal generates a first clock pulse signal, A, for the L1 latches and a second clock pulse signal, B, for the L2 latches. The L2 latches are further configured to selectively receive L1 data therein upon a separate activation of the B clock signal, independent of the test clock signal, such that a scan out operation of the individual latches results in observation of L1 latch data.
摘要翻译：可扫描寄存器阵列结构包括多个单独锁存器，每个锁存器被配置为在正常操作模式下保持一位数组数组。多个单独的锁存器在测试操作模式下以可扫描的锁存器对操作，可扫描锁存器对的第一锁存器包括包括L2锁存器的可扫描锁存器对的L1锁存器和第二锁存器。测试时钟信号为L1锁存器产生第一时钟脉冲信号A，为L2锁存器产生第二时钟脉冲信号B。 L2锁存器还被配置为在独立于测试时钟信号的B时钟信号的单独激活之后有选择地接收L1数据，使得各个锁存器的扫描输出操作导致观察L1锁存器数据。

6. 发明申请

US20120179944A1 DENSE REGISTER ARRAY FOR ENABLING SCAN OUT OBSERVATION OF BOTH L1 AND L2 LATCHES 有权
标题翻译： DENSE寄存器阵列用于启用两个L1和L2锁存器的扫描
公开(公告)号：US20120179944A1
公开(公告)日：2012-07-12
申请号：US13004104
申请日：2011-01-11
申请人： Pamela S. Gillis , David E. Lackey , Steven F. Oakland , Jeffery H. Oppold
发明人： Pamela S. Gillis , David E. Lackey , Steven F. Oakland , Jeffery H. Oppold
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318541
摘要： A scannable register array structure includes a plurality of individual latches, each configured to hold one bit of array data in a normal mode of operation. The plurality of individual latches operate in scannable latch pairs in a test mode of operation, with first latches of the scannable latch pairs comprising L1 latches and second latches of the scannable latch pairs comprising L2 latches. A test clock signal generates a first clock pulse signal, A, for the L1 latches and a second clock pulse signal, B, for the L2 latches. The L2 latches are further configured to selectively receive L1 data therein upon a separate activation of the B clock signal, independent of the test clock signal, such that a scan out operation of the individual latches results in observation of L1 latch data.
摘要翻译：可扫描寄存器阵列结构包括多个单独锁存器，每个锁存器被配置为在正常操作模式下保持一位数组数组。多个单独锁存器在测试操作模式下在可扫描锁存器对中操作，可扫描锁存器对的第一锁存器包括包括L2锁存器的可扫描锁存器对的L1锁存器和第二锁存器。测试时钟信号为L1锁存器产生第一时钟脉冲信号A，为L2锁存器产生第二时钟脉冲信号B。 L2锁存器还被配置为在独立于测试时钟信号的B时钟信号的单独激活之后有选择地接收L1数据，使得各个锁存器的扫描输出操作导致观察L1锁存器数据。

7. 发明授权

US06656751B2 Self test method and device for dynamic voltage screen functionality improvement 失效
标题翻译：用于动态电压屏幕功能改进的自检方法和装置
公开(公告)号：US06656751B2
公开(公告)日：2003-12-02
申请号：US09683050
申请日：2001-11-13
申请人： John E. Andersen , Bruce M. Cowan , Pamela S. Gillis , Steven F. Oakland , Michael R. Ouellette
发明人： John E. Andersen , Bruce M. Cowan , Pamela S. Gillis , Steven F. Oakland , Michael R. Ouellette
IPC分类号： H01L2100
CPC分类号： G11C29/12015 , G01R31/31724 , G01R31/3187 , G11C29/14 , H03K5/135
摘要： Disclosed is a device that includes a built-in-self-test controller having a mechanism for providing an interface signal that indicates whether a dynamic voltage screen (DVS) test is being performed. The self-test controller is associated with a memory array that includes a clock having a clock speed. The memory array also includes a clock adjuster that receives the interface signal and reduces the clock speed when the interface signal indicates that a DVS test is being performed.
摘要翻译：公开了一种包括内置自检控制器的装置，其具有用于提供指示是否正在执行动态电压屏幕（DVS）测试的接口信号的机制。自检控制器与包括具有时钟速度的时钟的存储器阵列相关联。存储器阵列还包括时钟调节器，当接口信号指示正在执行DVS测试时，时钟调节器接收接口信号并降低时钟速度。

8. 发明授权

US07281182B2 Method and circuit using boundary scan cells for design library analysis 有权
标题翻译：使用边界扫描单元的方法和电路进行设计库分析
公开(公告)号：US07281182B2
公开(公告)日：2007-10-09
申请号：US10906481
申请日：2005-02-22
申请人： Pamela S. Gillis , David D. Litten , Steven F. Oakland
发明人： Pamela S. Gillis , David D. Litten , Steven F. Oakland
IPC分类号： G01R31/28
CPC分类号： G01R31/2882 , G01R31/2853
摘要： A boundary scan register circuit and a method of characterization testing. The boundary scan register circuit, including: a multiplicity of boundary scan cells connected in series, each boundary scan cell having a latch; means for isolating the boundary scan cells into one or more boundary scan segments, each boundary scan segment containing a different set of the boundary scan cells; and means for characterizing signal propagation through each boundary scan segment.
摘要翻译：边界扫描寄存器电路和表征测试方法。边界扫描寄存器电路包括：多个边界扫描单元串联连接，每个边界扫描单元具有锁存器; 用于将边界扫描单元隔离成一个或多个边界扫描段的装置，每个边界扫描段包含不同的边界扫描单元组; 以及用于表征通过每个边界扫描段的信号传播的装置。

9. 发明授权

US06768694B2 Method of electrically blowing fuses under control of an on-chip tester interface apparatus 有权
标题翻译：在片上测试仪接口装置的控制下电熔熔丝的方法
公开(公告)号：US06768694B2
公开(公告)日：2004-07-27
申请号：US10265591
申请日：2002-10-07
申请人： Darren L. Anand , Bruce Cowan , L. Owen Farnsworth, III , Pamela S. Gillis , Peter O. Jakobsen , Krishnendu Mondal , Steven F. Oakland , Michael R. Ouellette , Donald L. Wheater
发明人： Darren L. Anand , Bruce Cowan , L. Owen Farnsworth, III , Pamela S. Gillis , Peter O. Jakobsen , Krishnendu Mondal , Steven F. Oakland , Michael R. Ouellette , Donald L. Wheater
IPC分类号： G11C700
CPC分类号： G11C29/027 , G11C17/18 , G11C29/56 , G11C29/785 , G11C2029/1208
摘要： A chip repair system designed for automated test equipment independent application on many unique very dense ASIC devices in a high turnover environment is disclosed. During test, the system will control on chip built-in self-test (BIST) engines collect and compress repair data, program fuses and finally decompress and reload the repair data for post fuse testing. In end use application this system decompresses and loads the repair data at power-up or at the request of the system.
摘要翻译：公开了一种芯片修复系统，专为自动化测试设备而独立应用于许多独特的非常密集的ASIC设备，在高周转环境中。在测试期间，系统将控制芯片内置的自检（BIST）引擎收集和压缩修复数据，程序保险丝，并最终解压缩并重新加载后保险丝测试的修复数据。在最终使用应用程序中，该系统在上电时或在系统请求下解压缩加载修复数据。

10. 发明授权

US08423847B2 Microcontroller for logic built-in self test (LBIST) 有权
公开(公告)号：US08423847B2
公开(公告)日：2013-04-16
申请号：US13469604
申请日：2012-05-11
申请人： Gary D. Grise , David E. Lackey , Steven F. Oakland , Donald L. Wheater
发明人： Gary D. Grise , David E. Lackey , Steven F. Oakland , Donald L. Wheater
IPC分类号： G01R31/28
CPC分类号： G01R31/31724 , G01R31/31727
摘要： Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches adapted to store a plurality of values corresponding to a behavioral profile of a test clock.

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