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1. 发明申请

US20090106608A1 APPARATUS AND METHOD FOR SELECTIVELY IMPLEMENTING LAUNCH OFF SCAN CAPABILITY IN AT SPEED TESTING 失效
标题翻译：在速度测试中选择实现启动扫描能力的装置和方法
公开(公告)号：US20090106608A1
公开(公告)日：2009-04-23
申请号：US11874972
申请日：2007-10-19
申请人： Gary D. Grise , Vikram Iyengar , David E. Lackey , Mark R. Taylor
发明人： Gary D. Grise , Vikram Iyengar , David E. Lackey , Mark R. Taylor
IPC分类号： G01R31/28
CPC分类号： G01R31/318594 , G01R31/318541
摘要： An apparatus for selectively implementing launch-off-scan capability in at-speed testing of integrated circuit devices includes a control device configured to selectively disable a master clock signal of a latch structure under test such that a pulse sequence of a system clock signal results in a slave-master-slave clock pulse sequence in the latch structure under test; wherein the control device utilizes the system clock signal as an input thereto and operates in a self-resetting fashion that is timing independent with respect to a scan chain.
摘要翻译：一种用于在集成电路装置的高速测试中选择性地实施发射扫描能力的装置包括控制装置，其被配置为选择性地禁用被测闩锁结构的主时钟信号，使得系统时钟信号的脉冲序列导致被锁存结构中的从主从主时钟脉冲序列; 其中所述控制装置利用所述系统时钟信号作为其输入，并以相对于扫描链定时无关的自复位方式操作。

2. 发明授权

US07721170B2 Apparatus and method for selectively implementing launch off scan capability in at speed testing 失效
标题翻译：用于在速度测试中选择性地实施发射扫描能力的装置和方法
公开(公告)号：US07721170B2
公开(公告)日：2010-05-18
申请号：US11874972
申请日：2007-10-19
申请人： Gary D. Grise , Vikram Iyengar , David E. Lackey , Mark R. Taylor
发明人： Gary D. Grise , Vikram Iyengar , David E. Lackey , Mark R. Taylor
IPC分类号： G01R31/28
CPC分类号： G01R31/318594 , G01R31/318541
摘要： An apparatus for selectively implementing launch-off-scan capability in at-speed testing of integrated circuit devices includes a control device configured to selectively disable a master clock signal of a latch structure under test such that a pulse sequence of a system clock signal results in a slave-master-slave clock pulse sequence in the latch structure under test; wherein the control device utilizes the system clock signal as an input thereto and operates in a self-resetting fashion that is timing independent with respect to a scan chain.
摘要翻译：一种用于在集成电路装置的高速测试中选择性地实施发射扫描能力的装置包括控制装置，其被配置为选择性地禁用被测闩锁结构的主时钟信号，使得系统时钟信号的脉冲序列导致被锁存结构中的从主从主时钟脉冲序列; 其中所述控制装置利用所述系统时钟信号作为其输入，并以相对于扫描链定时无关的自复位方式操作。

3. 发明授权

US07620921B2 IC chip at-functional-speed testing with process coverage evaluation 有权
标题翻译： IC芯片在功能速度测试与过程覆盖评估
公开(公告)号：US07620921B2
公开(公告)日：2009-11-17
申请号：US11741164
申请日：2007-04-27
申请人： Eric A. Foreman , Gary D. Grise , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Eric A. Foreman , Gary D. Grise , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/10
摘要： Methods, systems and program products for evaluating an IC chip are disclosed. In one embodiment, the method includes running a statistical static timing analysis (SSTA) of a full IC chip design; creating at-functional-speed test (AFST) robust paths for an IC chip, the created robust paths representing a non-comprehensive list of AFST robust paths for the IC chip; and re-running the SSTA with the SSTA delay model setup based on the created robust paths. A process coverage is calculated for evaluation from the SSTA runnings; and a particular IC chip is evaluated based on the process coverage.
摘要翻译：公开了用于评估IC芯片的方法，系统和程序产品。在一个实施例中，该方法包括运行全IC芯片设计的统计静态时序分析（SSTA）; 创建用于IC芯片的功能速度测试（AFST）鲁棒路径，所创建的鲁棒路径表示IC芯片的AFST鲁棒路径的非全面列表; 并基于创建的鲁棒路径，使用SSTA延迟模型设置重新运行SSTA。计算过程覆盖率用于从SSTA运行中进行评估; 并且基于处理覆盖来评估特定的IC芯片。

4. 发明申请

US20090265677A1 INTEGRATED TEST WAVEFORM GENERATOR (TWG) AND CUSTOMER WAVEFORM GENERATOR (CWG), DESIGN STRUCTURE AND METHOD 有权
标题翻译：集成测试波形发生器（TWG）和客户波形发生器（CWG），设计结构和方法
公开(公告)号：US20090265677A1
公开(公告)日：2009-10-22
申请号：US12104461
申请日：2008-04-17
申请人： Gary D. Grise , Vikram Iyengar , David E. Lackey , David W. Milton
发明人： Gary D. Grise , Vikram Iyengar , David E. Lackey , David W. Milton
IPC分类号： H03K5/156 , G06F1/10 , G06F17/50
CPC分类号： G06F17/505 , G06F1/10 , G06F2217/62 , H03K5/156
摘要： Disclosed are embodiments of a clock generation circuit, a design structure for the circuit and an associated method that provide deskewing functions and that further provide precise timing for both testing and functional operations. Specifically, the embodiments incorporate a deskewer circuit that is capable of receiving waveform signals from both an external waveform generator and an internal waveform generator. The external waveform generator can generate and supply to the deskewer circuit a pair of waveform signals for functional operations. The internal waveform generator can be uniquely configured with control logic and counter logic for generating and supplying a pair of waveform signals to the deskewer circuit for any one of built-in self-test (BIST) operations, macro-test operations, other test operations or functional operations. The deskewer circuit can selectively gate an input clock signal with the waveform signals from either the external or internal waveform generator in order to generate the required output clock signal.
摘要翻译：公开了时钟发生电路的实施例，用于电路的设计结构和相关联的方法，其提供了偏移功能，并进一步为测试和功能操作提供精确的定时。具体地说，这些实施例结合了能够从外部波形发生器和内部波形发生器接收波形信号的偏移电路。外部波形发生器可以生成和提供一个用于功能操作的波形信号。内部波形发生器可以独特地配置控制逻辑和计数器逻辑，用于为内置自检（BIST）操作，宏测试操作，其他测试操作中的任何一个生成和提供一对波形信号到电路板电路或功能操作。该偏移电路可以使用来自外部或内部波形发生器的波形信号选择性地输入输入时钟信号，以便产生所需的输出时钟信号。

5. 发明申请

US20080270953A1 IC CHIP AT-FUNCTIONAL-SPEED TESTING WITH PROCESS COVERAGE EVALUATION 有权
标题翻译： IC芯片功能快速测试与过程覆盖评估
公开(公告)号：US20080270953A1
公开(公告)日：2008-10-30
申请号：US11741164
申请日：2007-04-27
申请人： Eric A. Foreman , Gary D. Grise , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Eric A. Foreman , Gary D. Grise , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/10
摘要： Methods, systems and program products for evaluating an IC chip are disclosed. In one embodiment, the method includes running a statistical static timing analysis (SSTA) of a full IC chip design; creating at-functional-speed test (AFST) robust paths for an IC chip, the created robust paths representing a non-comprehensive list of AFST robust paths for the IC chip; and re-running the SSTA with the SSTA delay model setup based on the created robust paths. A process coverage is calculated for evaluation from the SSTA runnings; and a particular IC chip is evaluated based on the process coverage.
摘要翻译：公开了用于评估IC芯片的方法，系统和程序产品。在一个实施例中，该方法包括运行全IC芯片设计的统计静态时序分析（SSTA）; 创建用于IC芯片的功能速度测试（AFST）鲁棒路径，所创建的鲁棒路径表示IC芯片的AFST鲁棒路径的非全面列表; 并基于创建的鲁棒路径，使用SSTA延迟模型设置重新运行SSTA。计算过程覆盖率用于从SSTA运行中进行评估; 并且基于处理覆盖来评估特定的IC芯片。

6. 发明申请

US20090119629A1 SYSTEM AND METHOD FOR GENERATING AT-SPEED STRUCTURAL TESTS TO IMPROVE PROCESS AND ENVIRONMENTAL PARAMETER SPACE COVERAGE 有权
标题翻译：用于产生速度快速结构测试以改进过程和环境参数空间覆盖的系统和方法
公开(公告)号：US20090119629A1
公开(公告)日：2009-05-07
申请号：US11934146
申请日：2007-11-02
申请人： Gary D. Grise , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Chandramouli Visweswariah , Vladimir Zolotov
发明人： Gary D. Grise , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F11/24 , G01R31/31835
摘要： A system for enhancing the practicability of at-speed structural testing (ASST). In one embodiment, the system includes first means for performing statistical timing analysis on a design of logic circuitry. A second means performs a criticality analysis on the logic circuitry as a function of the statistical timing analysis so as to determine a criticality probability for each node of the logic circuitry. A third means selects nodes of the logic circuitry as a function of the criticality analysis. A fourth means selects timing paths as a function of the criticality probabilities of the selected nodes. A fifth means generates an ASST pattern for each of the selected timing paths. A sixth mean is provided to perform ASST on a fabricated instantiation of the design at functional speed using the generated ASST pattern.
摘要翻译：一种提高高速结构测试（ASST）实用性的系统。在一个实施例中，系统包括用于对逻辑电路的设计执行统计时序分析的第一装置。第二种方法是根据统计时序分析对逻辑电路执行关键性分析，以确定逻辑电路的每个节点的临界概率。第三种方法是选择逻辑电路的节点作为关键性分析的函数。第四种装置根据所选节点的临界概率来选择定时路径。第五装置为每个所选定时路径生成ASST模式。提供了第六个平均值，以使用所生成的ASST模式在功能速度上对制造的设计实例化执行ASST。

7. 发明授权

US07996807B2 Integrated test waveform generator (TWG) and customer waveform generator (CWG), design structure and method 有权
标题翻译：集成测试波形发生器（TWG）和客户波形发生器（CWG），设计结构和方法
公开(公告)号：US07996807B2
公开(公告)日：2011-08-09
申请号：US12104461
申请日：2008-04-17
申请人： Gary D. Grise , Vikram Iyengar , David E. Lackey , David W. Milton
发明人： Gary D. Grise , Vikram Iyengar , David E. Lackey , David W. Milton
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F1/10 , G06F2217/62 , H03K5/156
摘要： Disclosed are embodiments of a clock generation circuit, a design structure for the circuit and an associated method that provide deskewing functions and that further provide precise timing for both testing and functional operations. Specifically, the embodiments incorporate a deskewer circuit that is capable of receiving waveform signals from both an external waveform generator and an internal waveform generator. The external waveform generator can generate and supply to the deskewer circuit a pair of waveform signals for functional operations. The internal waveform generator can be uniquely configured with control logic and counter logic for generating and supplying a pair of waveform signals to the deskewer circuit for any one of built-in self-test (BIST) operations, macro-test operations, other test operations or functional operations. The deskewer circuit can selectively gate an input clock signal with the waveform signals from either the external or internal waveform generator in order to generate the required output clock signal.
摘要翻译：公开了时钟发生电路的实施例，用于电路的设计结构和相关联的方法，其提供了偏移功能，并进一步为测试和功能操作提供精确的定时。具体地说，这些实施例结合了能够从外部波形发生器和内部波形发生器接收波形信号的偏移电路。外部波形发生器可以生成和提供一个用于功能操作的波形信号。内部波形发生器可以独特地配置控制逻辑和计数器逻辑，用于为内置自检（BIST）操作，宏测试操作，其他测试操作中的任何一个产生和提供一对波形信号到电路板电路或功能操作。该偏移电路可以使用来自外部或内部波形发生器的波形信号选择性地输入输入时钟信号，以便产生所需的输出时钟信号。

8. 发明授权

US07856607B2 System and method for generating at-speed structural tests to improve process and environmental parameter space coverage 有权
标题翻译：用于生成高速结构测试以改进过程和环境参数空间覆盖的系统和方法
公开(公告)号：US07856607B2
公开(公告)日：2010-12-21
申请号：US11934146
申请日：2007-11-02
申请人： Gary D. Grise , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Chandramouli Visweswariah , Vladimir Zolotov
发明人： Gary D. Grise , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F11/24 , G01R31/31835
摘要： A system for enhancing the practicability of at-speed structural testing (ASST). In one embodiment, the system includes first means for performing statistical timing analysis on a design of logic circuitry. A second means performs a criticality analysis on the logic circuitry as a function of the statistical timing analysis so as to determine a criticality probability for each node of the logic circuitry. A third means selects nodes of the logic circuitry as a function of the criticality analysis. A fourth means selects timing paths as a function of the criticality probabilities of the selected nodes. A fifth means generates an ASST pattern for each of the selected timing paths. A sixth mean is provided to perform ASST on a fabricated instantiation of the design at functional speed using the generated ASST pattern.
摘要翻译：一种提高高速结构测试（ASST）实用性的系统。在一个实施例中，系统包括用于对逻辑电路的设计执行统计时序分析的第一装置。第二种方法是根据统计时序分析对逻辑电路执行关键性分析，以确定逻辑电路的每个节点的临界概率。第三种方法是选择逻辑电路的节点作为关键性分析的函数。第四种装置根据所选节点的临界概率来选择定时路径。第五装置为每个所选定时路径生成ASST模式。提供了第六个平均值，以使用所生成的ASST模式在功能速度上对制造的设计实例化执行ASST。

9. 发明授权

US08538718B2 Clock edge grouping for at-speed test 失效
标题翻译：用于速度测试的时钟分组
公开(公告)号：US08538718B2
公开(公告)日：2013-09-17
申请号：US12967885
申请日：2010-12-14
申请人： Gary D. Grise , Vikram Iyengar , Douglas E. Sprague , Mark R. Taylor
发明人： Gary D. Grise , Vikram Iyengar , Douglas E. Sprague , Mark R. Taylor
IPC分类号： G06F19/00
CPC分类号： G01R31/31726 , G01R31/31922
摘要： A method of grouping clock domains includes: separating a plurality of test clocks into a plurality of domain groups by adding to each respective one of the plurality of domain groups those test clocks that originate from a same clock source and have a unique clock divider ratio; sorting the domain groups in decreasing order of size; and creating a plurality of parts by adding the respective one of the plurality of domain groups to a first one of the plurality of parts in which already present test clocks have a different clock source, and creating a new part and adding the respective one of the plurality of domain groups to the new part when test clocks present in the respective one of the plurality of domain groups originate from a respective same clock source and have a different clock divider ratio as test clocks present in all previously-created parts.
摘要翻译：一种对时钟域进行分组的方法包括：通过向多个域组中的每个相应的一个组分配来自相同时钟源的那些测试时钟并具有唯一的时钟分频比，将多个测试时钟分离成多个域组; 按照大小顺序排列域组; 以及通过将多个域组中的相应一个组合添加到已经存在的测试时钟具有不同时钟源的多个部分中的第一部分来创建多个部分，并且创建新部分并将相应的一个当存在于多个域组中的相应一个域组中的相应一个域组中的测试时钟源自相应的相同时钟源并且具有不同的时钟分频比作为存在于所有先前创建的部分中的测试时钟时，多个域组到新部分。

10. 发明申请

US20080222472A1 METHOD FOR AUTOMATIC TEST PATTERN GENERATION FOR ONE TEST CONSTRAINT AT A TIME 审中-公开
标题翻译：一种用于一次测试约束的自动测试图形生成方法
公开(公告)号：US20080222472A1
公开(公告)日：2008-09-11
申请号：US11684242
申请日：2007-03-09
申请人： Gary D. Grise , Vikram Iyengar , Mark R. Taylor
发明人： Gary D. Grise , Vikram Iyengar , Mark R. Taylor
IPC分类号： G01R31/28
CPC分类号： G01R31/318307
摘要： A method for automatically generating test patterns for an IC device includes initially generating a subset of available test patterns according to each of a plurality of test constraints for the IC device, determining an incremental amount of total test coverage of the IC device attributable to each of the test constraints as a result of the initially generated subset of test patterns therefor; determining the test constraint initially providing the largest amount of incremental test coverage, and thereafter generating another subset of test patterns therefor; and iteratively determining the current test constraint providing the largest amount of incremental test coverage, and continuing to generate additional test patterns therefor until one or more test exit criteria is reached.
摘要翻译：一种用于自动生成用于IC器件的测试图案的方法包括：根据IC器件的多个测试约束中的每一个，初始地生成可用测试图案的子集，确定归属于每个IC器件的IC器件的总测试覆盖的增量作为最初生成的测试模式子集的结果的测试约束; 确定最初提供最大量的增量测试覆盖的测试约束，然后生成另一个测试模式子集; 并迭代地确定提供最大量的增量测试覆盖的当前测试约束，并且继续生成附加的测试模式，直到达到一个或多个测试退出标准。

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