专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08117579B2 LSSD compatibility for GSD unified global clock buffers 有权
标题翻译： LSSD兼容GSD统一全局时钟缓冲区
公开(公告)号：US08117579B2
公开(公告)日：2012-02-14
申请号：US12023337
申请日：2008-01-31
申请人： James Douglas Warnock , Wendel Dieter , David E. Lackey , William Vincent Huott , Leon Jacob Sigal , Louis Bernard Bushard , Sang Hoo Dhong
发明人： James Douglas Warnock , Wendel Dieter , David E. Lackey , William Vincent Huott , Leon Jacob Sigal , Louis Bernard Bushard , Sang Hoo Dhong
IPC分类号： G06F17/50
CPC分类号： G01R31/318594 , G01R31/318552
摘要： A method, system and program are provided for generating level sensitive scan design (LSSD) clock signals from a general scan design (GSD) clock buffer using an intermediate clock signal and one or more first mode control signals to generate a plurality of LSSD clock signals from an output section of the GSD clock buffer that receives the intermediate clock signal and the first mode control signal(s), where the GSD clock buffer is also configured to generate a plurality of GSD clock signals in response to receiving a GSD mode, generating an intermediate clock signal from the input section of the GSD clock buffer in response receiving a GSD mode signal.
摘要翻译：提供了一种方法，系统和程序，用于使用中间时钟信号和一个或多个第一模式控制信号从一般扫描设计（GSD）时钟缓冲器产生电平敏感扫描设计（LSSD）时钟信号，以产生多个LSSD时钟信号从GSD时钟缓冲器的输出部分接收中间时钟信号和第一模式控制信号，其中GSD时钟缓冲器还被配置为响应于接收到GSD模式产生多个GSD时钟信号，产生来自GSD时钟缓冲器的输入部分的中间时钟信号响应于接收GSD模式信号。

2. 发明申请

US20090121747A1 Maintaining Circuit Delay Characteristics During Power Management Mode 审中-公开
标题翻译：在电源管理模式下维护电路延迟特性
公开(公告)号：US20090121747A1
公开(公告)日：2009-05-14
申请号：US11938347
申请日：2007-11-12
申请人： Sang Hoo Dhong , Peter Harm Hofstee , Mack Wayne Riley , James Douglas Warnock , Stephen Douglas Weitzel
发明人： Sang Hoo Dhong , Peter Harm Hofstee , Mack Wayne Riley , James Douglas Warnock , Stephen Douglas Weitzel
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K19/0008
摘要： A system and method for maintaining circuit delay characteristics during power management mode. The method for maintaining circuit delay characteristics during power management mode continually toggles the clock distribution circuits at a frequency sufficiently low that it does not significantly impact chip power dissipation. The clock frequency used to toggle the clock distribution circuits is high enough to minimize the asymmetrical stress on the clock buffer transistors so that both P and N device characteristics equally change over time.
摘要翻译：一种用于在电源管理模式下维持电路延迟特性的系统和方法。用于在电源管理模式期间维持电路延迟特性的方法连续地将时钟分配电路切换到足够低的频率，使其不会显着影响芯片功率耗散。用于切换时钟分配电路的时钟频率足够高以最小化时钟缓冲晶体管上的不对称应力，以便P和N器件特性随时间均匀变化。

3. 发明授权

US06927615B2 Low skew, power efficient local clock signal generation system 失效
标题翻译：低偏移，功率有效的本地时钟信号发生系统
公开(公告)号：US06927615B2
公开(公告)日：2005-08-09
申请号：US10455178
申请日：2003-06-05
申请人： Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi , James Douglas Warnock , Dieter Wendel
发明人： Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi , James Douglas Warnock , Dieter Wendel
IPC分类号： G06F1/04 , G06F1/10 , H03K3/00
CPC分类号： G06F1/10
摘要： A local clock signal generation system is disclosed including multiple local clock buffers each receiving a global clock signal and producing a version of one or more local clock signals derived from the global clock signal. Each local clock buffer includes an input section and an output section. The input sections are substantially identical such that timing differences between the versions of the one or more local clock signals are reduced. An electronic circuit is described including the local clock signal generation system and a latch (e.g., a master latch of a flip-flop). A local clock buffer produces a gating signal and a local clock signal received by the latch. When the gating signal is a certain logic value, the local clock signal is a steady logic value, and the latch produces an input data signal as an output signal. An integrated circuit including the electronic circuit is disclosed.
摘要翻译：公开了本地时钟信号产生系统，其包括多个本地时钟缓冲器，每个时钟缓冲器接收全局时钟信号并产生从全局时钟信号导出的一个或多个本地时钟信号的版本。每个本地时钟缓冲器包括输入部分和输出部分。输入部分基本相同，使得一个或多个本地时钟信号的版本之间的定时差减小。描述了包括本地时钟信号产生系统和锁存器（例如，触发器的主锁存器）的电子电路。本地时钟缓冲器产生门控信号和由锁存器接收到的本地时钟信号。当门控信号为某一逻辑值时，本地时钟信号为稳定逻辑值，锁存器产生输入数据信号作为输出信号。公开了一种包括电子电路的集成电路。

4. 发明授权

US06825695B1 Unified local clock buffer structures 失效
标题翻译：统一本地时钟缓冲结构
公开(公告)号：US06825695B1
公开(公告)日：2004-11-30
申请号：US10455170
申请日：2003-06-05
申请人： Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi , James Douglas Warnock , Dieter Wendel
发明人： Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi , James Douglas Warnock , Dieter Wendel
IPC分类号： H03K19096
CPC分类号： G06F1/10
摘要： Several local clock buffers are disclosed, each including an input section and an output section. The input sections are substantially identical, and include control logic and gating logic. The control logic produces a gating signal dependent upon multiple control signals and a time-delayed global clock signal. The gating logic produces an intermediate clock signal dependent upon the global clock signal and the gating signal. The output section produces at least one local clock signal dependent upon the intermediate clock signal. In one embodiment, the output section produces a first local clock signal dependent upon the intermediate clock signal and a second local clock signal dependent upon the first local clock signal. In another embodiment, the gating logic produces the intermediate clock signal dependent upon the global clock and gating signals and a feedback signal. The output section produces the feedback signal and one or more local clock signals.
摘要翻译：公开了几个本地时钟缓冲器，每个本地时钟缓冲器包括输入部分和输出部分。输入部分基本相同，包括控制逻辑和门控逻辑。控制逻辑产生取决于多个控制信号和时间延迟的全局时钟信号的选通信号。门控逻辑产生取决于全局时钟信号和门控信号的中间时钟信号。输出部分根据中间时钟信号产生至少一个本地时钟信号。在一个实施例中，输出部分产生取决于中间时钟信号的第一本地时钟信号和取决于第一本地时钟信号的第二本地时钟信号。在另一个实施例中，选通逻辑根据全局时钟和门控信号以及反馈信号产生中间时钟信号。输出部分产生反馈信号和一个或多个本地时钟信号。

5. 发明授权

US07165006B2 Scan chain disable function for power saving 失效
标题翻译：扫描链禁用功能进行省电
公开(公告)号：US07165006B2
公开(公告)日：2007-01-16
申请号：US10976259
申请日：2004-10-28
申请人： Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi , James Douglas Warnock , Dieter Wendel
发明人： Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi , James Douglas Warnock , Dieter Wendel
IPC分类号： G06F19/00
CPC分类号： G06F1/3203 , G06F1/325
摘要： An apparatus, a method and a computer program product are provided for conserving energy during functional mode of a processor by disabling the scan chain. By inserting logic gating into the scan chain it is possible to disable the scan chain during the processor's functional mode. During functional mode the scan out port of the latch bit in a scan chain toggles, which leads to unnecessary energy consumption. By gating scan control signals and the scan out port of a latch bit, the scan chain segment between latch bits can be disconnected. Therefore, the scan control signals can disable the scan chain during functional mode.
摘要翻译：提供了一种装置，方法和计算机程序产品，用于通过禁用扫描链来在处理器的功能模式期间节省能量。通过将逻辑门控插入到扫描链中，可以在处理器的功能模式期间禁用扫描链。在功能模式期间，扫描链中锁存位的扫描输出端口切换，这导致不必要的能量消耗。通过门控扫描控制信号和锁存位的扫描输出端口，可以断开锁存位之间的扫描链段。因此，扫描控制信号可以在功能模式下禁用扫描链。

6. 发明授权

US07962811B2 Scan chain disable function for power saving 失效
标题翻译：扫描链禁用功能进行省电
公开(公告)号：US07962811B2
公开(公告)日：2011-06-14
申请号：US11552807
申请日：2006-10-25
申请人： Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi , James Douglas Warnock , Dieter Wendel
发明人： Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi , James Douglas Warnock , Dieter Wendel
IPC分类号： G01R31/28 , G01R27/28 , G01R31/00 , G01R31/14
CPC分类号： G06F1/3203 , G06F1/325
摘要： An apparatus, a method and a computer program product are provided for conserving energy during functional mode of a processor by disabling the scan chain. By inserting logic gating into the scan chain it is possible to disable the scan chain during the processor's functional mode. During functional mode the scan out port of the latch bit in a scan chain toggles, which leads to unnecessary energy consumption. By gating scan control signals and the scan out port of a latch bit, the scan chain segment between latch bits can be disconnected. Therefore, the scan control signals can disable the scan chain during functional mode.
摘要翻译：提供了一种装置，方法和计算机程序产品，用于通过禁用扫描链来在处理器的功能模式期间节省能量。通过将逻辑门控插入到扫描链中，可以在处理器的功能模式期间禁用扫描链。在功能模式期间，扫描链中锁存位的扫描输出端口切换，这导致不必要的能量消耗。通过门控扫描控制信号和锁存位的扫描输出端口，可以断开锁存位之间的扫描链段。因此，扫描控制信号可以在功能模式下禁用扫描链。

7. 发明授权

US06744282B1 Latching dynamic logic structure, and integrated circuit including same 有权
标题翻译：闭锁动态逻辑结构，集成电路包括相同
公开(公告)号：US06744282B1
公开(公告)日：2004-06-01
申请号：US10401327
申请日：2003-03-27
申请人： Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi , James Douglas Warnock , Dieter Wendel
发明人： Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi , James Douglas Warnock , Dieter Wendel
IPC分类号： H03K1900
CPC分类号： H03K19/0963
摘要： A latching dynamic logic structure is disclosed including a static logic interface, a dynamic logic gate, and a static latch. The static logic interface receives a data signal, a select signal, and a clock signal, and produces a first intermediate signal such that when the select signal is active, the first intermediate signal is dependent upon the data signal for a period of time following a clock signal transition. The dynamic logic gate discharges a dynamic node following the clock signal transition dependent upon the first intermediate signal. The static latch produces an output signal assuming one of two logic levels following the clock signal transition, and assuming the other logic level in the event the dynamic node is discharged. A scan-testing-enabled version of the latching dynamic logic structure is described, as is an integrated circuit including the latching dynamic logic structure.
摘要翻译：公开了一种闭锁动态逻辑结构，其包括静态逻辑接口，动态逻辑门和静态锁存器。静态逻辑接口接收数据信号，选择信号和时钟信号，并产生第一中间信号，使得当选择信号有效时，第一中间信号取决于数据信号一段时间时钟信号转换。动态逻辑门在取决于第一中间信号的时钟信号转换之后放电动态节点。静态锁存器产生一个输出信号，假定在时钟信号转换之后有两个逻辑电平之一，并且假定动态节点放电的另一个逻辑电平。描述了锁定动态逻辑结构的扫描测试功能版本，以及包括锁存动态逻辑结构的集成电路。

8. 发明授权

US06901546B2 Enhanced debug scheme for LBIST 失效
标题翻译： LBIST增强的调试方案
公开(公告)号：US06901546B2
公开(公告)日：2005-05-31
申请号：US09876753
申请日：2001-06-07
申请人： Sam Gat-Shang Chu , Joachim Gerhard Clabes , Michael Normand Goulet , Johnny J. Leblanc , James Douglas Warnock
发明人： Sam Gat-Shang Chu , Joachim Gerhard Clabes , Michael Normand Goulet , Johnny J. Leblanc , James Douglas Warnock
IPC分类号： G01R31/317 , G01R31/3185 , G01R31/3187 , G06F11/27 , G01R31/28 , G06R11/00
CPC分类号： G01R31/3187 , G01R31/31705 , G01R31/318502 , G06F11/27
摘要： A device for fault testing in a microprocessor chip provides a LBIST circuit which has a first reference signature. A loading unit is further provided for receiving and outputting a set of masking data. A file unit connected to the loading unit is yet further provided for receiving the masking data. A masking unit connected to the file unit is yet further provided for generating a second reference signature based on the masking data from the file unit and a scanning data from a scan string in the chip. And, a signature logic connected to the output of the masking unit is yet further provided for compressing the second reference signature and inputting the compressed second reference signature to the LBIST circuit, wherein the compressed second reference signature replaces the first reference signature.
摘要翻译：用于微处理器芯片中的故障测试的装置提供具有第一参考标识的LBIST电路。进一步提供加载单元，用于接收和输出一组屏蔽数据。还提供连接到加载单元的文件单元用于接收掩蔽数据。还提供连接到文件单元的掩蔽单元，用于基于来自文件单元的掩蔽数据和来自芯片中的扫描串的扫描数据来生成第二参考签名。并且，还提供连接到屏蔽单元的输出的签名逻辑，用于压缩第二参考签名并将压缩的第二参考签名输入到LBIST电路，其中压缩的第二参考签名替换第一参考签名。

9. 发明申请

US20090160515A1 Auto-tracking clock circuitry 审中-公开
标题翻译：自动跟踪时钟电路
公开(公告)号：US20090160515A1
公开(公告)日：2009-06-25
申请号：US11959907
申请日：2007-12-19
申请人： James Douglas Warnock
发明人： James Douglas Warnock
IPC分类号： H03K5/04
CPC分类号： H03K5/1565 , G06F1/04
摘要： A system and method for generating a clock signal is disclosed. In various embodiments of the invention disclosed herein, a global clock signal is generated and provided as an input to local clock circuitry operable to generate a local clock signal therefrom. The local clock circuitry comprises logic components that are susceptible to negative bias thermal instability (NBTI) effects resulting in degradation of the local clock signal. Clock propagation adjustment circuitry is used to modify the duty cycle of the global clock signal to compensate for the degradation resulting from NBTI effects thereby providing an optimized local clock signal.
摘要翻译：公开了一种用于产生时钟信号的系统和方法。在本文公开的本发明的各种实施例中，生成全局时钟信号并将其提供为可操作以从其产生本地时钟信号的本地时钟电路的输入。本地时钟电路包括易受负偏压热不稳定性（NBTI）影响的逻辑部件，导致本地时钟信号的劣化。时钟传播调整电路用于修改全局时钟信号的占空比，以补偿由NBTI效应引起的劣化，从而提供优化的本地时钟信号。

10. 发明授权

US07191419B2 Method of timing model abstraction for circuits containing simultaneously switching internal signals 失效
标题翻译：包含同时切换内部信号的电路的定时模型抽象方法
公开(公告)号：US07191419B2
公开(公告)日：2007-03-13
申请号：US10897349
申请日：2004-07-22
申请人： Jeffrey Paul Soreff , James Douglas Warnock
发明人： Jeffrey Paul Soreff , James Douglas Warnock
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： The present invention provides for determining arrival times in a circuit. An arrival time for a main signal is assigned. An arrival time for a secondary signal is assigned. It is determined whether a test is for an early arrival or for a later arrival. If the test type is for a late arrival, it is determined whether the arrival time for the secondary signal is later than for the first signal. If the test type is for an early arrival, it is determined whether the arrival time for the secondary signal is earlier than for the first signal. If the test type is for the late arrival and the arrival time for the secondary signal is later than for the first signal, assume maximum interference between the signals. If the test type is for the late arrival and the arrival time for the secondary signal is not later than for the first signal, calculate the actual interference between the signals.
摘要翻译：本发明提供了确定电路中的到达时间。分配主信号的到达时间。分配辅助信号的到达时间。确定测试是提前到达还是稍后到达。如果测试类型是迟到的，则确定辅助信号的到达时间是否晚于第一信号。如果测试类型是用于提前到达，则确定辅助信号的到达时间是否早于第一信号。如果测试类型为迟到，并且辅助信号的到达时间晚于第一信号，则假定信号之间的最大干扰。如果测试类型为迟到，并且次要信号的到达时间不晚于第一个信号，则计算信号之间的实际干扰。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式