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31. 发明授权

US07816706B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US07816706B2
公开(公告)日：2010-10-19
申请号：US12007890
申请日：2008-01-16
申请人： Munaf Rahimo , Peter Streit
发明人： Munaf Rahimo , Peter Streit
IPC分类号： H01L29/745 , H01L21/332
CPC分类号： H01L29/102 , H01L29/744
摘要： The power semiconductor device with a four-layer npnp structure can be turned-off via a gate electrode. The first base layer comprises a cathode base region adjacent to the cathode region and a gate base region adjacent to the gate electrode, but disposed at a distance from the cathode region. The gate base region has the same nominal doping density as the cathode base region in at least one first depth, the first depth being given as a perpendicular distance from the side of the cathode region, which is opposite the cathode metallization. The gate base region has a higher doping density than the cathode base region and/or the gate base region has a greater depth than the cathode base region in order to modulate the field in blocking state and to defocus generated holes from the cathode when driven into dynamic avalanche.
摘要翻译：具有四层npnp结构的功率半导体器件可以通过栅电极截止。第一基极层包括与阴极区域相邻的阴极基极区域和与栅极电极相邻但与阴极区域相距一定距离的栅极基极区域。栅极基极区域在至少一个第一深度中具有与阴极基极区域相同的标称掺杂密度，第一深度被给定为与阴极金属化相对的阴极区域侧的垂直距离。栅极基极区域具有比阴极基极区域更高的掺杂密度和/或栅极基极区域具有比阴极基极区域更大的深度，以便调制阻塞状态下的场并且当被驱动进入时将其从阴极散焦动态雪崩

32. 发明申请

US20090159926A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090159926A1
公开(公告)日：2009-06-25
申请号：US12277838
申请日：2008-11-25
申请人： Tetsuya IKUTA
发明人： Tetsuya IKUTA
IPC分类号： H01L29/745 , H01L21/332
CPC分类号： H01L29/7455 , H01L29/66363
摘要： A semiconductor device includes a thyristor in which a first-conductivity-type first region, a second-conductivity-type second region having a conductivity type reverse to the first conductivity type, a first-conductivity-type third region, and a second-conductivity-type fourth region are sequentially arranged to form junctions. The third region is formed on a semiconductor substrate separated by an element isolation region. A gate electrode formed via a gate insulating film and side wall formed at wall side of both side of the gate electrode are provided on the third region, and the fourth region is formed so that one end thereof covers the joint portion between the other end of the third region and the element isolation regions, and so that the other end of the fourth region is joined with the sidewall on the other side.
摘要翻译：半导体器件包括晶闸管，其中第一导电型第一区，具有与第一导电类型相反的导电类型的第二导电型第二区，第一导电型第三区和第二导电型依次排列形成接合点。第三区域形成在由元件隔离区域分离的半导体衬底上。通过栅极绝缘膜形成的栅电极和形成在栅极两侧的壁侧的侧壁设置在第三区域上，第四区域形成为使得其一端覆盖栅极电极的另一端的接合部分第三区域和元件隔离区域，并且使得第四区域的另一端与另一侧的侧壁接合。

33. 发明授权

US07479667B2 Semiconductor device with modified mobility and thin film transistor having the same 失效
标题翻译：具有改性迁移率的半导体器件和具有该迁移率的薄膜晶体管
公开(公告)号：US07479667B2
公开(公告)日：2009-01-20
申请号：US11022756
申请日：2004-12-28
申请人： Jang-yeon Kwon , Takashi Noguchi , Young-soo Park , Do-young Kim
发明人： Jang-yeon Kwon , Takashi Noguchi , Young-soo Park , Do-young Kim
IPC分类号： H01L29/76 , H01L29/745
CPC分类号： H01L29/78696 , H01L21/02532 , H01L21/02686 , H01L21/2026 , H01L27/1285 , H01L27/1296 , H01L29/04 , H01L29/1029 , H01L29/6675 , H01L29/78663 , H01L29/78672
摘要： Provided are a semiconductor device including an active area which is defined as high and low mobility areas and a thin film transistor having the semiconductor device. The mobility of the active area can be lowered to a level enough to satisfy the requirement of the semiconductor device. The lowering of the mobility of the active area can contribute to reducing mobility deviation between semiconductor devices. As a result, the quality of a flat panel display adopting a large-scale semiconductor device can be greatly improved.
摘要翻译：提供了包括被定义为高和低迁移率区域的有源区域和具有半导体器件的薄膜晶体管的半导体器件。有源面积的迁移率可以降低到足以满足半导体器件要求的水平。有源区的迁移率的降低有助于减少半导体器件之间的迁移率偏差。结果，可以大大提高采用大规模半导体器件的平板显示器的质量。

34. 发明申请

US20080006848A1 Semiconductor structure for use in a static induction transistor having improved gate-to-drain breakdown voltage 有权
公开(公告)号：US20080006848A1
公开(公告)日：2008-01-10
申请号：US11444497
申请日：2006-06-01
申请人： Li-Shu Chen , Victor Veliadis
发明人： Li-Shu Chen , Victor Veliadis
IPC分类号： H01L29/76 , H01L29/745
CPC分类号： H01L29/0661 , H01L29/0619 , H01L29/063 , H01L29/1608 , H01L29/66068 , H01L29/7722 , Y10S438/931
摘要： A structure for use in a static induction transistor includes a semiconductor body having first and second semiconductor layers on a substrate, with the second layer having a dopant concentration of around an order of magnitude higher than the dopant concentration of the first layer. A plurality of sources are located on the second layer. A plurality of gates are ion implanted in the second layer, an end one of the gates being connected to all of the plurality of gates and constituting a gate bus. The gate bus has an extension connecting the gate bus in the second layer of higher dopant concentration to the first layer of lower dopant concentration. The extension is ion implanted in either a series of steps or a sloping surface which is formed in the first and second layers.

35. 发明申请

US20070284623A1 Semiconductor device having vertical channel transistor 审中-公开
标题翻译：具有垂直沟道晶体管的半导体器件
公开(公告)号：US20070284623A1
公开(公告)日：2007-12-13
申请号：US11802647
申请日：2007-05-24
申请人： Sang-Jin Kim , Gi-sung Yeo , Joon-soo Park , Han-ku Cho , Sang-gyun Woo , Min-jong Hong
发明人： Sang-Jin Kim , Gi-sung Yeo , Joon-soo Park , Han-ku Cho , Sang-gyun Woo , Min-jong Hong
IPC分类号： H01L29/76 , H01L29/745
CPC分类号： H01L27/0207 , H01L27/10823 , H01L27/10876 , H01L29/4236 , H01L29/66666 , H01L29/7827
摘要： A semiconductor device includes a substrate, and a plurality of active pillars arranged in a pattern of alternating even and odd rows and alternating even and odd columns, each active pillar extending from the substrate and including a channel portion, wherein the odd columns include active pillars spaced at a first pitch, the first pitch being determined in the column direction, the even columns include active pillars spaced at the first pitch, the even rows include active pillars spaced at a third pitch, the third pitch being determined in the row direction the odd rows include active pillars spaced at the third pitch, and active pillars in the even columns are offset by a second pitch from active pillars in the odd columns, the second pitch being determined in the column direction.
摘要翻译：半导体器件包括衬底和布置成交替的偶数行和奇数行以及交替的偶数和奇数列的多个有源柱，每个有源柱从衬底延伸并且包括沟道部分，其中奇数列包括有源柱以第一间距间隔开，第一间距是在列方向上确定的，偶数列包括以第一节距间隔开的活动柱，偶数行包括以第三节距间隔开的有效柱，第三间距在行方向上确定奇数行包括在第三间距处间隔开的活动柱，并且偶数列中的活动柱由奇数列中的活动柱偏移第二间距，第二间距在列方向上确定。

36. 发明授权

US07268373B1 Thyristor-based memory and its method of operation 失效
标题翻译：基于晶闸管的存储器及其操作方法
公开(公告)号：US07268373B1
公开(公告)日：2007-09-11
申请号：US10947794
申请日：2004-09-23
申请人： Rajesh Narendra Gupta , Farid Nemati
发明人： Rajesh Narendra Gupta , Farid Nemati
IPC分类号： H01L29/745
CPC分类号： H01L27/11 , G11C11/39 , H01L27/1027 , H01L29/74
摘要： A semiconductor may contain a plurality of circuits each comprising at least one thyristor having a base region. The base region of at least one of the thyristors has a different doping profile than the others. When a bias circuit is used to bias the thyristors, the effect of biasing on the thyristors is found to be affected by the doping profile. In a specific embodiment, the doping concentration is higher near an electrode of the thyristor than near a supporting substrate. The different doping profiles can be achieved by using different ion implant energies.
摘要翻译：半导体可以包含多个电路，每个电路包括至少一个具有基极区域的晶闸管。至少一个晶闸管的基极区域具有与其它晶体管不同的掺杂分布。当偏置电路用于偏置晶闸管时，发现偏置对晶闸管的影响受到掺杂分布的影响。在具体实施例中，在晶闸管的电极附近的掺杂浓度比在支撑衬底附近更高。通过使用不同的离子注入能量可以实现不同的掺杂分布。

37. 发明申请

US20070102732A1 Metal oxide semiconductor device 审中-公开
标题翻译：金属氧化物半导体器件
公开(公告)号：US20070102732A1
公开(公告)日：2007-05-10
申请号：US11270928
申请日：2005-11-10
申请人： Ming-Kwei Lee , Jung-Jie Huang , Tsung-Shiun Wu , Chih-Feng Yen
发明人： Ming-Kwei Lee , Jung-Jie Huang , Tsung-Shiun Wu , Chih-Feng Yen
IPC分类号： H01L29/76 , H01L29/745
CPC分类号： H01L21/28185 , H01L21/28079 , H01L21/28194 , H01L21/28238 , H01L21/28264 , H01L29/513 , H01L29/517
摘要： A MOS device includes: a semiconductor substrate; an insulator layer formed on the semiconductor substrate, and including a fluorine-containing titanium dioxide film that has grain boundary defects passivated by fluorine; and upper and lower electrodes formed on the insulator layer and the semiconductor substrate, respectively.
摘要翻译： MOS器件包括：半导体衬底; 形成在半导体衬底上的绝缘体层，并且包括具有被氟钝化的晶界缺陷的含氟二氧化钛膜; 以及分别形成在绝缘体层和半导体衬底上的上下电极。

38. 发明申请

US20070090406A1 STRUCTURE AND METHOD FOR MANUFACTURING HIGH PERFORMANCE AND LOW LEAKAGE FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：制造高性能和低漏电场效应晶体管的结构和方法
公开(公告)号：US20070090406A1
公开(公告)日：2007-04-26
申请号：US11163647
申请日：2005-10-26
申请人： Huilong Zhu , Kangguo Cheng
发明人： Huilong Zhu , Kangguo Cheng
IPC分类号： H01L29/76 , H01L29/745
CPC分类号： H01L21/26506 , H01L21/26586 , H01L29/1054 , H01L29/165 , H01L29/6653 , H01L29/66545 , H01L29/66636 , H01L29/66659 , H01L29/78
摘要： There is provided a field effect transistor (FET) including a source side semiconductor; a drain side semiconductor; and a gate. The source side semiconductor is made of a high mobility semiconductor material, and the drain side semiconductor is made of a low leakage semiconductor material. In one embodiment, the FET is a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). There is also provided a method for manufacturing the FET.
摘要翻译：提供了包括源极半导体的场效应晶体管（FET）; 漏极侧半导体; 和一个门。源极半导体由高迁移率半导体材料制成，漏极侧半导体由低泄漏半导体材料制成。在一个实施例中，FET是金属氧化物半导体场效应晶体管（MOSFET）。还提供了一种用于制造FET的方法。

39. 发明申请

US20070082495A1 Semiconductor device having nano-pillars and method therefor 有权
标题翻译：具有纳米柱的半导体器件及其方法
公开(公告)号：US20070082495A1
公开(公告)日：2007-04-12
申请号：US11244516
申请日：2005-10-06
申请人： Leo Mathew , Rajesh Rao , Ramachandran Muralidhar
发明人： Leo Mathew , Rajesh Rao , Ramachandran Muralidhar
IPC分类号： H01L29/76 , H01L21/461 , H01L21/302 , H01L29/745
CPC分类号： H01L29/42368 , B82Y10/00 , H01L21/28273 , H01L21/32139 , H01L28/91 , H01L29/512 , H01L29/513
摘要： A semiconductor device includes a plurality of pillars formed from a conductive material. The pillars are formed by using a plurality of nanocrystals as a hardmask for patterning the conductive material. A thickness of the conductive material determines the height of the pillars. Likewise, a width of the pillar is determined by the diameter of a nanocrystal. In one embodiment, the pillars are formed from polysilicon and function as the charge storage region of a non-volatile memory cell having good charge retention and low voltage operation. In another embodiment, the pillars are formed from a metal and function as a plate electrode for a metal-insulator-metal (MIM) capacitor having an increased capacitance without increasing the surface area of an integrated circuit.
摘要翻译：半导体器件包括由导电材料形成的多个支柱。通过使用多个纳米晶体作为用于图案化导电材料的硬掩模来形成柱。导电材料的厚度决定了支柱的高度。同样，柱的宽度由纳米晶体的直径决定。在一个实施例中，柱由多晶硅形成，并且用作具有良好电荷保持和低电压操作的非易失性存储单元的电荷存储区。在另一个实施例中，支柱由金属形成，并且用作具有增加的电容的金属 - 绝缘体 - 金属（MIM）电容器的平板电极，而不增加集成电路的表面积。

40. 发明授权

US07199409B2 Device for subtracting or adding charge in a charge-coupled device 失效
标题翻译：用于在电荷耦合器件中减去或增加电荷的装置
公开(公告)号：US07199409B2
公开(公告)日：2007-04-03
申请号：US10926937
申请日：2004-08-26
申请人： Michael P. Anthony
发明人： Michael P. Anthony
IPC分类号： H01L27/148 , H01L29/747 , H01L29/768 , H01L29/745 , H01L29/76
CPC分类号： H04N5/347 , H04N5/372 , Y10S257/905
摘要： The present invention provides an apparatus for adding or subtracting an amount charge to or from a charge packet in a CCD as the packet traverses the CCD. The apparatus uses a “wire transfer” device structure to perform the addition or subtraction of charge during the charge packets traversal across the device. A pair of electrically interconnected diffusions are incorporated within the charge couple path to provide an amount of charge which can be added or subtracted from packets as the packets traverse the CCD.
摘要翻译：本发明提供了一种用于在数据包穿过CCD时向CCD中的电荷分组加或减量量的装置。该装置使用“有线传输”装置结构来在充电数据包遍历装置期间执行电荷的加或减。一对电互连的扩散结合在电荷耦合路径内，以提供当分组穿过CCD时能从分组中加或减的电荷量。

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