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31. 发明授权

US5113516A Data repacker having controlled feedback shifters and registers for changing data format 失效
标题翻译：数据重新包装器具有控制的反馈移位器和寄存器来改变数据格式
公开(公告)号：US5113516A
公开(公告)日：1992-05-12
申请号：US388281
申请日：1989-07-31
申请人： Brian C. Johnson
发明人： Brian C. Johnson
IPC分类号： G06F7/78 , H03M7/30
CPC分类号： G06F7/785 , H03M7/3084 , H03M7/3088
摘要： A data repacker utilizing a multiplexer, one intermediate register, two shifters, and a control for these circuits. The multiplexer output is connected to the intermediate register, which has a storage length greater than the size of data words to be repacked. The first shifter receives the output of the register, and its output can be concatenated with an input data word to form one input to the multiplexer. The output of the register is provided as another input to the multiplexer. The second shifter also receives the output of the multiplexer, and has an output which is the repacker output. Information representing the number of bits in and the number of bits out is used to determine the most and least significant bits of the intermediate data which will be stored in the intermediate register, and to control the shifters.
摘要翻译：一种利用多路复用器，一个中间寄存器，两个移位器和这些电路的控制的数据重新装载机。多路复用器输出连接到中间寄存器，该寄存器的存储长度大于要重新打包的数据字的大小。第一移位器接收寄存器的输出，并且其输出可以与输入数据字连接，以形成多路复用器的一个输入。寄存器的输出被提供给多路复用器的另一个输入。第二移位器还接收多路复用器的输出，并且具有作为再分配器输出的输出。表示位数和信号数的信息用于确定将存储在中间寄存器中的中间数据的最高有效位和最低有效位，并控制移位器。

32. 发明授权

US5058137A Lempel-Ziv decoder 失效
标题翻译： Lempel-Ziv解码器
公开(公告)号：US5058137A
公开(公告)日：1991-10-15
申请号：US388283
申请日：1989-07-31
申请人： Imran A. Shah
发明人： Imran A. Shah
IPC分类号： G06F7/78 , G06T9/00 , H03M7/30
CPC分类号： G06F7/785 , G06T9/005 , H03M7/3084 , H03M7/3088
摘要： A decoder for data encoded in a form combining a prefix which is a previously coded sub-string and a next data element in the data stream. The decoder includes memories for storing code words and data separately. Upon receipt of a code word the decoder stores the previously received code word, applies the newly received word to the code word memory to obtain the location of the last data element which is part of the data represented by the newly received code word, and another code word associated with the prefix. Upon completion of decoding the latest code word, the first data element of the decoded word is appended to the next previously received code word, and the combination is stored as the equivalent of a code word which is next after the highest code word already received. At least one memory is shared for use during encoding and decoding.
摘要翻译：一种解码器，用于以组合作为数据流中的先前编码的子串和下一个数据元素的前缀的形式进行编码的数据。解码器包括用于分别存储码字和数据的存储器。在接收到码字时，解码器存储先前接收到的码字，将新接收到的字应用于码字存储器，以获得作为由新接收的码字表示的数据的一部分的最后数据元素的位置，另一个与前缀关联的代码字。在完成对最新代码字的解码之后，解码字的第一数据元被附加到下一个先前接收到的代码字，并且该组合被存储为相当于已经接收的最高代码字之后的代码字。共享至少一个存储器以在编码和解码期间使用。

33. 发明授权

US5023828A Microinstruction addressing in high-speed CPU 失效
标题翻译：微指令寻址在高速CPU
公开(公告)号：US5023828A
公开(公告)日：1991-06-11
申请号：US221946
申请日：1988-07-20
申请人： William J. Grundmann , William C. Madden , George M. Uhler
发明人： William J. Grundmann , William C. Madden , George M. Uhler
IPC分类号： G06F7/78 , G06F9/22 , G06F9/26 , G06F9/30
CPC分类号： G06F7/785 , G06F9/26 , G06F9/265 , G06F9/30134
摘要： A memory stack used for storing microinstruction addresses in a pipelined CPU is constructed as a last-in, first-out memory using a stack pointer which applies a read control to one location of the stack and applies a write control to the next higher location. An unconditional read and write is done every machine cycle, before a microinstruction could be decoded, then the data on the read bus, or data from the write bus, is used and the pointer is incremented or decremented if a stack Push or Pop is decoded. These correspond to a Call or Return microinstruction. Thus the delay in decoding the microinstruction does not prevent completion of the stack operation in one machine cycle.

34. 发明授权

US4809156A Address generator circuit 失效
标题翻译：地址发生器电路
公开(公告)号：US4809156A
公开(公告)日：1989-02-28
申请号：US51173
申请日：1987-05-13
申请人： John E. Taber
发明人： John E. Taber
IPC分类号： G06F7/48 , G06F7/78 , G06F9/345 , G06F9/355 , G06F9/38 , G11C8/04 , G06F7/00 , G06F9/00
CPC分类号： G06F7/785 , G06F7/48 , G06F9/30167 , G06F9/345 , G06F9/355 , G06F9/3552 , G06F9/3879 , G11C8/04
摘要： A circuit for generating memory addresses for use in a computer system. The circuit includes multiple address register files that are usable to store parameters of multiple addressing sequences. Each address register file includes a base register for storing a base memory address, an accumulator register for storing a current address in the sequence, a displacement register for storing an address displacement to be used in conjunction with the accumulator register to produce the address sequence, an extension register used as an alternative displacement register, a count accumulator register to monitor a count of the address items in the sequence, and a count restore register used to store an original count for use at the end of the sequence. The circuit is responsive to a variety of commands to load and read the registers, and to manipulate them to provide a desired address sequence, which may be a modulo-N sequence useful in a variety of applications, such as accessing a matrix column-by-column when it is stored row-by-row.
摘要翻译：一种生成用于计算机系统的存储器地址的电路。该电路包括多个地址寄存器文件，可用于存储多个寻址序列的参数。每个地址寄存器文件包括用于存储基本存储器地址的基址寄存器，用于存储序列中的当前地址的累加器寄存器，用于存储与累加器寄存器一起使用以产生地址序列的地址位移的位移寄存器，用作替代位移寄存器的扩展寄存器，用于监视序列中地址项的计数的计数累加器寄存器，以及用于存储在序列结尾使用的原始计数的计数恢复寄存器。该电路响应于各种命令来加载和读取寄存器，并且操纵它们以提供期望的地址序列，其可以是在各种应用中有用的模N序列，诸如以矩阵方式访问矩阵列逐行存储。

35. 发明授权

US4692893A Buffer system using parity checking of address counter bit for detection of read/write failures 失效
标题翻译：缓冲系统使用地址计数器位的奇偶校验来检测读/写失败
公开(公告)号：US4692893A
公开(公告)日：1987-09-08
申请号：US685514
申请日：1984-12-24
申请人： Daniel F. Casper
发明人： Daniel F. Casper
IPC分类号： G06F5/06 , G06F5/10 , G06F7/78 , G06F11/10 , H04L13/08
CPC分类号： G06F7/785 , G06F11/1008 , G06F11/1076 , G06F5/10
摘要： A data buffer has a storage array that is addressable for read and write operations by an address of n bits that are supplied by a read address counter and a write address counter that each have n+1 bits. The n+1th bit is in effect a counter for passes through the array by the read and write circuits. During a write operation the n+1th bit of the write counter is stored as part of a parity bit for the addressed array location. During a read operation the n+1th bit of the read address counter is entered into a parity checking function on the word read from the addressed location. An errror is signaled if the n+1th bit of the read address counter does not agree with the n+1th bit of the write counter at the time of the write operation. For example, an error is detected if the write circuits fail and the read circuits make a second pass through words that have previously been read. The same entries on a next pass through the array.
摘要翻译：数据缓冲器具有存储阵列，可通过由读地址计数器和每个具有n + 1位的写地址计数器提供的n位的地址进行读和写操作。第n + 1位实际上是读和写电路通过阵列的计数器。在写操作期间，写计数器的第n + 1位被存储为寻址的阵列位置的奇偶校验位的一部分。在读取操作期间，读地址计数器的第n + 1位被输入到从寻址位置读取的字上的奇偶校验功能。如果读地址计数器的第n + 1位与写操作时的写计数器的第n + 1位不一致，则发出错误信号。例如，如果写入电路出现故障，并且读取电路再次通过先前已被读取的字，则检测到错误。下一次通过数组的相同条目。

36. 发明授权

US4535420A Circular-queue structure 失效
标题翻译：循环队列结构
公开(公告)号：US4535420A
公开(公告)日：1985-08-13
申请号：US389823
申请日：1982-06-18
申请人： Anthony K. Fung
发明人： Anthony K. Fung
IPC分类号： G06F7/78 , G06F15/167 , G06F11/00
CPC分类号： G06F7/785 , G06F15/167
摘要： Apparatus for producing a circular-queue structure which permits interfacing between a high speed mini-computer and a relatively slow speed microprocessor via a common memory and with multi-device, asynchronous handling capability. The structure also permits commands and data to be chained in the same queue. The apparatus permits multiple devices to be handled simultaneously. By monitoring the memory address which is being accessed by the minicomputer, the information retrieved from the memory by the microprocessor is selectively validated or invalidated.
摘要翻译：用于产生循环队列结构的装置，其允许通过公共存储器和多设备异步处理能力在高速微型计算机和相对慢速的微处理器之间进行接口。该结构还允许将命令和数据链接在同一个队列中。该设备允许同时处理多个设备。通过监视由小型计算机访问的存储器地址，由微处理器从存储器检索的信息被选择性地验证或无效。

37. 发明授权

US4405936A Method of and arrangement for digitizing a color video signal 失效
标题翻译：彩色视频信号数字化的方法和装置
公开(公告)号：US4405936A
公开(公告)日：1983-09-20
申请号：US288231
申请日：1981-07-27
申请人： Joseph H. Peters
发明人： Joseph H. Peters
IPC分类号： G06F7/78 , H04N11/04 , H04N9/32
CPC分类号： G06F7/785 , H04N11/044
摘要： In order to obtain a reduction of the bit rate when digitizing a color video signal using a picture transform, the color video signal is sampled with a frequency which is twice the color auxiliary carrier frequency. The video signal samples thus obtained are assembled into two-dimensional subpictures each comprising P consecutive video signal samples of each time Q consecutive line signals. Each subpicture can be considered as the sum of a series of superposed basic pictures, each having its own coefficient (which is a weighting factor representing the contribution of the basic picture in the subpicture). Each coefficient is encoded with a number of bits assigned thereto. The basic pictures are assembled from picture squares which are either of a first type (completely white) or a second type (completely black). The Hadamard matrix transform determines the basic picture patterns. Each of the two color information signals u(t) and v(t) in the color video signal now contributes to a subpicture in such a way that this contribution can be fully described by one basic picture. Only the coefficients associated with these basic pictures need not be encoded accurately.
摘要翻译：为了在使用图像变换数字化彩色视频信号时获得比特率的降低，以彩色辅助载波频率的两倍的频率对彩色视频信号进行采样。这样获得的视频信号样本被组装成每个包括每个Q个连续线信号的P个连续视频信号样本的二维子图。每个子画面可以被认为是一系列叠加的基本画面的和，每一个都具有其自己的系数（其是表示子画面中的基本画面的贡献的加权因子）。每个系数用分配给它的多个比特进行编码。基本图片是由第一类（完全白色）或第二类型（完全黑色）的图片正方形组合而成。 Hadamard矩阵变换确定基本图像模式。彩色视频信号中的两个颜色信息信号u（t）和v（t）中的每一个现在有助于子图像，使得该贡献可以由一个基本图像完全描述。只有与这些基本图像相关联的系数不需要被准确地编码。

38. 发明授权

US4302775A Digital video compression system and methods utilizing scene adaptive coding with rate buffer feedback 失效
标题翻译：数字视频压缩系统和利用速率缓冲器反馈的场景自适应编码的方法
公开(公告)号：US4302775A
公开(公告)日：1981-11-24
申请号：US969991
申请日：1978-12-15
申请人： Robert D. Widergren , Wen-Hsiung Chen , Stanley C. Fralick , Andrew G. Tescher
发明人： Robert D. Widergren , Wen-Hsiung Chen , Stanley C. Fralick , Andrew G. Tescher
IPC分类号： G06F7/78 , G06T9/00 , H04N7/26 , H04N7/30 , H04N7/32 , H04N11/04 , H04N7/12 , G06F15/20 , G08C9/00 , H04N9/32
CPC分类号： G06F7/785 , H04N11/044 , H04N19/126 , H04N19/152 , H04N19/176 , H04N19/186 , H04N19/196 , H04N19/197 , H04N19/423 , H04N19/60 , H04N19/88 , H04N19/124 , H04N19/146 , H04N19/30 , H04N19/50
摘要： A digital video compression system and its methods for compressing digitalized video signals in real time at rates up to NTSC color broadcast rates are disclosed. The system compressor receives digitalized video frames divided into subframes, performs in a single pass a spatial domain to transform domain transformation in two dimensions of the picture elements of each subframe, normalizes the resultant coefficients by a normalization factor having a predetermined compression ratio component and an adaptive rate buffer capacity control feedback component, to provide compression, encodes the coefficients and stores them in a first rate buffer memory asynchronously at a high data transfer rate from which they are put out at a slower, synchronous rate. The compressor adaptively determines the rate buffer capacity control feedback component in relation to instantaneous data content of the rate buffer memory in relation to its capacity, and it controls the absolute quantity of data resulting from the normalization step so that the buffer memory is never completely emptied and never completely filled. In expansion, the system essentially mirrors the steps performed during compression. An efficient, high speed decoder forms an important aspect of the present invention. The compression system forms an important element of a disclosed color broadcast compression system.
摘要翻译：公开了一种数字视频压缩系统及其用于以NTSC彩色广播速率的速率实时压缩数字化视频信号的方法。系统压缩器接收被划分为子帧的数字化视频帧，单次执行空间域以在每个子帧的像素的二维中变换域变换，通过具有预定压缩比分量的归一化因子对所得到的系数进行归一化，自适应速率缓冲器容量控制反馈分量，以提供压缩，对系数进行编码，并以高数据传输速率异步地将它们存储在第一速率缓冲存储器中，从而以较慢的同步速率将其推出。压缩机相对于其容量自适应地确定速率缓冲器容量控制反馈分量与速率缓冲存储器的瞬时数据内容的关系，并且控制由归一化步骤产生的数据的绝对数量，使得缓冲存储器从不完全清空并从未完全填满。在扩展中，系统基本上反映了压缩期间执行的步骤。有效的高速解码器形成本发明的重要方面。压缩系统形成所公开的彩色广播压缩系统的重要元件。

39. 发明授权

US3786432A Push-pop memory stack having reach down mode and improved means for processing double-word items 失效
标题翻译：具有下降模式的PUSH-POP存储堆栈和用于处理双字词项目的改进手段
公开(公告)号：US3786432A
公开(公告)日：1974-01-15
申请号：US3786432D
申请日：1972-06-20
申请人： HONEYWELL INF SYSTEMS
发明人： WOODS W
IPC分类号： G06F7/00 , G06F7/78 , G06F9/34 , G11C7/00 , G06F9/20
CPC分类号： G06F7/785
摘要： A first in-last out (i.e. push-pop, push-down, or last in-first out) memory stack is implemented with means for reaching down into the stack without pushing or popping thereby allowing access to information which would not otherwise be immediately available. The stack also features improved processing of doubleword items by use of unique double push and double pop algorithms.
摘要翻译：实现了先进先出（即推，弹，下，先进先出）存储器堆栈的手段，用于在不推动或弹出的情况下进入堆栈，从而允许访问否则将立即消除的信息可用。该堆栈还通过使用独特的双推和双弹出算法来改进对双字项目的处理。

40. 发明授权

US09083725B2 System and method providing hierarchical cache for big data applications 有权
标题翻译：为大数据应用提供分层缓存的系统和方法
公开(公告)号：US09083725B2
公开(公告)日：2015-07-14
申请号：US14531171
申请日：2014-11-03
申请人： Fred Korangy , Hamed Ghasemzadeh , Mohsen Arjmandi , Reza Azmi
发明人： Fred Korangy , Hamed Ghasemzadeh , Mohsen Arjmandi , Reza Azmi
IPC分类号： G06F15/16 , H04L29/08 , G06F7/527 , G06F7/78
CPC分类号： H04L67/1097 , G06F7/5272 , G06F7/785 , H04L67/1095
摘要： The embodiments herein develop a system for providing hierarchical cache for big data processing. The system comprises a caching layer, a plurality of actors in communication with the caching layer, a machine hosting the plurality of actors, a plurality of replication channels in communication with the plurality of actors, a predefined ring structure. The caching layer is a chain of memory and storage capacity elements, configured to store a data from the input stream. The plurality of actors is configured to replicate the input data stream and forward the replicated data to the caching layer. The replication channels are configured to forward the replicated data from a particular actor to another actor. The predefined ring structure maps the input data to the replica actors.
摘要翻译：本文的实施例开发了一种用于为大数据处理提供分层缓存的系统。该系统包括缓存层，与缓存层通信的多个角色，承载多个角色的机器，与多个角色通信的多个复制频道，预定义的环形结构。缓存层是存储器和存储容量元件链，被配置为存储来自输入流的数据。多个演员被配置为复制输入数据流并将复制的数据转发到缓存层。复制通道配置为将复制数据从特定演员转发到另一个演员。预定义的环结构将输入数据映射到副本演员。

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