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1. 发明授权

US5023828A Microinstruction addressing in high-speed CPU 失效
标题翻译：微指令寻址在高速CPU
公开(公告)号：US5023828A
公开(公告)日：1991-06-11
申请号：US221946
申请日：1988-07-20
申请人： William J. Grundmann , William C. Madden , George M. Uhler
发明人： William J. Grundmann , William C. Madden , George M. Uhler
IPC分类号： G06F7/78 , G06F9/22 , G06F9/26 , G06F9/30
CPC分类号： G06F7/785 , G06F9/26 , G06F9/265 , G06F9/30134
摘要： A memory stack used for storing microinstruction addresses in a pipelined CPU is constructed as a last-in, first-out memory using a stack pointer which applies a read control to one location of the stack and applies a write control to the next higher location. An unconditional read and write is done every machine cycle, before a microinstruction could be decoded, then the data on the read bus, or data from the write bus, is used and the pointer is incremented or decremented if a stack Push or Pop is decoded. These correspond to a Call or Return microinstruction. Thus the delay in decoding the microinstruction does not prevent completion of the stack operation in one machine cycle.

2. 发明授权

US4910713A High input impedance, strobed CMOS differential sense amplifier 失效
标题翻译：高输入阻抗，选通CMOS差分读出放大器
公开(公告)号：US4910713A
公开(公告)日：1990-03-20
申请号：US212346
申请日：1988-06-27
申请人： William C. Madden , William J. Bowhill
发明人： William C. Madden , William J. Bowhill
IPC分类号： G11C11/419
CPC分类号： G11C11/419
摘要： A general purpose sense amplifier, suited for memory and level shifting applications, is provided. The present invention provides a high input impedence for less loading of bit line voltages, wherein operation is relatively insensitive to capacitive mismatches on input bit line pairs. Inherent in the high input impedence design is the built-in isolation between input and output circuitry. The present invention also provides a full rail to rail separation of the output bit line voltages without requiring additional pull-up or pull-down circuitry. The present invention also provides a single strobing input for activating and deactivating the sense amplifier. The present invention also provides minimal circuitry with high speed characteristics and low power dissipation.
摘要翻译：提供了适用于存储器和电平转换应用的通用读出放大器。本发明提供了用于较少负载位线电压的高输入阻抗，其中操作对输入位线对上的电容失配相对不敏感。在高输入阻抗设计中固有的是输入和输出电路之间的内置隔离。本发明还提供了输出位线电压的完全轨到轨分离，而不需要额外的上拉或下拉电路。本发明还提供用于激活和去激活读出放大器的单个选通输入。本发明还提供具有高速特性和低功耗的最小电路。

3. 发明授权

US5341319A Method and apparatus for controlling a rounding operation in a floating point multiplier circuit 失效
标题翻译：用于控制浮点乘法器电路中的舍入操作的方法和装置
公开(公告)号：US5341319A
公开(公告)日：1994-08-23
申请号：US016058
申请日：1993-02-10
申请人： William C. Madden , Vidya Rajagopalan , Sridhar Samudrala
发明人： William C. Madden , Vidya Rajagopalan , Sridhar Samudrala
IPC分类号： G06F7/487 , G06F7/52 , G06F7/38
CPC分类号： G06F7/4876 , G06F7/49952
摘要： A floating point multiply of two n-bit operands creams a 2n-bit result, but ordinarily only n-bit precision is needed, so rounding is performed. Some rounding algorithms require the knowledge of the presence of any "1" in the n-2 low-order bits of the 2n-bit result. The presence of such a "1", indicates the so-called "sticky bit" is set. The sticky bit is calculated in a path separate from the multiply operation, so the n-2 least significant sums need not be calculated. This saves time and circuitry in an array multiplier, for example. In an example method, the difference between n and the number of trailing zeros, "x", in one of the n-bit operands is detected, by transposing the operand and detecting the leading one. The other operand is right-shifted by a number of bit positions equal to this difference. A sticky bit is generated if any logic "1's" are in the low-order n-x-2 bits fight shifted out of the second operand.
摘要翻译：两个n位操作数的浮点乘法使2n位结果出现，但通常只需要n位精度，因此执行舍入。一些舍入算法需要知道在2n位结果的n-2个低位中存在任何“1”。这样的“1”的存在表示所谓的“粘性位”被设定。在与乘法运算分离的路径中计算粘性位，因此不需要计算n-2个最小有效和。这样可以节省数组乘法器中的时间和电路。在一个示例方法中，通过转置操作数并检测前导码，检测n位操作数之一的n和尾数“x”之间的差异“x”。另一个操作数被右移位等于该差值的多个位位置。如果任何逻辑“1”处于从第二个操作数移出的低阶n-x-2位中，产生一个粘滞位。

4. 发明授权

US5155382A Two-stage CMOS latch with single-wire clock 失效
标题翻译：具有单线时钟的两级CMOS锁存器
公开(公告)号：US5155382A
公开(公告)日：1992-10-13
申请号：US832742
申请日：1992-02-07
申请人： William C. Madden , Vidya Rajagopalan
发明人： William C. Madden , Vidya Rajagopalan
IPC分类号： H03K3/356 , H03K3/3562
CPC分类号： H03K3/35625
摘要： A master/slave latch circuit employs a single-wire clock, with the clock being applied to only N-channel transistors in the master latch and to only P-channel transistors in the slave latch so that a race-through condition is alleviated in the event of clock skew. The circuits are of ratioless operation, since P-channel transistors are used in each circuit to pull the high side to the supply voltage, and N-channel transistors are used on the low side to assure a zero voltage level. Input to each latch is to the gates of a P-channel pull-up and an N-channel pull-down, while the storage node is between the two clocked transistors. The level of the storage node is inverted and fed back to at transistor across one of the clocked transistors, the one on the high side for the master latch and the low side for the slave latch, and these feedback transistors are of a channel type to support the ratioless scheme.
摘要翻译：主/从锁存电路采用单线时钟，时钟仅施加于主锁存器中的N沟道晶体管，并且仅施加于从锁存器中的P沟道晶体管，使得在时钟偏移事件。由于在每个电路中使用P沟道晶体管将高端拉到电源电压，所以这些电路是无竞争的操作的，并且在低端使用N沟道晶体管来确保零电压电平。每个锁存器的输入是P沟道上拉和N沟道下拉的栅极，而存储节点位于两个时钟晶体管之间。存储节点的电平被反相并且被反馈到晶体管，跨越时钟晶体管中的一个，主器件的高侧的晶体管和从锁存器的低电平，并且这些反馈晶体管是通道类型支持无限制方案。

5. 发明授权

US5119483A Application of state silos for recovery from memory management exceptions 失效
标题翻译：从内存管理异常中应用状态孤岛进行恢复
公开(公告)号：US5119483A
公开(公告)日：1992-06-02
申请号：US221944
申请日：1988-07-20
申请人： William C. Madden , Douglas E. Sanders , G. Michael Uhler , William R. Wheeler
发明人： William C. Madden , Douglas E. Sanders , G. Michael Uhler , William R. Wheeler
IPC分类号： G06F9/26 , G06F9/30 , G06F9/38 , G06F12/10
CPC分类号： G06F9/3867 , G06F9/26 , G06F9/30149 , G06F9/3863 , G06F12/10 , Y10S707/99939
摘要： To reduce the processing time required for correcting a fault, the instruction decorder segment and the first execution segment of a pipelined processor are provided with "state silos" that are operative during normal instruction execution to save a sufficient amount of state information to immediately restart the instruction decoder segment and the first execution segment by reloading the state information having been stored in the state silos. The state silos, for example, include a queue of registers clocked by a common clocking signal that is inhibited during correction of the fault. When the fault is corrected, multiplexers select the state information from the silos to be used by the respective pipeline segments. In a preferred embodiment, the instruction decoder segment decodes variable length macroinstructions into operand specifiers and operations to perform upon the specifiers. The first execution segment receives control information when a new operand specifier or operation is decoded, and otherwise holds the previously received control information. A microsequencer issues a series of microinstructions for each specifier or operation having been decoded, and also issues a series of microinstructions in a fault routine when a fault occurs. The microsequencer is also provided with a state silo so that the normal sequence of microinstruction execution is resumed when the fault is corrected.
摘要翻译：为了减少纠正故障所需的处理时间，流水线处理器的指令解码段和第一执行段被提供有在正常指令执行期间操作的“状态仓”以保存足够量的状态信息以立即重启指令解码器段和第一执行段，通过重新加载已经存储在状态列表中的状态信息。例如，状态孤岛包括由校正故障期间被禁止的公共时钟信号计时的寄存器队列。当故障被纠正时，多路复用器从相应流水线段使用的筒仓中选择状态信息。在优选实施例中，指令解码器段将可变长度宏指令解码为操作数说明符和在指定符上执行的操作。当新的操作数说明符或操作被解码时，第一执行段接收控制信息，否则保持先前接收到的控制信息。微定序器为每个说明符或操作已经解码了一系列微指令，并且在出现故障时也会在故障程序中发出一系列微指令。微定序器还设置有状态仓，使得当故障被校正时，微指令执行的正常序列被恢复。

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