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1. 发明授权

US5202678A Recognition unit 失效
标题翻译：识别单位
公开(公告)号：US5202678A
公开(公告)日：1993-04-13
申请号：US793212
申请日：1959-02-13
申请人： John E. Taber , Bernard H. Dell
发明人： John E. Taber , Bernard H. Dell
IPC分类号： H04L7/04 , H04L25/49
CPC分类号： H04L7/042 , H04L25/4904
摘要： An electronic recognition unit indicates that a flow of received information is starting when a desired bi-phased pulsed ratio signal starts to be received. The recognition unit discriminates against both noise and spurious radio signals. Desired signals are made recognizable by reversing, upon transmission, the phase of the carrier for a prescribed pattern of pulses. This technique prevents responding to unqualified continuous-wave signals. The relative phases of adjacent radio-frequency pulses of the desired pulse train convey the recognition information. When the phases of two adjacent pulses are the same a positive audio-pulse output is obtained, and if their phases differ by 180 degrees the output is negative. For a predetermined number of pulses, for example fourteen, the resulting positive and negative audio pulses are added in an audio delay circuit with appropriate inversion of the sign of the intentionally negative pulses. The procedure produces relatively large recognition signals, only when the incoming pulse train has the prescribed phase pattern.
摘要翻译：当期望的双相脉冲比信号开始被接收时，电子识别单元指示所接收信息的流程开始。识别单元鉴别噪声和杂散无线电信号。期望的信号通过在传输时反转载波的相位而使其可以被识别为规定的脉冲模式。这种技术防止响应不合格的连续波信号。期望的脉冲串的相邻射频脉冲的相对相位传达识别信息。当两个相邻脉冲的相位相同时，获得正音频脉冲输出，并且如果它们的相位相差180度，则输出为负。对于预定数量的脉冲，例如十四，所得到的正音频脉冲和负音频脉冲被加到具有有意负脉冲的符号的适当反转的音频延迟电路中。该过程产生相对较大的识别信号，只有当输入脉冲串具有规定的相位模式时。

2. 发明授权

US4809156A Address generator circuit 失效
标题翻译：地址发生器电路
公开(公告)号：US4809156A
公开(公告)日：1989-02-28
申请号：US51173
申请日：1987-05-13
申请人： John E. Taber
发明人： John E. Taber
IPC分类号： G06F7/48 , G06F7/78 , G06F9/345 , G06F9/355 , G06F9/38 , G11C8/04 , G06F7/00 , G06F9/00
CPC分类号： G06F7/785 , G06F7/48 , G06F9/30167 , G06F9/345 , G06F9/355 , G06F9/3552 , G06F9/3879 , G11C8/04
摘要： A circuit for generating memory addresses for use in a computer system. The circuit includes multiple address register files that are usable to store parameters of multiple addressing sequences. Each address register file includes a base register for storing a base memory address, an accumulator register for storing a current address in the sequence, a displacement register for storing an address displacement to be used in conjunction with the accumulator register to produce the address sequence, an extension register used as an alternative displacement register, a count accumulator register to monitor a count of the address items in the sequence, and a count restore register used to store an original count for use at the end of the sequence. The circuit is responsive to a variety of commands to load and read the registers, and to manipulate them to provide a desired address sequence, which may be a modulo-N sequence useful in a variety of applications, such as accessing a matrix column-by-column when it is stored row-by-row.
摘要翻译：一种生成用于计算机系统的存储器地址的电路。该电路包括多个地址寄存器文件，可用于存储多个寻址序列的参数。每个地址寄存器文件包括用于存储基本存储器地址的基址寄存器，用于存储序列中的当前地址的累加器寄存器，用于存储与累加器寄存器一起使用以产生地址序列的地址位移的位移寄存器，用作替代位移寄存器的扩展寄存器，用于监视序列中地址项的计数的计数累加器寄存器，以及用于存储在序列结尾使用的原始计数的计数恢复寄存器。该电路响应于各种命令来加载和读取寄存器，并且操纵它们以提供期望的地址序列，其可以是在各种应用中有用的模N序列，诸如以矩阵方式访问矩阵列逐行存储。

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