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1. 发明授权

US5339398A Memory architecture and method of data organization optimized for hashing 失效
标题翻译：数据组织的内存架构和方法优化哈希
公开(公告)号：US5339398A
公开(公告)日：1994-08-16
申请号：US913764
申请日：1992-07-14
申请人： Imran A. Shah , Brian C. Johnson
发明人： Imran A. Shah , Brian C. Johnson
IPC分类号： G06F17/30 , G06F12/02
CPC分类号： G06F17/30949
摘要： A hashing data storage and retrieval arrangement whose storage capacity is unaffected by collisions. A first memory serves as a hash index table, for storing pointers at each address location corresponding to a hash value generated by hashing a key data word. Each pointer is the address of a location in a second memory, which has a separate storage location for each key data word, its associated data, and a further pointer which is the address of the next key data word resulting from a collision during hashing. Preferably a pipeline register between the two memories permits hashing of a subsequent key data word while accessing of the second memory is still in progress.
摘要翻译：散列数据存储和检索布置，其存储容量不受碰撞影响。第一存储器用作散列索引表，用于存储与通过散列密钥数据字生成的散列值相对应的每个地址位置处的指针。每个指针是第二存储器中的位置的地址，其具有用于每个关键数据字及其关联数据的单独的存储位置，以及另外的指针，该指针是由于散列期间的碰撞产生的下一个关键数据字的地址。优选地，两个存储器之间的流水线寄存器允许随后的密钥数据字的散列，同时第二存储器的访问仍在进行中。

2. 发明授权

US5398315A Multi-processor video display apparatus 失效
标题翻译：多处理器视频显示设备
公开(公告)号：US5398315A
公开(公告)日：1995-03-14
申请号：US998358
申请日：1992-12-30
申请人： Brian C. Johnson , Michael A. Epstein
发明人： Brian C. Johnson , Michael A. Epstein
IPC分类号： G06F15/16 , G06F15/80 , G06T1/20 , H04N5/14 , H04N5/262 , G06F3/14
CPC分类号： H04N5/14
摘要： Video display apparatus having multiple processors for operation in parallel, each processing a respective complete video image in the sequence of video images (fields or frames) which form a video picture, the processing being in accordance with a selected signal processing algorithm. The algorithm may be one which simulates a signal processing circuit design which is to be evaluated, so that the effect of changes in circuit design can be displayed in real time. The signal data for each of the sequential video images is assembled into data packets in successive equal time slots, which are transmitted downstream on a data bus along which are a succession of data processors. The headers of the packets for a given image identify a serially corresponding processor to which such image is assigned, and such packets are processed by the assigned processor in accordance with the selected algorithm. If the processing time of each processor corresponds to the time period of N images, then by using N processors the nth processor will have completed processing of the nth complete image by the time of arrival of the (N+n) th image. Each series of N images can therefor be cyclically assigned to the series of processors, and are processed in parallel in real-time. Provision is made for inter-processor communication when the algorithm has temporal effects on the video picture which necessitate FIR or IIR filtering in order to display such effects.
摘要翻译：具有并行操作的多个处理器的视频显示装置，每个处理形成视频图像的视频图像（场或帧）的序列中的相应的完整视频图像，该处理根据所选择的信号处理算法。该算法可以是模拟要被评估的信号处理电路设计的算法，从而可以实时显示电路设计中的变化的影响。每个顺序视频图像的信号数据被组装成连续相等的时隙中的数据分组，这些时隙在数据总线上向下传送，数据总线沿着它们是一系列的数据处理器。用于给定图像的分组的报头标识分配了这种图像的串行对应的处理器，并且根据所选择的算法由分配的处理器处理这样的分组。如果每个处理器的处理时间对应于N个图像的时间段，则通过使用N个处理器，第n个处理器将在到达第（N + n）个图像时完成第n个完整图像的处理。每个N个图像系列可以循环地分配给一系列处理器，并且被实时并行处理。当算法对视频图像具有时效时，需要进行处理器间通信，这就需要FIR或IIR滤波才能显示这种效果。

3. 发明授权

US4465970A Method and apparatus for multiple rate metering of electrical energy 失效
标题翻译：电能多速率计量的方法和装置
公开(公告)号：US4465970A
公开(公告)日：1984-08-14
申请号：US578315
申请日：1984-02-10
申请人： Donald V. DiMassimo , John B. May , Brian C. Johnson , Jeffrey L. Cooper
发明人： Donald V. DiMassimo , John B. May , Brian C. Johnson , Jeffrey L. Cooper
IPC分类号： G01R21/133 , G01R15/08 , G01R11/64 , G06F15/20
CPC分类号： G01R21/1333
摘要： A programmable time-of-use metering system is disclosed for metering electrical energy consumption at multiple rates depending on the time of day, time of week and time of year in which the energy is being consumed. A method for registering total energy consumed by a metered system as well as energy consumed during preselected time intervals is also disclosed.
摘要翻译：公开了一种可编程的使用时间计量系统，用于以多个速率计量电能消耗，这取决于能量被消耗的一天中的时间，周的时间和年份的时间。还公开了一种用于记录计量系统消耗的总能量以及在预选时间间隔期间消耗的能量的方法。

4. 发明申请

US20160183878A1 TECHNOLOGIES FOR MANAGING DEVICE FUNCTIONS OF AN INGESTIBLE COMPUTING DEVICE 审中-公开
标题翻译：用于管理不可忽略的计算设备的设备功能的技术
公开(公告)号：US20160183878A1
公开(公告)日：2016-06-30
申请号：US14583705
申请日：2014-12-27
申请人： John C. Weast , Brian C. Johnson , Tobias M. Kohlenberg
发明人： John C. Weast , Brian C. Johnson , Tobias M. Kohlenberg
IPC分类号： A61B5/00 , A61B5/07
CPC分类号： A61B5/6861 , A61B5/073 , A61B5/4839 , A61B5/4848 , A61B5/7221 , A61B5/746 , A61B2560/0475 , A61B2560/0481 , A61B2562/08
摘要： Technologies for managing device functions of an ingestible computing device include determining whether adaptation of a device function of the ingestible computing device is required based on sensor data generated by the ingestible computing device. If device function adaption is determined to be required, the ingestible computing device determines a new device function to be performed, obtains program code modules to perform the new device function, and locally compiles the new program code modules to generate executable code. The ingestible computing device may execute the executable code to cause the ingestible computing device to begin performing the new device function. The ingestible computing device may obtain the program code modules from a local function database or via an authenticated wireless communication.
摘要翻译：用于管理可摄入计算设备的设备功能的技术包括基于可摄入计算设备生成的传感器数据来确定是否需要适应可摄入计算设备的设备功能。如果确定需要设备功能适应，则可摄取计算设备确定要执行的新设备功能，获得执行新设备功能的程序代码模块，并且本地编译新的程序代码模块以生成可执行代码。可摄入计算设备可以执行可执行代码以使可摄入计算设备开始执行新的设备功能。可摄取计算设备可以从本地功能数据库或经由认证的无线通信获得程序代码模块。

5. 发明授权

US5034907A Dynamically configurable signal processor and processor arrangement 失效
标题翻译：动态配置信号处理器和处理器布置
公开(公告)号：US5034907A
公开(公告)日：1991-07-23
申请号：US614043
申请日：1990-11-09
申请人： Brian C. Johnson , Carlo Basile , Amihai Miron , Neil H. E. Weste , Christopher J. Terman , Judson Leonard
发明人： Brian C. Johnson , Carlo Basile , Amihai Miron , Neil H. E. Weste , Christopher J. Terman , Judson Leonard
IPC分类号： G06F7/544 , G06F15/78
CPC分类号： G06F15/7867 , G06F7/5443
摘要： A programmable digital signal processor usable in a variety of configurations and controlled by stored coefficients and control words which are addressable to be provided to a plurality of processing sections as often as once per clock cycle. The processor arrangement is suitable for use as a decoder of multiple analog component (MAC) television signals.
摘要翻译：一种可编程数字信号处理器，可用于各种配置并由可存储的系数和控制字控制，可被寻址以每时钟周期一次提供给多个处理部分。处理器布置适合用作多个模拟分量（MAC）电视信号的解码器。

6. 发明授权

US4542407A Method and apparatus for scrambling and descrambling television programs 失效
标题翻译：用于扰频和解扰电视节目的方法和装置
公开(公告)号：US4542407A
公开(公告)日：1985-09-17
申请号：US503208
申请日：1983-06-10
申请人： Jeffrey L. Cooper , Brian C. Johnson
发明人： Jeffrey L. Cooper , Brian C. Johnson
IPC分类号： H04N7/167 , H04N7/171 , H04N7/16
CPC分类号： H04N7/1675 , H04N7/1713
摘要： A method for scrambling and descrambling television programs in which the horizontal synchronizing information is suppressed at a CATV supplier's head-end and then regenerated at the subscriber's converter. The pulse frequency is multiplied by a factor N/M, in which N and M are integers thereby generating a synthesized pulse stream which is, in turn, encoded with data identifying the values for N and M. This encoded pulse stream is modulated onto the audio subcarrier wave in the TV video signal and transmitted to the converter. The converter then demodulates and recovers the encoded pulse stream, decodes the same to recover the identifying data, using this data to obtain the correct values for N and M which have been transmitted separately on a digital data channel. The converter then multiplies the synthesized pulse stream by M/N regenerating the horizontal synchronizing pulse stream and inserts the same into the TV video signal at the proper phase.
摘要翻译：一种用于加扰和解扰电视节目的方法，其中水平同步信息在CATV供应商的头端被抑制，然后在用户转换器处再生。脉冲频率乘以因子N / M，其中N和M是整数，从而产生合成脉冲流，该合成脉冲流又被用于识别N和M的值的数据编码。该编码脉冲流被调制到音频副载波在TV视频信号中发送并传输到转换器。然后，转换器解调并恢复编码的脉冲流，对其进行解码以恢复识别数据，使用该数据来获得在数字数据信道上分别发送的N和M的正确值。然后，转换器将合成脉冲流乘以M / N再生水平同步脉冲流，并将其插入到适当阶段的TV视频信号中。

7. 发明授权

US5113516A Data repacker having controlled feedback shifters and registers for changing data format 失效
标题翻译：数据重新包装器具有控制的反馈移位器和寄存器来改变数据格式
公开(公告)号：US5113516A
公开(公告)日：1992-05-12
申请号：US388281
申请日：1989-07-31
申请人： Brian C. Johnson
发明人： Brian C. Johnson
IPC分类号： G06F7/78 , H03M7/30
CPC分类号： G06F7/785 , H03M7/3084 , H03M7/3088
摘要： A data repacker utilizing a multiplexer, one intermediate register, two shifters, and a control for these circuits. The multiplexer output is connected to the intermediate register, which has a storage length greater than the size of data words to be repacked. The first shifter receives the output of the register, and its output can be concatenated with an input data word to form one input to the multiplexer. The output of the register is provided as another input to the multiplexer. The second shifter also receives the output of the multiplexer, and has an output which is the repacker output. Information representing the number of bits in and the number of bits out is used to determine the most and least significant bits of the intermediate data which will be stored in the intermediate register, and to control the shifters.
摘要翻译：一种利用多路复用器，一个中间寄存器，两个移位器和这些电路的控制的数据重新装载机。多路复用器输出连接到中间寄存器，该寄存器的存储长度大于要重新打包的数据字的大小。第一移位器接收寄存器的输出，并且其输出可以与输入数据字连接，以形成多路复用器的一个输入。寄存器的输出被提供给多路复用器的另一个输入。第二移位器还接收多路复用器的输出，并且具有作为再分配器输出的输出。表示位数和信号数的信息用于确定将存储在中间寄存器中的中间数据的最高有效位和最低有效位，并控制移位器。

8. 发明授权

US4493032A Method and apparatus for positioning using circular interpolation 失效
标题翻译：使用圆弧插补定位的方法和装置
公开(公告)号：US4493032A
公开(公告)日：1985-01-08
申请号：US415745
申请日：1982-09-07
申请人： Brian C. Johnson
发明人： Brian C. Johnson
IPC分类号： G05B19/4103 , G05B19/25
CPC分类号： G05B19/4103
摘要： A method and apparatus are disclosed for providing very precise incremental motion of a numerically controlled machine tool, or other similarly controlled object, along a circularly arced path. For a mutually perpendicular X and Y coordinate system, X and Y indices are determined based on certain prescribed input information related to the parameters of the circular path and the relative rate of motion between the machine tool and the workpiece, and on immediate, continuously recomputed, coordinates of the tool or object. The indices are each scaled by a modulus related to the radius of the arc to generate incremental distances .DELTA.X and .DELTA.Y according to which the next move is to be made. The process is reiterated until the desired circular path is complete. In both method and apparatus, only integer values of .DELTA.X and .DELTA.Y are used for implementing each increment of motion. Non-integer values are carried forward to the next iteration of the process to prevent error accumulation.
摘要翻译：公开了一种方法和装置，用于沿圆弧路径提供数控机床或其他类似受控对象的非常精确的增量运动。对于相互垂直的X和Y坐标系，X和Y指数根据与圆轨迹参数和机床与工件之间的相对运动速度相关的特定规定输入信息确定，并立即连续重新计算，工具或对象的坐标。这些索引各自用与弧的半径相关的模量缩放以产生增量距离DELTA X和DELTA Y，根据该距离将进行下一个移动。重复该过程，直到所需的循环路径完成。在这两种方法和装置中，仅使用DELTA X和DELTA Y的整数值来实现每个运动增量。非整数值被转发到进程的下一次迭代，以防止错误累积。

9. 发明授权

US4393501A Line protocol for communication system 失效
标题翻译：通讯系统线路协议
公开(公告)号：US4393501A
公开(公告)日：1983-07-12
申请号：US238205
申请日：1981-02-26
申请人： Richard A. Kellogg , John B. May , Brian C. Johnson
发明人： Richard A. Kellogg , John B. May , Brian C. Johnson
IPC分类号： G08C19/00 , G01R21/00 , H02J13/00 , H04B10/00 , H04L5/16 , H04L25/49 , H04L29/00 , H04Q9/14 , G06F11/10
CPC分类号： G01R21/00 , H02J13/0031 , H04L25/4902 , H04L5/16 , Y02E60/7892 , Y04S40/146
摘要： In a communication system, a line protocol format with a variable bit rate and low bit overhead provides for the high integrity, synchronous exchange of digital signal information between master and slave processing units, with master processing unit controlling the line protocol.
摘要翻译：在通信系统中，具有可变比特率和低位开销的线路协议格式提供主处理单元与从属处理单元之间数字信号信息的高完整性，同步交换，主处理单元控制线路协议。

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