专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明申请

US20090079005A1 Integrated Circuits and Methods of Design and Manufacture Thereof 有权
标题翻译：集成电路及其设计和制造方法
公开(公告)号：US20090079005A1
公开(公告)日：2009-03-26
申请号：US11860955
申请日：2007-09-25
申请人： Henning Haffner , Manfred Eller , Richard Lindsay
发明人： Henning Haffner , Manfred Eller , Richard Lindsay
IPC分类号： H01L29/76 , B44C1/22 , G06F17/50 , H01L21/3205 , H01L21/76
CPC分类号： G06F17/5072 , G03F1/00 , G06F2217/12 , H01L21/0334 , H01L21/28123 , H01L21/823425 , H01L21/823437 , H01L27/0207 , H01L27/082 , H01L27/085 , H01L27/088 , H01L29/6659 , H01L29/7833 , Y10T29/41
摘要： Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.
摘要翻译：公开了集成电路及其制造和设计方法。例如，制造方法包括使用第一掩模对形成多个第一和第二特征的栅极材料进行图案化。第一特征形成半导体器件的栅电极，而第二特征是虚拟电极。基于这些虚拟电极的位置，使用第二掩模去除所选择的虚拟电极。该方法的使用提供了更大的灵活性，为不同的目标定制单个设备。

32. 发明申请

US20080076036A1 Mask and method for patterning a semiconductor wafer 有权
标题翻译：用于图案化半导体晶片的掩模和方法
公开(公告)号：US20080076036A1
公开(公告)日：2008-03-27
申请号：US11527075
申请日：2006-09-26
申请人： Henning Haffner
发明人： Henning Haffner
IPC分类号： G03C5/00 , G03F1/00
CPC分类号： G03F7/70441 , G03F1/30 , G03F1/36 , G03F7/70433
摘要： A mask and method for patterning a semiconductor wafer is disclosed. A mask set is fabricated on a transparent substrate. A mask layer comprising mask region elements that transmit light is disposed on the substrate, wherein each mask element is segmented into a plurality of segments.
摘要翻译：公开了用于图案化半导体晶片的掩模和方法。在透明基板上制作掩模组。包含透光的掩模区域元件的掩模层设置在基板上，其中每个掩模元件被分割成多个段。

33. 发明授权

US07304721B2 Method for dynamically monitoring a reticle 有权
标题翻译：动态监控光罩的方法
公开(公告)号：US07304721B2
公开(公告)日：2007-12-04
申请号：US10984797
申请日：2004-11-10
申请人： Henning Haffner , Karin Eggers , Norbert Haase , Andreas Frangen , Carmen Jaehnert
发明人： Henning Haffner , Karin Eggers , Norbert Haase , Andreas Frangen , Carmen Jaehnert
IPC分类号： G01N21/00
CPC分类号： G01N21/95692 , G01N2021/95676 , G03F1/84
摘要： The method of dynamically monitoring a reticle includes preventively macro monitoring and defect inspecting with regard to mechanical loading, including particle deposits or electrostatically induced damage, and energy load, including the associated changes to the reticle material and surface characteristics. Different surface distributions of the absorber layer as well as characteristics of the exposure system, such as N2 purging of the projection lens/reticle area in order to reduce contamination and recrystallization on optically active surfaces are considered.
摘要翻译：动态监测掩模版的方法包括对机械载荷（包括颗粒沉积物或静电诱发的损伤）以及能量负载（包括对掩模版材料的相关变化和表面特性）的预防性宏观监测和缺陷检查。考虑吸收层的不同表面分布以及曝光系统的特性，例如投影透镜/掩模版区域的N 2清洗，以减少光学活性表面上的污染和重结晶。

34. 发明申请

US20050090925A1 Method and device for control of the data flow on application of reticles in a semiconductor component production 审中-公开
标题翻译：用于控制在半导体部件生产中应用掩模版时的数据流的方法和装置
公开(公告)号：US20050090925A1
公开(公告)日：2005-04-28
申请号：US10488486
申请日：2002-08-28
申请人： Thomas Albrecht , Norbert Haase , Henning Haffner , Carmen Jahnert , Olaf Kronefeld , Manfred Stiegler
发明人： Thomas Albrecht , Norbert Haase , Henning Haffner , Carmen Jahnert , Olaf Kronefeld , Manfred Stiegler
IPC分类号： G03F1/00 , G03F7/20 , H01L21/027 , G03F9/00 , G06F19/00
CPC分类号： G03F1/84 , G03F7/70525 , G03F7/70541 , G03F7/70741
摘要： A reticle control system and method in which each reticle is unambiguously assigned a structured reticle data set, and the content of each reticle data set is automatically changed and/or supplemented depending on use of the associated reticle in the semiconductor component production process for which the reticle was produced. The reticle data set is used to identify and control the reticles over the entire production sequence. The ability to change or supplement the reticle data sets facilitates progressively storing production-dictated information related to the use of the associated reticles, thereby enabling effective control of the reticles in the production process.
摘要翻译：一种掩模版控制系统和方法，其中每个掩模版被明确地分配结构化掩模版数据集，并且每个掩模版数据集的内容根据半导体部件生产过程中相关联的掩模版的使用自动地改变和/或补充，制作掩模版。掩模版数据集用于在整个生产序列上识别和控制光罩。改变或补充标线数据集的能力有助于逐渐地存储与使用相关联的掩模版有关的生产规定的信息，从而能够在生产过程中有效地控制标线。

35. 发明授权

US06571383B1 Semiconductor device fabrication using a photomask designed using modeling and empirical testing 有权
标题翻译：使用建模和经验测试设计的光掩模的半导体器件制造
公开(公告)号：US06571383B1
公开(公告)日：2003-05-27
申请号：US09562700
申请日：2000-04-28
申请人： Shahid Butt , Henning Haffner , Beate Frankowsky
发明人： Shahid Butt , Henning Haffner , Beate Frankowsky
IPC分类号： G06F1750
CPC分类号： G03F1/68 , G03F1/36 , G03F1/44 , Y10S977/839 , Y10S977/887
摘要： A method of fabricating a semiconductor device is outlined in FIG. 3. An ideal (or desired) pattern of a layer of the semiconductor device is designed (305). A first pass corrected pattern is then derived by correcting the ideal patterns for major effects, e.g., aerial image effects (315, 320). A second pass corrected pattern is then derived by correcting the first pass corrected patterns for remaining errors (304). The second pass corrected pattern can be used to build a photomask (345). The photomask can then be used to produce a semiconductor device, such a memory chip or logic chip (350).
摘要翻译：制造半导体器件的方法在图1中概述。设计半导体器件层的理想（或期望）图案（305）。然后通过校正主要效果（例如，空中影像效果）的理想图案（315,320）来导出第一通过校正图案。然后通过校正剩余错误的第一遍校正图案来导出第二遍校正图案（304）。第二遍校正图案可用于构建光掩模（345）。然后可以使用光掩模来制造半导体器件，诸如存储芯片或逻辑芯片（350）。

36. 发明授权

US06421820B1 Semiconductor device fabrication using a photomask with assist features 失效
标题翻译：使用具有辅助功能的光掩模的半导体器件制造
公开(公告)号：US06421820B1
公开(公告)日：2002-07-16
申请号：US09460034
申请日：1999-12-13
申请人： Scott M. Mansfield , Lars W. Liebmann , Shahid Butt , Henning Haffner
发明人： Scott M. Mansfield , Lars W. Liebmann , Shahid Butt , Henning Haffner
IPC分类号： G06F1750
CPC分类号： G03F1/36 , G03F7/70441
摘要： A semiconductor device can be fabricated using a photomask that has been modified using an assist feature design method (see e.g., FIG. 4A) based on normalized feature spacing. Before the device can be fabricated, a layout of original shapes is designed (402). For at least some of the original shapes, the width of the shape and a distance to at least one neighboring shape are measured (404). A modified shape can then be generated by moving edges of the original shape based on the width and distance measurements (406). This modification can be performed on some or all of the original shapes (408). For each of the modified shapes, a normalized space and correct number of assist features can be computed (410). The layout is then modified by adding the correct number of assist features in a space between the modified shape and the neighboring shape (412). This modified layout can then be used in producing a photomask, which can in turn be used to produce a semiconductor device.
摘要翻译：可以使用已经基于归一化特征间隔使用辅助特征设计方法（参见例如图4A）修改的光掩模来制造半导体器件。在可以制造设备之前，设计原始形状的布局（402）。对于至少一些原始形状，测量形状的宽度和至少一个相邻形状的距离（404）。然后可以通过基于宽度和距离测量来移动原始形状的边缘来生成修改的形状（406）。可以对部分或全部原始形状执行该修改（408）。对于每个修改的形状，可以计算归一化空间和正确数量的辅助特征（410）。然后通过在修改的形状和相邻形状之间的空间中添加正确数量的辅助特征来修改布局（412）。然后，该修改后的布局可用于制造光掩模，光掩模又可用于制造半导体器件。

37. 发明授权

US06353248B1 Optimized decoupling capacitor using lithographic dummy filler 有权
标题翻译：使用光刻虚拟填料的优化去耦电容器
公开(公告)号：US06353248B1
公开(公告)日：2002-03-05
申请号：US09562220
申请日：2000-04-28
申请人： Armin M Reith , Louis Hsu , Henning Haffner , Gunther Lehmann
发明人： Armin M Reith , Louis Hsu , Henning Haffner , Gunther Lehmann
IPC分类号： H01L2976
CPC分类号： H01L28/40 , H01L27/10861 , H01L27/10894 , H01L27/10897
摘要： A method to optimize the size and filling of decoupling capacitors for very large scale integrated circuits (VLSI) using existing lithographic fillers. The method combines the automatic or manual generation of lithographic fill patterns with the forming of the capacitors. According to the method, when the chip layout is about to be finished, all remaining empty space on the chip gets identified by a layout tool. Then, the closest power-supply nets get extracted. All power supplies and their combinations are sorted in a connection table which determines the appropriate types of capacitances once the power-supply nets closest to the empty spaces extracted from the layout. The empty spaces are then assigned appropriate decoupling capacitances. Decoupling capacitors generated by the method are suitable for VLSI power supplies for noise reduction.
摘要翻译：使用现有的平版印刷填料，优化大型集成电路（VLSI）的去耦电容的尺寸和填充的方法。该方法将自动或手动生成光刻填充图案与电容器的形成相结合。根据该方法，当芯片布局即将完成时，芯片上的所有剩余空间都由布局工具识别。然后，最近的电源网络被提取。所有电源及其组合在连接表中排序，一旦电源网最接近从布局提取的空白空间中，则确定适当类型的电容。然后空的空间被分配适当的去耦电容。通过该方法产生的去耦电容适用于降低噪声的VLSI电源。

38. 发明授权

US06232154B1 Optimized decoupling capacitor using lithographic dummy filler 有权
标题翻译：使用光刻虚拟填料的优化去耦电容器
公开(公告)号：US06232154B1
公开(公告)日：2001-05-15
申请号：US09442890
申请日：1999-11-18
申请人： Armin M. Reith , Louis Hsu , Henning Haffner , Gunther Lehmann
发明人： Armin M. Reith , Louis Hsu , Henning Haffner , Gunther Lehmann
IPC分类号： H01L2182
CPC分类号： H01L28/40 , H01L27/10861 , H01L27/10894 , H01L27/10897
摘要： A method to optimize the size and filling of decoupling capacitors for very large scale integrated circuits (VLSI) using existing lithographic fillers. The method combines the automatic or manual generation of lithographic fill patterns with the forming of the capacitors. According to the method, when the chip layout is about to be finished, all remaining empty space on the chip gets identified by a layout tool. Then, the closest power-supply nets get extracted. All power supplies and their combinations are sorted in a connection table which determines the appropriate types of capacitances once the power-supply nets closest to the empty spaces extracted from the layout. The empty spaces are then assigned appropriate decoupling capacitances. Decoupling capacitors generated by the method are suitable for VLSI power supplies for noise reduction.
摘要翻译：使用现有的平版印刷填料，优化大型集成电路（VLSI）的去耦电容的尺寸和填充的方法。该方法将自动或手动生成光刻填充图案与电容器的形成相结合。根据该方法，当芯片布局即将完成时，芯片上剩余的空余空间由布局工具识别。然后，最近的电源网络被提取。所有电源及其组合在连接表中排序，一旦电源网最接近从布局提取的空白空间中，则确定适当类型的电容。然后空的空间被分配适当的去耦电容。通过该方法产生的去耦电容适用于降低噪声的VLSI电源。

39. 发明申请

US20120156881A1 METHOD FOR DEFINING A SEPARATING STRUCTURE WITHIN A SEMICONDUCTOR DEVICE 有权
标题翻译：用于在半导体器件中定义分离结构的方法
公开(公告)号：US20120156881A1
公开(公告)日：2012-06-21
申请号：US12973295
申请日：2010-12-20
申请人： Henning Haffner
发明人： Henning Haffner
IPC分类号： G03F7/20 , H01L21/308
CPC分类号： H01L21/32139 , G03F7/0035 , H01L21/0337 , H01L21/28123 , H01L21/31144
摘要： A method includes depositing a material layer over a semiconductor substrate and using a first mask in a first exposure/patterning process to pattern the material layer thereby forming a plurality of first and second features. The first features include patterns for the semiconductor device and the second features include printing assist features. The method includes using a second mask in a second exposure/patterning process to effectively remove the second features from the material layer and to define at least one separating structure between two first features.
摘要翻译：一种方法包括在半导体衬底上沉积材料层并且在第一曝光/图案化工艺中使用第一掩模来对材料层进行图案化从而形成多个第一和第二特征。第一特征包括用于半导体器件的图案，第二特征包括印刷辅助特征。该方法包括在第二曝光/图案化工艺中使用第二掩模以有效地从材料层去除第二特征并且在两个第一特征之间限定至少一个分离结构。

40. 发明授权

US08099684B2 Methodology of placing printing assist feature for random mask layout 有权
标题翻译：放置随机蒙版布局的打印辅助功能的方法
公开(公告)号：US08099684B2
公开(公告)日：2012-01-17
申请号：US12350251
申请日：2009-01-08
申请人： Jason E Meiring , Henning Haffner
发明人： Jason E Meiring , Henning Haffner
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： Embodiments of the present invention provide a method of placing printing assist features in a mask layout. The method includes providing a design layout having one or more designed features; generating a set of parameters, the set of parameters being associated with one or more printing assist features (PrAFs); adding the one or more PrAFs of the set of parameters to the design layout to produce a modified design layout; performing simulation of the one or more PrAFs and the one or more designed features on the modified design layout; verifying whether the one or more PrAFs are removable based on results of the simulation; and creating a set of PrAF placement rules based on the set of parameters, if the one or more PrAFs are verified as removable. The set of PrAF placement rules may be used in creating a final set of PrAF features to be used for creating the mask layout.
摘要翻译：本发明的实施例提供了一种将打印辅助特征放置在掩模布局中的方法。该方法包括提供具有一个或多个设计特征的设计布局; 产生一组参数，该组参数与一个或多个打印辅助特征（PrAF）相关联; 将该组参数中的一个或多个PrAF添加到设计布局以产生修改的设计布局; 在修改的设计布局上执行一个或多个PrAF的模拟和一个或多个设计的特征; 基于模拟结果验证一个或多个PrAF是否可移除; 以及如果一个或多个PrAF被验证为可移除的，则基于该参数集创建一组PrAF放置规则。 PrAF放置规则的集合可以用于创建用于创建掩模布局的最后一组PrAF特征。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式