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1. 发明授权

US06353248B1 Optimized decoupling capacitor using lithographic dummy filler 有权
标题翻译：使用光刻虚拟填料的优化去耦电容器
公开(公告)号：US06353248B1
公开(公告)日：2002-03-05
申请号：US09562220
申请日：2000-04-28
申请人： Armin M Reith , Louis Hsu , Henning Haffner , Gunther Lehmann
发明人： Armin M Reith , Louis Hsu , Henning Haffner , Gunther Lehmann
IPC分类号： H01L2976
CPC分类号： H01L28/40 , H01L27/10861 , H01L27/10894 , H01L27/10897
摘要： A method to optimize the size and filling of decoupling capacitors for very large scale integrated circuits (VLSI) using existing lithographic fillers. The method combines the automatic or manual generation of lithographic fill patterns with the forming of the capacitors. According to the method, when the chip layout is about to be finished, all remaining empty space on the chip gets identified by a layout tool. Then, the closest power-supply nets get extracted. All power supplies and their combinations are sorted in a connection table which determines the appropriate types of capacitances once the power-supply nets closest to the empty spaces extracted from the layout. The empty spaces are then assigned appropriate decoupling capacitances. Decoupling capacitors generated by the method are suitable for VLSI power supplies for noise reduction.
摘要翻译：使用现有的平版印刷填料，优化大型集成电路（VLSI）的去耦电容的尺寸和填充的方法。该方法将自动或手动生成光刻填充图案与电容器的形成相结合。根据该方法，当芯片布局即将完成时，芯片上的所有剩余空间都由布局工具识别。然后，最近的电源网络被提取。所有电源及其组合在连接表中排序，一旦电源网最接近从布局提取的空白空间中，则确定适当类型的电容。然后空的空间被分配适当的去耦电容。通过该方法产生的去耦电容适用于降低噪声的VLSI电源。

2. 发明授权

US06232154B1 Optimized decoupling capacitor using lithographic dummy filler 有权
标题翻译：使用光刻虚拟填料的优化去耦电容器
公开(公告)号：US06232154B1
公开(公告)日：2001-05-15
申请号：US09442890
申请日：1999-11-18
申请人： Armin M. Reith , Louis Hsu , Henning Haffner , Gunther Lehmann
发明人： Armin M. Reith , Louis Hsu , Henning Haffner , Gunther Lehmann
IPC分类号： H01L2182
CPC分类号： H01L28/40 , H01L27/10861 , H01L27/10894 , H01L27/10897
摘要： A method to optimize the size and filling of decoupling capacitors for very large scale integrated circuits (VLSI) using existing lithographic fillers. The method combines the automatic or manual generation of lithographic fill patterns with the forming of the capacitors. According to the method, when the chip layout is about to be finished, all remaining empty space on the chip gets identified by a layout tool. Then, the closest power-supply nets get extracted. All power supplies and their combinations are sorted in a connection table which determines the appropriate types of capacitances once the power-supply nets closest to the empty spaces extracted from the layout. The empty spaces are then assigned appropriate decoupling capacitances. Decoupling capacitors generated by the method are suitable for VLSI power supplies for noise reduction.
摘要翻译：使用现有的平版印刷填料，优化大型集成电路（VLSI）的去耦电容的尺寸和填充的方法。该方法将自动或手动生成光刻填充图案与电容器的形成相结合。根据该方法，当芯片布局即将完成时，芯片上剩余的空余空间由布局工具识别。然后，最近的电源网络被提取。所有电源及其组合在连接表中排序，一旦电源网最接近从布局提取的空白空间中，则确定适当类型的电容。然后空的空间被分配适当的去耦电容。通过该方法产生的去耦电容适用于降低噪声的VLSI电源。

3. 发明授权

US06601205B1 Method to descramble the data mapping in memory circuits 有权
标题翻译：在存储器电路中解扰数据映射的方法
公开(公告)号：US06601205B1
公开(公告)日：2003-07-29
申请号：US09675953
申请日：2000-09-29
申请人： Gunther Lehmann , Gerd Frankowsky , Louis Hsu , Armin Reith
发明人： Gunther Lehmann , Gerd Frankowsky , Louis Hsu , Armin Reith
IPC分类号： G01R3128
CPC分类号： G01R31/318378 , G01R31/3183 , G01R31/31926 , G11C29/10 , G11C29/56
摘要： An automatic method for the generation of a logical hardware test pattern in memory circuits is based on a given physical pattern. The method includes backwards transformation from a given set of logical data patterns. Since the method is automatic, no knowledge of data scrambling inside the memory circuit is required.
摘要翻译：用于在存储器电路中产生逻辑硬件测试图案的自动方法基于给定的物理模式。该方法包括从给定的一组逻辑数据模式的向后变换。由于该方法是自动的，所以不需要存储电路内的数据加扰知识。

4. 发明申请

US20090111235A1 Semiconductor Integrated Circuit Devices Having High-Q Wafer Back-Side Capacitors 有权
标题翻译：具有高Q晶片背面电容器的半导体集成电路器件
公开(公告)号：US20090111235A1
公开(公告)日：2009-04-30
申请号：US12348707
申请日：2009-01-05
申请人： Lawrence Clevenger , Timothy Joseph Dalton , Louis Hsu , Carl Radens , Vidhya Ramachandran , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence Clevenger , Timothy Joseph Dalton , Louis Hsu , Carl Radens , Vidhya Ramachandran , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/02
CPC分类号： H01L21/84 , H01L21/76898 , H01L23/481 , H01L23/5223 , H01L27/1203 , H01L2924/0002 , Y10S438/957 , H01L2924/00
摘要： Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semiconductor device includes a semiconductor substrate having a front side, a back side, and a buried insulating layer interposed between the front and back sides of the substrate. An integrated circuit is formed on the front side of the semiconductor substrate, an integrated capacitor is formed on the back side of the semiconductor substrate, and an interconnection structure is formed through the buried insulating layer to connect the integrated capacitor to the integrated circuit.
摘要翻译：提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面的高Q片上电容器，并使用晶片间互连连接到芯片正面的集成电路。在一个方面，半导体器件包括一个半导体衬底，该半导体衬底具有介于衬底的正面和背面之间的正面，背面和掩埋绝缘层。在半导体基板的正面形成有集成电路，在半导体基板的背面形成有集成电容器，通过埋入绝缘层形成互连结构，将集成电容器与集成电路连接起来。

5. 发明申请

US20080023789A1 REPROGRAMMABLE ELECTRICAL FUSE 审中-公开
标题翻译：可折叠电气保险丝
公开(公告)号：US20080023789A1
公开(公告)日：2008-01-31
申请号：US11834841
申请日：2007-08-07
申请人： Louis Hsu , Conal Murray , Chaudrasekhar Narayan , Chih-Chao Yang
发明人： Louis Hsu , Conal Murray , Chaudrasekhar Narayan , Chih-Chao Yang
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , G11C16/02 , G11C17/16 , G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a reprogrammable electrically blowable fuse. The electrically blowable fuse is programmed using an electro-migration effect and is reprogrammed using a reverse electro-migration effect. The state (i.e., “opened” or “closed”) of the electrically blowable fuse is determined by a sensing system which compares a resistance of the electrically blowable fuse to a reference resistance.
摘要翻译：本发明提供一种可再编程的可电熔熔断器。电可熔熔丝使用电迁移效应进行编程，并使用反向电迁移效应重新编程。可电熔熔丝的状态（即“打开”或“关闭”）由将电可电熔丝的电阻与参考电阻进行比较的感测系统确定。

6. 发明申请

US20070235833A1 Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures 失效
标题翻译：具有自对准掺杂区域的半导体器件结构和用于形成这种半导体器件结构的方法
公开(公告)号：US20070235833A1
公开(公告)日：2007-10-11
申请号：US11393142
申请日：2006-03-30
申请人： Kangguo Cheng , Louis Hsu , Jack Mandelman
发明人： Kangguo Cheng , Louis Hsu , Jack Mandelman
IPC分类号： H01L29/00
CPC分类号： H01L27/10841 , H01L27/10864
摘要： Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures. The semiconductor structure comprises first and second doped regions of a first conductivity type defined in the semiconductor material of a substrate bordering a sidewall of a trench. An intervening region of the semiconductor material separates the first and second doped regions. A third doped region is defined in the semiconductor material bordering the sidewall of the trench and disposed between the first and second doped regions. The third doped region is doped to have a second conductivity type opposite to the first conductivity type. Methods for forming the doped regions involve depositing either a layer of a material doped with both dopants or different layers each doped with one of the dopants in the trench and, then, diffusing the dopants from the layer or layers into the semiconductor material bordering the trench sidewall.
摘要翻译：具有自对准掺杂区域的半导体器件结构和用于形成这种半导体器件结构的方法。半导体结构包括限定在与沟槽的侧壁相邻的衬底的半导体材料中的第一导电类型的第一和第二掺杂区域。半导体材料的中间区域分离第一和第二掺杂区域。第三掺杂区域限定在与沟槽的侧壁接壤并且设置在第一和第二掺杂区域之间的半导体材料中。第三掺杂区被掺杂以具有与第一导电类型相反的第二导电类型。用于形成掺杂区域的方法包括沉积掺杂有掺杂剂或不同层的材料的层，每个掺杂剂或不同的层在沟槽中掺杂有一种掺杂剂，然后将掺杂剂从层或层扩散到与沟槽接壤的半导体材料侧壁。

7. 发明申请

US20070224801A1 Dielectric interconnect structures and methods for forming the same 有权
标题翻译：介电互连结构及其形成方法
公开(公告)号：US20070224801A1
公开(公告)日：2007-09-27
申请号：US11390390
申请日：2006-03-27
申请人： Chih-Chao Yang , Louis Hsu , Rajiv Joshi
发明人： Chih-Chao Yang , Louis Hsu , Rajiv Joshi
IPC分类号： H01L21/4763
CPC分类号： H01L21/76834 , H01L21/76814 , H01L21/76826 , H01L21/76843 , H01L21/76844 , H01L21/76846
摘要： Dielectric interconnect structures and methods for forming the same are provided. Specifically, the present invention provides a dielectric interconnect structure having a noble metal layer (e.g., Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa) that is formed directly on a modified dielectric surface. In a typical embodiment, the modified dielectric surface is created by treating an exposed dielectric layer of the interconnect structure with a gaseous ion plasma (e.g., Ar, He, Ne, Xe, N2, H2, NH3, and N2H2). Under the present invention, the noble metal layer could be formed directly on an optional glue layer that is maintained only on vertical surfaces of any trench or via formed in the exposed dielectric layer. In addition, the noble metal layer may or may not be provided along an interface between the via and an internal metal layer.
摘要翻译：提供介电互连结构及其形成方法。具体地说，本发明提供一种具有贵金属层（例如，Ru，Ir，Rh，Pt，RuTa以及Ru，Ir，Rh，Pt和RuTa的合金）的电介质互连结构，其直接形成在改性电介质上表面。在典型的实施例中，通过用气体离子等离子体（例如，Ar，He，Ne，Xe，N 2，H 2，NH 3和N 2 H 2）。在本发明中，贵金属层可以直接形成在只保留在暴露的介电层中形成的任何沟槽或通孔的垂直表面上的任选的胶层上。此外，贵金属层可以沿着通孔和内部金属层之间的界面设置也可以不设置。

8. 发明申请

US20070210890A1 Electronic fuse with conformal fuse element formed over a freestanding dielectric spacer 失效
标题翻译：具有保形熔丝元件的电子保险丝，形成在独立电介质垫片上
公开(公告)号：US20070210890A1
公开(公告)日：2007-09-13
申请号：US11372387
申请日：2006-03-09
申请人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
发明人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
IPC分类号： H01H85/04
CPC分类号： H01L23/5256 , H01L2924/0002 , Y10T29/49107 , H01L2924/00
摘要： An electronic fuse for an integrated circuit and a method of fabrication thereof are presented. The electronic fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The fuse element has a convex upper surface and a lower surface with a radius of curvature at a smallest surface area of curvature less than or equal to 100 nanometers. Fabricating the electronic fuse includes forming an at least partially freestanding dielectric spacer above a supporting structure, and then conformably forming the fuse element of the fuse over at least a portion of the freestanding dielectric spacer, with the fuse element characterized as noted above. The dielectric spacer may remain in place as a thermally insulating layer underneath the fuse element, or may be removed to form a void underneath the fuse element.
摘要翻译：本发明提供一种用于集成电路的电子熔断器及其制造方法。电子熔断器具有由熔丝元件互连的第一端子部分和第二端子部分。保险丝元件具有凸起的上表面和具有小于或等于100纳米的曲率的最小表面积的曲率半径的下表面。制造电子熔断器包括在支撑结构之上形成至少部分独立的介电隔离物，然后在独立电介质隔离物的至少一部分上顺应地形成熔丝的熔丝元件，其中熔丝元件的特征如上所述。电介质间隔物可以保留在熔丝元件下面的绝热层的适当位置，或者可以被去除以在熔丝元件下面形成空隙。

9. 发明申请

US20070035342A1 Differential amplifier offset voltage minimization independently from common mode voltage adjustment 失效
公开(公告)号：US20070035342A1
公开(公告)日：2007-02-15
申请号：US11203860
申请日：2005-08-15
申请人： Minhan Chen , Westerfield Ficken , Louis Hsu , Steven Zier
发明人： Minhan Chen , Westerfield Ficken , Louis Hsu , Steven Zier
IPC分类号： H03F3/45
CPC分类号： H03F3/45197 , H03F2203/45424 , H03F2203/45431 , H03F2203/45488 , H03F2203/45646
摘要： Offset voltages in differential amplifiers are minimized by controlling compensation currents through the load impedances of the amplifiers. The currents are varied while sensing the polarity of the offset voltage. When the polarity changes, the current values are latched to keep the offset voltage at a minimum.

10. 发明申请

US20060284251A1 Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same 有权
公开(公告)号：US20060284251A1
公开(公告)日：2006-12-21
申请号：US11155030
申请日：2005-06-16
申请人： Louis Hsu , Jack Mandelman
发明人： Louis Hsu , Jack Mandelman
IPC分类号： H01L27/12
CPC分类号： H01L29/045 , H01L21/76283 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , H01L27/1207
摘要： In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) providing a substrate; and (2) forming a first silicon-on-insulator (SOI) region having a first crystal orientation, a second SOI region having a second crystal orientation and a third SOI region having a third crystal orientation on the substrate. The first, second and third SOI regions are coplanar. Numerous other aspects are provided.

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