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31. 发明申请

US20090008758A1 USE OF DISCRETE CONDUCTIVE LAYER IN SEMICONDUCTOR DEVICE TO RE-ROUTE BONDING WIRES FOR SEMICONDUCTOR DEVICE PACKAGE 有权
标题翻译：在半导体器件中使用分离导电层以重新布线用于半导体器件封装
公开(公告)号：US20090008758A1
公开(公告)日：2009-01-08
申请号：US12209106
申请日：2008-09-11
申请人： Jun Lu , Anup Bhalla , Xiaobin Wang , Allen Chang , Man Sheng Hu , Xiaotian Zhang
发明人： Jun Lu , Anup Bhalla , Xiaobin Wang , Allen Chang , Man Sheng Hu , Xiaotian Zhang
IPC分类号： H01L23/495 , H01L21/58 , H01L23/488
CPC分类号： H01L21/823487 , H01L23/4952 , H01L23/49524 , H01L23/49531 , H01L23/49562 , H01L23/49575 , H01L23/58 , H01L24/37 , H01L24/39 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/85 , H01L24/91 , H01L25/071 , H01L25/074 , H01L25/18 , H01L27/088 , H01L2224/05552 , H01L2224/0603 , H01L2224/32145 , H01L2224/32245 , H01L2224/37124 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48247 , H01L2224/48465 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49112 , H01L2224/4917 , H01L2224/49171 , H01L2224/49431 , H01L2224/73265 , H01L2224/83801 , H01L2224/8385 , H01L2224/85 , H01L2225/06562 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H02J7/0031 , H01L2224/78 , H01L2924/00 , H01L2924/00012 , H01L2224/45099
摘要： A semiconductor package assembly may include a lead frame having a die bonding pad and plurality of leads coupled to the first die bonding pad. A vertical semiconductor device may be bonded to the die bonding pad. The device may have a conductive pad electrically connected to one lead through a first bond wire. An electrically isolated conductive trace may be formed from a layer of conductive material of the first semiconductor device. The conductive trace provides an electrically conductive path between the first bond wire and a second bond wire. The conductive path may either pass underneath a third bond wire thereby avoiding the third bond wire crossing another bond wire, or the conductive path may result in a reduced length for the first and second bond wires that is less than a predetermined maximum length.
摘要翻译：半导体封装组件可以包括引线框架，其具有管芯接合焊盘和耦合到第一管芯接合焊盘的多个引线。垂直半导体器件可以结合到芯片焊盘。该器件可以具有通过第一接合线电连接到一个引线的导电焊盘。电绝缘的导电迹线可以由第一半导体器件的导电材料层形成。导电迹线在第一接合线和第二接合线之间提供导电路径。导电路径可以通过第三接合线下方，从而避免第三接合线穿过另一接合线，或者导电路径可导致第一和第二接合线的长度小于预定最大长度。

32. 发明申请

US20130009242A1 MOS DEVICE WITH LOW INJECTION DIODE 审中-公开
标题翻译：具有低注射二极管的MOS器件
公开(公告)号：US20130009242A1
公开(公告)日：2013-01-10
申请号：US13610758
申请日：2012-09-11
申请人： Anup Bhalla , Xiaobin Wang , Ji Pan , Sung-Po Wei
发明人： Anup Bhalla , Xiaobin Wang , Ji Pan , Sung-Po Wei
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/1095 , H01L21/26586 , H01L29/0623 , H01L29/165 , H01L29/41766 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813
摘要： A semiconductor device is formed on a semiconductor substrate. The device includes: a drain; an epitaxial layer overlaying the drain, wherein a drain region extends into the epitaxial layer; and an active region. The active region includes: a body disposed in the epitaxial layer, having a body top surface; a source embedded in the body, extending from the body top surface into the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; an active region contact trench extending through the source and into the body; and an active region contact electrode disposed within the active region contact trench. A layer of body region separates the active region contact electrode from the epitaxial layer, and a low injection diode is formed below a body/drain junction.
摘要翻译：半导体器件形成在半导体衬底上。该装置包括：排水管; 覆盖所述漏极的外延层，其中漏区延伸到所述外延层中; 和活跃区域。有源区包括：设置在外延层中的具有主体顶表面的主体; 嵌入在体内的源体，从身体顶面延伸到体内; 延伸到外延层中的栅极沟槽; 设置在栅极沟槽中的栅极; 有源区接触沟槽延伸穿过该源并进入体内; 以及设置在有源区接触沟槽内的有源区接触电极。主体区域将有源区接触电极与外延层分开，并且在主体/漏极结下方形成低注入二极管。

33. 发明申请

US20120302021A1 FABRICATION OF MOS DEVICE WITH VARYING TRENCH DEPTH 有权
标题翻译：具有不断变化的深度深度的MOS器件的制造
公开(公告)号：US20120302021A1
公开(公告)日：2012-11-29
申请号：US13559975
申请日：2012-07-27
申请人： Anup Bhalla , Xiaobin Wang
发明人： Anup Bhalla , Xiaobin Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0623 , H01L29/1095 , H01L29/165 , H01L29/41766 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; disposing gate material in the gate trench; forming a body in the epitaxial layer; forming a source in the body; forming an active region contact trench that has a varying trench depth; and disposing a contact electrode within the active region contact trench. Forming the active region contact trench includes performing a first etch to form a first contact trench depth associated with a first region, and performing a second etch to form a second contact trench depth associated with a second region. The first contact trench depth is substantially different from the second contact trench depth.
摘要翻译：制造半导体器件包括：在覆盖半导体衬底的外延层中形成栅极沟槽; 在门沟中设置栅极材料; 在外延层中形成主体; 在身体中形成一个来源; 形成具有变化的沟槽深度的有源区接触沟槽; 以及将接触电极设置在有源区接触沟槽内。形成有源区接触沟槽包括执行第一蚀刻以形成与第一区域相关联的第一接触沟槽深度，以及执行第二蚀刻以形成与第二区域相关联的第二接触沟槽深度。第一接触沟槽深度与第二接触沟槽深度基本不同。

34. 发明授权

US08299494B2 Nanotube semiconductor devices 有权
标题翻译：纳米管半导体器件
公开(公告)号：US08299494B2
公开(公告)日：2012-10-30
申请号：US12484170
申请日：2009-06-12
申请人： Hamza Yilmaz , Xiaobin Wang , Anup Bhalla , John Chen , Hong Chang
发明人： Hamza Yilmaz , Xiaobin Wang , Anup Bhalla , John Chen , Hong Chang
IPC分类号： H01L29/74 , H01L31/111 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/0886 , H01L21/26586 , H01L27/0623 , H01L27/0629 , H01L27/0664 , H01L29/0615 , H01L29/0619 , H01L29/063 , H01L29/0634 , H01L29/0638 , H01L29/0649 , H01L29/0653 , H01L29/0676 , H01L29/0688 , H01L29/0692 , H01L29/0696 , H01L29/0865 , H01L29/0878 , H01L29/0882 , H01L29/1095 , H01L29/36 , H01L29/365 , H01L29/402 , H01L29/404 , H01L29/41741 , H01L29/41775 , H01L29/4236 , H01L29/42368 , H01L29/66136 , H01L29/66143 , H01L29/66348 , H01L29/66734 , H01L29/7395 , H01L29/7397 , H01L29/7803 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/7827 , H01L29/861 , H01L29/8613 , H01L29/872 , H01L29/8725
摘要： A semiconductor device includes a first semiconductor layer and a second semiconductor layer of opposite conductivity type, a first epitaxial layer of the first conductivity type formed on sidewalls of the trenches, and a second epitaxial layer of the second conductivity type formed on the first epitaxial layer where the second epitaxial layer is electrically connected to the second semiconductor layer. The first epitaxial layer and the second epitaxial layer form parallel doped regions along the sidewalls of the trenches, each having uniform doping concentration. The second epitaxial layer has a first thickness and a first doping concentration and the first epitaxial layer and a mesa of the first semiconductor layer together having a second thickness and a second average doping concentration where the first and second thicknesses and the first doping concentration and second average doping concentrations are selected to achieve charge balance in operation.
摘要翻译：半导体器件包括第一半导体层和相反导电类型的第二半导体层，形成在沟槽的侧壁上的第一导电类型的第一外延层和形成在第一外延层上的第二导电类型的第二外延层其中第二外延层电连接到第二半导体层。第一外延层和第二外延层沿着沟槽的侧壁形成平行的掺杂区域，每个具有均匀的掺杂浓度。第二外延层具有第一厚度和第一掺杂浓度，第一外延层和第一半导体层的台面一起具有第二厚度和第二平均掺杂浓度，其中第一和第二厚度和第一掺杂浓度和第二掺杂浓度选择平均掺杂浓度以在操作中实现电荷平衡。

35. 发明授权

US08049315B2 Use of discrete conductive layer in semiconductor device to re-route bonding wires for semiconductor device package 有权
标题翻译：在半导体器件中使用离散导电层来重新布线用于半导体器件封装的接合线
公开(公告)号：US08049315B2
公开(公告)日：2011-11-01
申请号：US13007279
申请日：2011-01-14
申请人： Jun Lu , Anup Bhalla , Xiaobin Wang , Allen Chang , Kenny Man Sheng Hu , Xiaotian Zhang
发明人： Jun Lu , Anup Bhalla , Xiaobin Wang , Allen Chang , Kenny Man Sheng Hu , Xiaotian Zhang
IPC分类号： H01L23/495
CPC分类号： H01L21/823487 , H01L23/4952 , H01L23/49524 , H01L23/49531 , H01L23/49562 , H01L23/49575 , H01L23/58 , H01L24/37 , H01L24/39 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/85 , H01L24/91 , H01L25/071 , H01L25/074 , H01L25/18 , H01L27/088 , H01L2224/05552 , H01L2224/0603 , H01L2224/32145 , H01L2224/32245 , H01L2224/37124 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48247 , H01L2224/48465 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49112 , H01L2224/4917 , H01L2224/49171 , H01L2224/49431 , H01L2224/73265 , H01L2224/83801 , H01L2224/8385 , H01L2224/85 , H01L2225/06562 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H02J7/0031 , H01L2224/78 , H01L2924/00 , H01L2924/00012 , H01L2224/45099
摘要： A semiconductor package assembly may include a lead frame having a die bonding pad and plurality of leads coupled to the first die bonding pad. A vertical semiconductor device may be bonded to the die bonding pad. The device may have a conductive pad electrically connected to one lead through a first bond wire. An electrically isolated conductive trace may be formed from a layer of conductive material of the first semiconductor device. The conductive trace provides an electrically conductive path between the first bond wire and a second bond wire. The conductive path may either pass underneath a third bond wire thereby avoiding the third bond wire crossing another bond wire, or the conductive path may result in a reduced length for the first and second bond wires that is less than a predetermined maximum length.
摘要翻译：半导体封装组件可以包括引线框架，其具有管芯接合焊盘和耦合到第一管芯接合焊盘的多个引线。垂直半导体器件可以结合到芯片焊盘。该器件可以具有通过第一接合线电连接到一个引线的导电焊盘。电绝缘的导电迹线可以由第一半导体器件的导电材料层形成。导电迹线在第一接合线和第二接合线之间提供导电路径。导电路径可以通过第三接合线下方，从而避免第三接合线穿过另一接合线，或者导电路径可导致第一和第二接合线的长度小于预定最大长度。

36. 发明申请

US20110140228A1 Method of Filling Large Deep Trench with High Quality Oxide for Semiconductor Devices 有权
标题翻译：用于半导体器件的高质量氧化物填充大深沟槽的方法
公开(公告)号：US20110140228A1
公开(公告)日：2011-06-16
申请号：US12637988
申请日：2009-12-15
申请人： Xiaobin Wang , Anup Bhalla , Yeeheng Lee
发明人： Xiaobin Wang , Anup Bhalla , Yeeheng Lee
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L29/0657 , H01L21/76202 , H01L21/76224 , H01L21/76227 , H01L29/407 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： A method is disclosed for creating a semiconductor device structure with an oxide-filled large deep trench (OFLDT) portion having trench size TCS and trench depth TCD. A bulk semiconductor layer (BSL) is provided with a thickness BSLT>TCD. A large trench top area (LTTA) is mapped out atop BSL with its geometry equal to OFLDT. The LTTA is partitioned into interspersed, complementary interim areas ITA-A and ITA-B. Numerous interim vertical trenches of depth TCD are created into the top BSL surface by removing bulk semiconductor materials corresponding to ITA-B. The remaining bulk semiconductor materials corresponding to ITA-A are converted into oxide. If any residual space is still left between the so-converted ITA-A, the residual space is filled up with oxide deposition. Importantly, the geometry of all ITA-A and ITA-B should be configured simple and small enough to facilitate fast and efficient processes of oxide conversion and oxide filling.
摘要翻译：公开了一种用于产生具有沟槽尺寸TCS和沟槽深度TCD的具有氧化物填充的大深沟槽（OFLDT）部分的半导体器件结构的方法。体积半导体层（BSL）设置有厚度BSLT> TCD。一个大的沟槽顶部区域（LTTA）映射到BSL顶部，其几何形状等于OFLDT。 LTTA被划分为散置的，互补的临时区域ITA-A和ITA-B。通过去除对应于ITA-B的散装半导体材料，在顶部BSL表面上形成了许多深度TCD的临时垂直沟槽。对应于ITA-A的剩余体积半导体材料被转化为氧化物。如果在经过转换的ITA-A之间仍然留有剩余空间，则剩余空间被氧化物沉积填满。重要的是，所有ITA-A和ITA-B的几何形状都应该被简单而小型化，以便于快速有效地进行氧化物转换和氧化物填充。

37. 发明申请

US20110140194A1 Enhancing Schottky breakdown voltage (BV) without affecting an integrated Mosfet-Schottky device layout 有权
标题翻译：增强肖特基击穿电压（BV），而不影响集成的Mosfet-Schottky器件布局
公开(公告)号：US20110140194A1
公开(公告)日：2011-06-16
申请号：US12932163
申请日：2011-02-17
申请人： Anup Bhalla , Xiaobin Wang , Moses Ho
发明人： Anup Bhalla , Xiaobin Wang , Moses Ho
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/1095 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/872
摘要： This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.
摘要翻译：本发明公开了一种包括具有多个功率晶体管单元的有源单元区域的半导体功率器件。每个所述功率晶体管单元具有平面肖特基二极管，其包括覆盖两个相邻功率晶体管单元之间的分离体区域之间的间隙上方的区域的肖特基结阻挡金属。分离体区域还提供调节每个所述功率晶体管单元中的所述肖特基二极管的漏电流的功能。每个平面肖特基二极管还包括设置在两个相邻功率晶体管单元的分离的体区之间的间隙中的香农注入区，用于进一步调整所述肖特基二极管的漏电流。每个功率晶体管单元进一步包括分离体区域中的重体掺杂区域，其邻近形成结屏障肖特基（JBS）口袋区域的围绕所述肖特基二极管的源极区域。

38. 发明授权

US07952139B2 Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout 有权
标题翻译：增强肖特基击穿电压（BV），而不影响集成MOSFET肖特基器件布局
公开(公告)号：US07952139B2
公开(公告)日：2011-05-31
申请号：US12217092
申请日：2008-06-30
申请人： Anup Bhalla , Xiaobin Wang , Moses Ho
发明人： Anup Bhalla , Xiaobin Wang , Moses Ho
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/1095 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/872
摘要： This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.
摘要翻译：本发明公开了一种包括具有多个功率晶体管单元的有源单元区域的半导体功率器件。每个所述功率晶体管单元具有平面肖特基二极管，其包括覆盖两个相邻功率晶体管单元之间的分离体区域之间的间隙上方的区域的肖特基结阻挡金属。分离体区域还提供调节每个所述功率晶体管单元中的所述肖特基二极管的漏电流的功能。每个平面肖特基二极管还包括设置在两个相邻功率晶体管单元的分离的体区之间的间隙中的香农注入区，用于进一步调整所述肖特基二极管的漏电流。每个功率晶体管单元进一步包括分离体区域中的重体掺杂区域，其邻近形成结屏障肖特基（JBS）口袋区域的围绕所述肖特基二极管的源极区域。

39. 发明授权

US07948029B2 MOS device with varying trench depth 有权
标题翻译：具有不同沟槽深度的MOS器件
公开(公告)号：US07948029B2
公开(公告)日：2011-05-24
申请号：US12228142
申请日：2008-08-07
申请人： Anup Bhalla , Xiaobin Wang
发明人： Anup Bhalla , Xiaobin Wang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0623 , H01L29/1095 , H01L29/165 , H01L29/41766 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： A semiconductor device includes a drain, an epitaxial layer overlaying the drain, a body disposed in the epitaxial layer, a source embedded in the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, an active region contact trench extending through the source, the active region contact trench having a varying contact trench depth, and an active region contact electrode disposed within the active region contact trench.
摘要翻译：半导体器件包括漏极，覆盖漏极的外延层，设置在外延层中的主体，嵌入在主体中的源极，延伸到外延层中的栅极沟槽，设置在栅极沟槽中的栅极，有源区域触点延伸穿过源极的沟槽，具有变化的接触沟槽深度的有源区接触沟槽和设置在有源区接触沟槽内的有源区接触电极。

40. 发明申请

US20110108998A1 USE OF DISCRETE CONDUCTIVE LAYER IN SEMICONDUCTOR DEVICE TO RE-ROUTE BONDING WIRES FOR SEMICONDUCTOR DEVICE PACKAGE 有权
标题翻译：在半导体器件中使用分离导电层以重新布线用于半导体器件封装
公开(公告)号：US20110108998A1
公开(公告)日：2011-05-12
申请号：US13007279
申请日：2011-01-14
申请人： Jun Lu , Anup Bhalla , Xiaobin Wang , Allen Chang , Man Sheng Hu , Xiaotian Zhang
发明人： Jun Lu , Anup Bhalla , Xiaobin Wang , Allen Chang , Man Sheng Hu , Xiaotian Zhang
IPC分类号： H01L23/52
CPC分类号： H01L21/823487 , H01L23/4952 , H01L23/49524 , H01L23/49531 , H01L23/49562 , H01L23/49575 , H01L23/58 , H01L24/37 , H01L24/39 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/85 , H01L24/91 , H01L25/071 , H01L25/074 , H01L25/18 , H01L27/088 , H01L2224/05552 , H01L2224/0603 , H01L2224/32145 , H01L2224/32245 , H01L2224/37124 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48247 , H01L2224/48465 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49112 , H01L2224/4917 , H01L2224/49171 , H01L2224/49431 , H01L2224/73265 , H01L2224/83801 , H01L2224/8385 , H01L2224/85 , H01L2225/06562 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H02J7/0031 , H01L2224/78 , H01L2924/00 , H01L2924/00012 , H01L2224/45099
摘要： A semiconductor package assembly may include a lead frame having a die bonding pad and plurality of leads coupled to the first die bonding pad. A vertical semiconductor device may be bonded to the die bonding pad. The device may have a conductive pad electrically connected to one lead through a first bond wire. An electrically isolated conductive trace may be formed from a layer of conductive material of the first semiconductor device. The conductive trace provides an electrically conductive path between the first bond wire and a second bond wire. The conductive path may either pass underneath a third bond wire thereby avoiding the third bond wire crossing another bond wire, or the conductive path may result in a reduced length for the first and second bond wires that is less than a predetermined maximum length.
摘要翻译：半导体封装组件可以包括引线框架，其具有管芯接合焊盘和耦合到第一管芯接合焊盘的多个引线。垂直半导体器件可以结合到芯片焊盘。该器件可以具有通过第一接合线电连接到一个引线的导电焊盘。电绝缘的导电迹线可以由第一半导体器件的导电材料层形成。导电迹线在第一接合线和第二接合线之间提供导电路径。导电路径可以通过第三接合线下方，从而避免第三接合线穿过另一接合线，或者导电路径可导致第一和第二接合线的长度小于预定最大长度。

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