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31. 发明授权

US5243317A Magneto-resistor digitizer 失效
标题翻译：磁电阻数字转换器
公开(公告)号：US5243317A
公开(公告)日：1993-09-07
申请号：US804738
申请日：1991-12-11
申请人： Hsing Chen , Pie-Yu Jeang , Spring Yeh , Ting Chou , Ping-Wei Wang
发明人： Hsing Chen , Pie-Yu Jeang , Spring Yeh , Ting Chou , Ping-Wei Wang
IPC分类号： G06F3/033 , G06F3/046 , H01C10/00
CPC分类号： G06F3/046 , H01C10/00
摘要： A digitizer whose sensing elements are made of magnetoresistive materials is designed for use with a computer system. The digitizer board includes a substrate made of dielectric material; a first array of strip-shaped magneto-resistors arranged on the front surface of the substrate; a second array of strip-shaped magneto-resistors arranged on the reverse surface of the substrate; a plurality of analog comparators coupled to the magneto-resistors; and a pen with a magnetic pinpoint used for pointing to a particular location on the front side of the digitizer board. The resistance of the magneto-resistors will vary due to a magnetic field emerging from the nearby pinpoint, and the magnetic-resistors will be effected, and subsequently the comparators connected to the magneto-resistors will send digital signals to the computer system.
摘要翻译：感测元件由磁阻材料制成的数字化仪被设计用于计算机系统。数字转换器板包括由介电材料制成的基板; 布置在所述基板的前表面上的第一阵列的带状磁阻电阻器; 布置在所述基板的相反表面上的第二阵列的带状磁电阻器; 耦合到所述磁电阻器的多个模拟比较器; 以及具有用于指向数字转换器板的前侧上的特定位置的磁性精确点的笔。磁阻电阻的电阻将由于从附近的尖端产生的磁场而变化，并且磁阻将被实现，随后连接到磁阻的比较器将向计算机系统发送数字信号。

32. 发明授权

US08406028B1 Word line layout for semiconductor memory 有权
标题翻译：半导体存储器的字线布局
公开(公告)号：US08406028B1
公开(公告)日：2013-03-26
申请号：US13285212
申请日：2011-10-31
申请人： Tzu-Kuei Lin , Hung-Jen Liao , Yen-Huei Chen , Ping-Wei Wang , Huai-Ying Huang
发明人： Tzu-Kuei Lin , Hung-Jen Liao , Yen-Huei Chen , Ping-Wei Wang , Huai-Ying Huang
IPC分类号： G11C5/06 , H01L21/66
CPC分类号： H01L27/1104 , G11C8/16 , G11C11/412 , H01L27/0207
摘要： A semiconductor memory includes first and second word lines. A first bit cell of a first type is coupled to a first one of a plurality of bit lines and has a first layout in which the first bit cell of the first type is coupled to the first word line with a first number of vias and to the second word line with a second number of vias. A first bit cell of a second type is coupled to a second one of the plurality of bit lines and has a second layout in which the first bit cell of the second type is coupled to the first word line with a third number of vias and to the second word line with a fourth number of vias. A load on the first word line is approximately equal to a load on the second word line.
摘要翻译：半导体存储器包括第一和第二字线。第一类型的第一位单元耦合到多个位线中的第一位，并且具有第一布局，其中第一类型的第一位单元与第一数量的通孔耦合到第一字线，并且第二个字线与第二个通孔。第二类型的第一位单元耦合到多个位线中的第二位，并且具有第二布局，其中第二类型的第一位单元与第三数量的通孔耦合到第一字线，并且第二个字线，第四个通孔。第一个字线上的负载近似等于第二个字线上的负载。

33. 发明授权

US08315085B1 SRAM timing tracking circuit 有权
标题翻译： SRAM定时跟踪电路
公开(公告)号：US08315085B1
公开(公告)日：2012-11-20
申请号：US13289030
申请日：2011-11-04
申请人： Feng-Ming Chang , Chang-Ta Yang , Huai-Ying Huang , Ping-Wei Wang
发明人： Feng-Ming Chang , Chang-Ta Yang , Huai-Ying Huang , Ping-Wei Wang
IPC分类号： G11C11/00
CPC分类号： G11C29/24 , G11C11/41 , G11C29/50012
摘要： A timing tracking circuit is configured within a functional memory array, obviating the need for a separate, standalone timing tracking circuit. A generated pulse is routed circuitously through conductors enlisted for timing purposes, to trigger switching of a test cell in the array, which discharges an associated bit line from a pre-charged high value. The pulled down signal resulting from the discharge is detected at a measurement unit to infer timing characteristics of the memory array. The timing tracking circuitry is implemented by re-purposing certain conductors, test cells and dummy cells inserting certain conductive or nonconductive regions at one or more layers or at vias between layers to alter operation of the respective conductors and cells. Cells and conductors not enlisted for timing remain available for efficient, reliable memory access performance.
摘要翻译：定时跟踪电路配置在功能存储器阵列内，消除了对单独的独立定时跟踪电路的需要。所产生的脉冲通过定时目的的导体被路由布线，以触发阵列中的测试单元的切换，该预定电荷从预充电的高值放电相关联的位线。在测量单元处检测由放电产生的下拉信号以推断存储器阵列的定时特性。定时跟踪电路通过重新使用某些导体，测试单元和虚设单元来实现，所述导体，测试单元和虚设单元在层之间或层之间的通孔处插入某些导电或非导电区域，以改变相应导体和单元的操作。不用于定时的单元和导体仍然可用于高效，可靠的存储器访问性能。

34. 发明申请

US20120108036A1 Active Region Patterning in Double Patterning Processes 有权
标题翻译：双重图案化过程中的活动区域图案化
公开(公告)号：US20120108036A1
公开(公告)日：2012-05-03
申请号：US12917205
申请日：2010-11-01
申请人： Feng-Ming Chang , Chang-Ta Yang , Huai-Ying Huang , Ping-Wei Wang , Hsiang-Lin Chen
发明人： Feng-Ming Chang , Chang-Ta Yang , Huai-Ying Huang , Ping-Wei Wang , Hsiang-Lin Chen
IPC分类号： H01L21/20
CPC分类号： H01L27/1104 , H01L27/0207
摘要： A method includes forming an SRAM cell including a first and a second pull-up transistor and a first and a second pull-down transistor. The step of forming the SRAM cell includes forming a first and a second active region of the first and the second pull-up transistors using a first lithography mask, and forming a third and a fourth active region of the first and the second pull-down transistors using a second lithography mask.
摘要翻译：一种方法包括形成包括第一和第二上拉晶体管以及第一和第二下拉晶体管的SRAM单元。形成SRAM单元的步骤包括使用第一光刻掩模形成第一和第二上拉晶体管的第一和第二有源区，并且形成第一和第二下拉的第三和第四有源区使用第二光刻掩模的晶体管。

35. 发明申请

US20100237419A1 Static Random Access Memory (SRAM) Cell and Method for Forming Same 有权
标题翻译：静态随机存取存储器（SRAM）单元及其形成方法
公开(公告)号：US20100237419A1
公开(公告)日：2010-09-23
申请号：US12408193
申请日：2009-03-20
申请人： Lie-Yong Yang , Feng-Ming Chang , Chang-Ta Yang , Ping-Wei Wang
发明人： Lie-Yong Yang , Feng-Ming Chang , Chang-Ta Yang , Ping-Wei Wang
IPC分类号： H01L27/11 , H01L21/768
CPC分类号： H01L27/088 , H01L27/0207 , H01L27/0886 , H01L27/11 , H01L27/1104
摘要： In accordance with an embodiment of the present invention, a static random access memory (SRAM) cell comprises a first pull-down transistor, a first pull-up transistor, a first pass-gate transistor, a second pull-down transistor, a second pull-up transistor, a second pass-gate transistor, a first linear intra-cell connection, and a second linear intra-cell connection. Active areas of the transistors are disposed in a substrate, and longitudinal axes of the active areas of the transistors are all parallel. The first linear intra-cell connection electrically couples the active area of the first pull-down transistor, the active area of the first pull-up transistor, and the active area of the first pass-gate transistor to a gate electrode of the second pull-down transistor and a gate electrode of the second pull-up transistor. The second linear intra-cell connection electrically couples the active area of the second pull-down transistor, the active area of the second pull-up transistor, and the active area of the second pass-gate transistor to a gate electrode of the first pull-down transistor and a gate electrode of the first pull-up transistor.
摘要翻译：根据本发明的实施例，静态随机存取存储器（SRAM）单元包括第一下拉晶体管，第一上拉晶体管，第一通过栅极晶体管，第二下拉晶体管，第二上拉晶体管，第二通孔晶体管，第一线性单元内连接和第二线性单元内连接。晶体管的有源区域设置在衬底中，并且晶体管的有源区域的纵轴全部是平行的。第一线性单元间连接将第一下拉晶体管的有源区域，第一上拉晶体管的有效区域和第一通过栅极晶体管的有源区域电耦合到第二拉伸的栅电极下降晶体管和第二上拉晶体管的栅电极。第二线性单元间连接将第二下拉晶体管的有效区域，第二上拉晶体管的有效区域和第二通过栅极晶体管的有源区域电耦合到第一拉拔的栅电极下降晶体管和第一上拉晶体管的栅电极。

36. 发明申请

US20100176424A1 Doping of Semiconductor Fin Devices 有权
标题翻译：半导体鳍片器件的掺杂
公开(公告)号：US20100176424A1
公开(公告)日：2010-07-15
申请号：US12732011
申请日：2010-03-25
申请人： Yee-Chia Yeo , Ping-Wei Wang , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Ping-Wei Wang , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L29/786 , H01L29/04
CPC分类号： H01L29/785 , H01L21/26586 , H01L29/66803
摘要： A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.
摘要翻译：半导体结构包括覆盖绝缘体层的多个半导体鳍片，覆盖所述半导体鳍片的一部分的栅极电介质和覆盖栅极电介质的栅电极。每个半导体翅片具有顶表面，第一侧壁表面和第二侧壁表面。掺杂离子相对于半导体鳍片的顶表面的法线以第一角度（例如，大于约7°）注入，以掺杂第一侧壁表面和顶表面。相对于半导体鳍片的顶表面的法线注入另外的掺杂剂离子以掺杂第二侧壁表面和顶表面。

37. 发明授权

US07701008B2 Doping of semiconductor fin devices 有权
标题翻译：掺杂半导体鳍片器件
公开(公告)号：US07701008B2
公开(公告)日：2010-04-20
申请号：US11446890
申请日：2006-06-05
申请人： Yee-Chia Yeo , Ping-Wei Wang , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Ping-Wei Wang , Hao-Yu Chen , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L21/26586 , H01L29/66803
摘要： A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.
摘要翻译：半导体结构包括覆盖绝缘体层的多个半导体鳍片，覆盖所述半导体鳍片的一部分的栅极电介质和覆盖栅极电介质的栅电极。每个半导体翅片具有顶表面，第一侧壁表面和第二侧壁表面。掺杂离子相对于半导体鳍片的顶表面的法线以第一角度（例如，大于约7°）注入，以掺杂第一侧壁表面和顶表面。相对于半导体鳍片的顶表面的法线注入另外的掺杂剂离子以掺杂第二侧壁表面和顶表面。

38. 发明申请

US20080244483A1 INTEGRATED CIRCUIT DESIGN USAGE AND SANITY VERIFICATION 有权
标题翻译：集成电路设计使用和SANITY验证
公开(公告)号：US20080244483A1
公开(公告)日：2008-10-02
申请号：US11960900
申请日：2007-12-20
申请人： Gwan Sin Chang , Cheng Hung Yeh , Feng-Ming Chang , Ping-Wei Wang
发明人： Gwan Sin Chang , Cheng Hung Yeh , Feng-Ming Chang , Ping-Wei Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method and system for verifying an integrated circuit design are provided. The method includes identifying cell tags embedded in a proposed integrated circuit design file, comparing cells identified as having a tag embedded therein to a cell library containing verified cell data to determine differences between the identified tagged cells and corresponding verified cell data from the cell library, and revising the proposed integrated circuit design to correct differences between the proposed integrated circuit design file and the verified cell data.
摘要翻译：提供了一种验证集成电路设计的方法和系统。该方法包括识别嵌入在所提出的集成电路设计文件中的细胞标签，将标识为具有嵌入其中的标签的细胞与包含经验证的细胞数据的细胞库进行比较，以确定所识别的标记细胞与来自细胞库的相应的经检测细胞数据之间的差异，并修改所提出的集成电路设计，以纠正所提出的集成电路设计文件与经过验证的单元数据之间的差异。

39. 发明申请

US20080043561A1 CIRCUIT FOR AN SRAM WITH REDUCED POWER CONSUMPTION 有权
标题翻译：具有降低功耗的SRAM的电路
公开(公告)号：US20080043561A1
公开(公告)日：2008-02-21
申请号：US11506438
申请日：2006-08-18
申请人： Ping-Wei Wang , Yuh-Jier Mii
发明人： Ping-Wei Wang , Yuh-Jier Mii
IPC分类号： G11C5/14 , G11C11/00 , G11C8/00
CPC分类号： G11C11/413 , G11C8/08
摘要： A circuit and method for providing an SRAM memory with reduced power consumption, the SRAM memory particularly useful for embedding SRAM memory with other logic and memory functions in an integrated circuit. A lower supply voltage is provided to the peripheral circuitry for the SRAM memory. A level shifter circuit is provided coupled to the lower power supply and outputting a higher supply voltage. An array of SRAM memory cells that may comprise 4 T, 6 T or 8 T static RAM memory cells are coupled to the higher supply voltage during read and write operations. Operating the peripheral circuitry of the SRAM memory at the lower supply voltage achieves reduced power consumption for the SRAM memory and the integrated circuit.
摘要翻译：一种用于提供具有降低功耗的SRAM存储器的电路和方法，该SRAM存储器特别适用于将具有其他逻辑和存储器功能的SRAM存储器嵌入集成电路中。向SRAM存储器的外围电路提供较低的电源电压。提供电平移位器电路，耦合到下电源并输出较高的电源电压。可以包括4T，6T或8T静态RAM存储器单元的SRAM存储器单元的阵列在读取和写入操作期间耦合到更高的电源电压。在较低电源电压下操作SRAM存储器的外围电路实现了SRAM存储器和集成电路的功耗降低。

40. 发明申请

US20070257308A1 Modifying work function in PMOS devices by counter-doping 失效
标题翻译：通过反掺杂改进PMOS器件的功能
公开(公告)号：US20070257308A1
公开(公告)日：2007-11-08
申请号：US11416938
申请日：2006-05-03
申请人： Chun-Yi Lee , Harry Chuang , Ping-Wei Wang , Kong-Beng Thei
发明人： Chun-Yi Lee , Harry Chuang , Ping-Wei Wang , Kong-Beng Thei
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L27/0883 , G11C11/412 , H01L27/092 , H01L27/105 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/1083 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848 , Y10S438/919
摘要： A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.
摘要翻译：提供了包括SRAM /反相器单元的半导体结构及其形成方法，其中SRAM /反相器单元具有改善的写入裕度。 SRAM /反相器单元包括上拉PMOS器件，其包括半导体衬底上的栅极电介质，栅极电介质上的栅电极，其中栅电极包括p型杂质和n型杂质，以及形成在源极/漏极区域。上拉PMOS器件的器件驱动电流由于栅电极的反掺杂而降低。

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