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1. 发明授权

US08004042B2 Static random access memory (SRAM) cell and method for forming same 有权
标题翻译：静态随机存取存储器（SRAM）单元及其形成方法
公开(公告)号：US08004042B2
公开(公告)日：2011-08-23
申请号：US12408193
申请日：2009-03-20
申请人： Lie-Yong Yang , Feng-Ming Chang , Chang-Ta Yang , Ping-Wei Wang
发明人： Lie-Yong Yang , Feng-Ming Chang , Chang-Ta Yang , Ping-Wei Wang
IPC分类号： H01L27/11 , H01L21/768
CPC分类号： H01L27/088 , H01L27/0207 , H01L27/0886 , H01L27/11 , H01L27/1104
摘要： In accordance with an embodiment of the present invention, a static random access memory (SRAM) cell comprises a first pull-down transistor, a first pull-up transistor, a first pass-gate transistor, a second pull-down transistor, a second pull-up transistor, a second pass-gate transistor, a first linear intra-cell connection, and a second linear intra-cell connection. Active areas of the transistors are disposed in a substrate, and longitudinal axes of the active areas of the transistors are all parallel. The first linear intra-cell connection electrically couples the active area of the first pull-down transistor, the active area of the first pull-up transistor, and the active area of the first pass-gate transistor to a gate electrode of the second pull-down transistor and a gate electrode of the second pull-up transistor. The second linear intra-cell connection electrically couples the active area of the second pull-down transistor, the active area of the second pull-up transistor, and the active area of the second pass-gate transistor to a gate electrode of the first pull-down transistor and a gate electrode of the first pull-up transistor.
摘要翻译：根据本发明的实施例，静态随机存取存储器（SRAM）单元包括第一下拉晶体管，第一上拉晶体管，第一通过栅极晶体管，第二下拉晶体管，第二上拉晶体管，第二通孔晶体管，第一线性单元内连接和第二线性单元内连接。晶体管的有源区域设置在衬底中，并且晶体管的有源区域的纵轴全部是平行的。第一线性单元间连接将第一下拉晶体管的有源区域，第一上拉晶体管的有效区域和第一通过栅极晶体管的有源区域电耦合到第二拉伸的栅电极下降晶体管和第二上拉晶体管的栅电极。第二线性单元间连接将第二下拉晶体管的有效区域，第二上拉晶体管的有效区域和第二通过栅极晶体管的有源区域电耦合到第一拉拔的栅电极下降晶体管和第一上拉晶体管的栅电极。

2. 发明申请

US20100237419A1 Static Random Access Memory (SRAM) Cell and Method for Forming Same 有权
标题翻译：静态随机存取存储器（SRAM）单元及其形成方法
公开(公告)号：US20100237419A1
公开(公告)日：2010-09-23
申请号：US12408193
申请日：2009-03-20
申请人： Lie-Yong Yang , Feng-Ming Chang , Chang-Ta Yang , Ping-Wei Wang
发明人： Lie-Yong Yang , Feng-Ming Chang , Chang-Ta Yang , Ping-Wei Wang
IPC分类号： H01L27/11 , H01L21/768
CPC分类号： H01L27/088 , H01L27/0207 , H01L27/0886 , H01L27/11 , H01L27/1104
摘要： In accordance with an embodiment of the present invention, a static random access memory (SRAM) cell comprises a first pull-down transistor, a first pull-up transistor, a first pass-gate transistor, a second pull-down transistor, a second pull-up transistor, a second pass-gate transistor, a first linear intra-cell connection, and a second linear intra-cell connection. Active areas of the transistors are disposed in a substrate, and longitudinal axes of the active areas of the transistors are all parallel. The first linear intra-cell connection electrically couples the active area of the first pull-down transistor, the active area of the first pull-up transistor, and the active area of the first pass-gate transistor to a gate electrode of the second pull-down transistor and a gate electrode of the second pull-up transistor. The second linear intra-cell connection electrically couples the active area of the second pull-down transistor, the active area of the second pull-up transistor, and the active area of the second pass-gate transistor to a gate electrode of the first pull-down transistor and a gate electrode of the first pull-up transistor.
摘要翻译：根据本发明的实施例，静态随机存取存储器（SRAM）单元包括第一下拉晶体管，第一上拉晶体管，第一通过栅极晶体管，第二下拉晶体管，第二上拉晶体管，第二通孔晶体管，第一线性单元内连接和第二线性单元内连接。晶体管的有源区域设置在衬底中，并且晶体管的有源区域的纵轴全部是平行的。第一线性单元间连接将第一下拉晶体管的有源区域，第一上拉晶体管的有效区域和第一通过栅极晶体管的有源区域电耦合到第二拉伸的栅电极下降晶体管和第二上拉晶体管的栅电极。第二线性单元间连接将第二下拉晶体管的有效区域，第二上拉晶体管的有效区域和第二通过栅极晶体管的有源区域电耦合到第一拉拔的栅电极下降晶体管和第一上拉晶体管的栅电极。

3. 发明授权

US08492215B2 Static random access memory (SRAM) cell and method for forming same 有权
标题翻译：静态随机存取存储器（SRAM）单元及其形成方法
公开(公告)号：US08492215B2
公开(公告)日：2013-07-23
申请号：US13183127
申请日：2011-07-14
申请人： Lie-Yong Yang , Feng-Ming Chang , Chang-Ta Yang , Ping-Wei Wang
发明人： Lie-Yong Yang , Feng-Ming Chang , Chang-Ta Yang , Ping-Wei Wang
IPC分类号： H01L21/337
CPC分类号： H01L27/088 , H01L27/0207 , H01L27/0886 , H01L27/11 , H01L27/1104
摘要： An embodiment is a method for forming a static random access memory (SRAM) cell. The method comprises forming transistors on a semiconductor substrate and forming a first linear intra-cell connection and a second linear intra-cell connection. Longitudinal axes of the active areas of the transistors are parallel. A first pull-down transistor and a first pull-up transistor share a first common gate structure, and a second pull-down transistor and a second pull-up transistor share a second common gate structure. The first linear intra-cell connection electrically couples active areas of the first pull-down transistor and the first pull-up transistor to the second common gate structure. The second linear intra-cell connection electrically couples active areas of the second pull-down transistor and the second pull-up transistor to the first common gate structure.
摘要翻译：实施例是用于形成静态随机存取存储器（SRAM）单元的方法。该方法包括在半导体衬底上形成晶体管并形成第一线性小区内连接和第二线性小区内连接。晶体管的有源区的纵轴是平行的。第一下拉晶体管和第一上拉晶体管共享第一公共栅极结构，并且第二下拉晶体管和第二上拉晶体管共享第二公共栅极结构。第一线性单元间连接将第一下拉晶体管和第一上拉晶体管的有源区域电耦合到第二公共栅极结构。第二线性单元间连接将第二下拉晶体管和第二上拉晶体管的有源区域电耦合到第一公共栅极结构。

4. 发明申请

US20110269275A1 Static Random Access Memory (SRAM) Cell and Method for Forming Same 有权
标题翻译：静态随机存取存储器（SRAM）单元及其形成方法
公开(公告)号：US20110269275A1
公开(公告)日：2011-11-03
申请号：US13183127
申请日：2011-07-14
申请人： Lie-Yong Yang , Feng-Ming Chang , Chang-Ta Yang , Ping-Wei Wang
发明人： Lie-Yong Yang , Feng-Ming Chang , Chang-Ta Yang , Ping-Wei Wang
IPC分类号： H01L21/337
CPC分类号： H01L27/088 , H01L27/0207 , H01L27/0886 , H01L27/11 , H01L27/1104
摘要： An embodiment is a method for forming a static random access memory (SRAM) cell. The method comprises forming transistors on a semiconductor substrate and forming a first linear intra-cell connection and a second linear intra-cell connection. Longitudinal axes of the active areas of the transistors are parallel. A first pull-down transistor and a first pull-up transistor share a first common gate structure, and a second pull-down transistor and a second pull-up transistor share a second common gate structure. The first linear intra-cell connection electrically couples active areas of the first pull-down transistor and the first pull-up transistor to the second common gate structure. The second linear intra-cell connection electrically couples active areas of the second pull-down transistor and the second pull-up transistor to the first common gate structure.
摘要翻译：实施例是用于形成静态随机存取存储器（SRAM）单元的方法。该方法包括在半导体衬底上形成晶体管并形成第一线性小区内连接和第二线性小区内连接。晶体管的有源区的纵轴是平行的。第一下拉晶体管和第一上拉晶体管共享第一公共栅极结构，并且第二下拉晶体管和第二上拉晶体管共享第二公共栅极结构。第一线性单元间连接将第一下拉晶体管和第一上拉晶体管的有源区域电耦合到第二公共栅极结构。第二线性单元间连接将第二下拉晶体管和第二上拉晶体管的有源区域电耦合到第一公共栅极结构。

5. 发明授权

US09152039B2 Multiple patterning technology method and system for achieving minimal pattern mismatch 有权
标题翻译：用于实现最小图案不匹配的多种图案化技术方法和系统
公开(公告)号：US09152039B2
公开(公告)日：2015-10-06
申请号：US13275899
申请日：2011-10-18
申请人： Feng-Ming Chang , Chang-Ta Yang , Ping-Wei Wang , Min Cao
发明人： Feng-Ming Chang , Chang-Ta Yang , Ping-Wei Wang , Min Cao
IPC分类号： G06F17/50 , G03F1/68 , H01L27/02 , G03F7/00 , H01L27/11
CPC分类号： G03F1/68 , G03F1/70 , G03F7/0005 , H01L27/0207 , H01L27/1104
摘要： The present disclosure provides for many different embodiments of a multiple patterning technology method and system. An exemplary method includes receiving a pattern layout having a plurality of features; coloring each of the plurality of features one of at least two colors, thereby forming a colored pattern layout, wherein the coloring includes coloring match-sensitive features a same color; and fabricating at least two masks with the features of the colored pattern layout, wherein each mask includes features of a single color.
摘要翻译：本公开提供了多种图案化技术方法和系统的许多不同实施例。一种示例性方法包括接收具有多个特征的图案布局; 将多个特征中的每一个着色为至少两种颜色中的一种，从而形成着色图案布局，其中着色包括对相同颜色的匹配敏感特征进行着色; 以及制造具有着色图案布局的特征的至少两个掩模，其中每个掩模包括单一颜色的特征。

6. 发明授权

US08642451B2 Active region patterning in double patterning processes 有权
标题翻译：双重图案化工艺中的有源区域图案化
公开(公告)号：US08642451B2
公开(公告)日：2014-02-04
申请号：US12917205
申请日：2010-11-01
申请人： Feng-Ming Chang , Chang-Ta Yang , Huai-Ying Huang , Ping-Wei Wang , Hsiang-Lin Chen
发明人： Feng-Ming Chang , Chang-Ta Yang , Huai-Ying Huang , Ping-Wei Wang , Hsiang-Lin Chen
IPC分类号： H01L21/20
CPC分类号： H01L27/1104 , H01L27/0207
摘要： A method includes forming an SRAM cell including a first and a second pull-up transistor and a first and a second pull-down transistor. The step of forming the SRAM cell includes forming a first and a second active region of the first and the second pull-up transistors using a first lithography mask, and forming a third and a fourth active region of the first and the second pull-down transistors using a second lithography mask.
摘要翻译：一种方法包括形成包括第一和第二上拉晶体管以及第一和第二下拉晶体管的SRAM单元。形成SRAM单元的步骤包括使用第一光刻掩模形成第一和第二上拉晶体管的第一和第二有源区，并且形成第一和第二下拉的第三和第四有源区使用第二光刻掩模的晶体管。

7. 发明申请

US20130094035A1 MULTIPLE PATTERNING TECHNOLOGY METHOD AND SYSTEM FOR ACHIEVING MINIMAL PATTERN MISMATCH 有权
标题翻译：用于实现最小图案误差的多种格局技术方法和系统
公开(公告)号：US20130094035A1
公开(公告)日：2013-04-18
申请号：US13275899
申请日：2011-10-18
申请人： Feng-Ming Chang , Chang-Ta Yang , Ping-Wei Wang , Min Cao
发明人： Feng-Ming Chang , Chang-Ta Yang , Ping-Wei Wang , Min Cao
IPC分类号： H04N1/60
CPC分类号： G03F1/68 , G03F1/70 , G03F7/0005 , H01L27/0207 , H01L27/1104
摘要： The present disclosure provides for many different embodiments of a multiple patterning technology method and system. An exemplary method includes receiving a pattern layout having a plurality of features; coloring each of the plurality of features one of at least two colors, thereby forming a colored pattern layout, wherein the coloring includes coloring match-sensitive features a same color; and fabricating at least two masks with the features of the colored pattern layout, wherein each mask includes features of a single color.
摘要翻译：本公开提供了多种图案化技术方法和系统的许多不同实施例。一种示例性方法包括接收具有多个特征的图案布局; 将多个特征中的每一个着色为至少两种颜色中的一种，从而形成着色图案布局，其中着色包括对相同颜色的匹配敏感特征进行着色; 以及制造具有着色图案布局的特征的至少两个掩模，其中每个掩模包括单一颜色的特征。

8. 发明授权

US08315085B1 SRAM timing tracking circuit 有权
标题翻译： SRAM定时跟踪电路
公开(公告)号：US08315085B1
公开(公告)日：2012-11-20
申请号：US13289030
申请日：2011-11-04
申请人： Feng-Ming Chang , Chang-Ta Yang , Huai-Ying Huang , Ping-Wei Wang
发明人： Feng-Ming Chang , Chang-Ta Yang , Huai-Ying Huang , Ping-Wei Wang
IPC分类号： G11C11/00
CPC分类号： G11C29/24 , G11C11/41 , G11C29/50012
摘要： A timing tracking circuit is configured within a functional memory array, obviating the need for a separate, standalone timing tracking circuit. A generated pulse is routed circuitously through conductors enlisted for timing purposes, to trigger switching of a test cell in the array, which discharges an associated bit line from a pre-charged high value. The pulled down signal resulting from the discharge is detected at a measurement unit to infer timing characteristics of the memory array. The timing tracking circuitry is implemented by re-purposing certain conductors, test cells and dummy cells inserting certain conductive or nonconductive regions at one or more layers or at vias between layers to alter operation of the respective conductors and cells. Cells and conductors not enlisted for timing remain available for efficient, reliable memory access performance.
摘要翻译：定时跟踪电路配置在功能存储器阵列内，消除了对单独的独立定时跟踪电路的需要。所产生的脉冲通过定时目的的导体被路由布线，以触发阵列中的测试单元的切换，该预定电荷从预充电的高值放电相关联的位线。在测量单元处检测由放电产生的下拉信号以推断存储器阵列的定时特性。定时跟踪电路通过重新使用某些导体，测试单元和虚设单元来实现，所述导体，测试单元和虚设单元在层之间或层之间的通孔处插入某些导电或非导电区域，以改变相应导体和单元的操作。不用于定时的单元和导体仍然可用于高效，可靠的存储器访问性能。

9. 发明申请

US20120108036A1 Active Region Patterning in Double Patterning Processes 有权
标题翻译：双重图案化过程中的活动区域图案化
公开(公告)号：US20120108036A1
公开(公告)日：2012-05-03
申请号：US12917205
申请日：2010-11-01
申请人： Feng-Ming Chang , Chang-Ta Yang , Huai-Ying Huang , Ping-Wei Wang , Hsiang-Lin Chen
发明人： Feng-Ming Chang , Chang-Ta Yang , Huai-Ying Huang , Ping-Wei Wang , Hsiang-Lin Chen
IPC分类号： H01L21/20
CPC分类号： H01L27/1104 , H01L27/0207
摘要： A method includes forming an SRAM cell including a first and a second pull-up transistor and a first and a second pull-down transistor. The step of forming the SRAM cell includes forming a first and a second active region of the first and the second pull-up transistors using a first lithography mask, and forming a third and a fourth active region of the first and the second pull-down transistors using a second lithography mask.
摘要翻译：一种方法包括形成包括第一和第二上拉晶体管以及第一和第二下拉晶体管的SRAM单元。形成SRAM单元的步骤包括使用第一光刻掩模形成第一和第二上拉晶体管的第一和第二有源区，并且形成第一和第二下拉的第三和第四有源区使用第二光刻掩模的晶体管。

10. 发明授权

US08461634B2 Divot engineering for enhanced device performance 有权
标题翻译： Divot工程用于增强设备性能
公开(公告)号：US08461634B2
公开(公告)日：2013-06-11
申请号：US13087016
申请日：2011-04-14
申请人： Lie-Yong Yang , Sheng Chiang Hung , Kian-Long Lim , Ping-Wei Wang
发明人： Lie-Yong Yang , Sheng Chiang Hung , Kian-Long Lim , Ping-Wei Wang
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L21/28123 , H01L21/76229 , H01L21/76232 , H01L29/41783 , H01L29/665 , H01L29/6659 , H01L29/66628 , H01L29/7834
摘要： An integrated circuit device and method for manufacturing the same are disclosed. An exemplary device includes a semiconductor substrate having a substrate surface; a trench isolation structure disposed in the semiconductor substrate, the trench isolation structure having a trench isolation structure surface that is substantially planar to the substrate surface; and a gate feature disposed over the semiconductor substrate, wherein the gate feature includes a portion that extends from the substrate surface to a depth in the trench isolation structure, the portion being defined by a trench isolation structure sidewall and a semiconductor substrate sidewall, such that the portion tapers from a first width at the substrate surface to a second width at the depth, the first width being greater than the second width.
摘要翻译：公开了一种集成电路器件及其制造方法。示例性器件包括具有衬底表面的半导体衬底; 设置在所述半导体衬底中的沟槽隔离结构，所述沟槽隔离结构具有与所述衬底表面基本平坦的沟槽隔离结构表面; 以及设置在所述半导体衬底上的栅极特征，其中所述栅极特征包括从所述衬底表面延伸到所述沟槽隔离结构中的深度的部分，所述部分由沟槽隔离结构侧壁和半导体衬底侧壁限定，使得该部分从衬底表面的第一宽度到深度处的第二宽度逐渐变细，第一宽度大于第二宽度。

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