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    • 33. 发明授权
    • Method and apparatus for electrochemical planarization of a workpiece
    • 工件电化学平面化的方法和装置
    • US06464855B1
    • 2002-10-15
    • US09679473
    • 2000-10-04
    • Saket ChaddaChris Barns
    • Saket ChaddaChris Barns
    • C25F316
    • B24B37/046B23H5/08B24B37/042C25F7/00H01L21/32125
    • An electrochemical planarization apparatus for planarizing a metallized surface on a workpiece includes a platen, a conductive element disposed adjacent the platen and a polishing surface disposed adjacent the conductive element. A workpiece carrier is configured to carry a workpiece and press the workpiece against the polishing surface while causing relative motion between the workpiece and the polishing surface. A voltage source is configured to effect an electric potential difference between the metallized surface on the workpiece and the conductive element so that an electric field is produced between the metallized surface and the conductive element. The apparatus further includes a solution application mechanism configured to supply an electrolytic solution to the polishing surface.
    • 用于平坦化工件上的金属化表面的电化学平面化装置包括压板,邻近压板设置的导电元件和邻近导电元件设置的抛光表面。 工件载体构造成承载工件并将工件压靠在抛光表面上,同时引起工件和抛光表面之间的相对运动。 电压源被配置为实现工件上的金属化表面与导电元件之间的电位差,使得在金属化表面和导电元件之间产生电场。 该设备还包括一个配置成将电解液供应到抛光表面的溶液施加机构。
    • 38. 发明申请
    • Poly open polish process
    • 多孔开放抛光工艺
    • US20060134916A1
    • 2006-06-22
    • US11015151
    • 2004-12-17
    • Matthew PrinceFrancis TambweChris Barns
    • Matthew PrinceFrancis TambweChris Barns
    • H01L21/8234H01L21/461
    • H01L21/31053H01L29/6659H01L29/7833
    • A method of fabricating microelectronic structure using at least two material removal steps, such as for in a poly open polish process, is disclosed. In one embodiment, the first removal step may be chemical mechanical polishing (CMP) step utilizing a slurry with high selectivity to an interlevel dielectric layer used relative to an etch stop layer abutting a transistor gate. This allows the first CMP step to stop after contacting the etch stop layer, which results in substantially uniform “within die”, “within wafer”, and “wafer to wafer” topography. The removal step may expose a temporary component, such as a polysilicon gate within the transistor gate structure. Once the polysilicon gate is exposed other processes may be employed to produce a transistor gate having desired properties.
    • 公开了一种使用至少两种材料去除步骤制造微电子结构的方法,例如在多孔开式抛光工艺中。 在一个实施例中,第一去除步骤可以是利用相对于邻接晶体管栅极的蚀刻停止层使用的层间介电层具有高选择性的浆料的化学机械抛光(CMP)步骤。 这允许第一CMP步骤在接触蚀刻停止层之后停止,这导致基本上均匀的“在晶片内”,“在晶片内”和“晶片到晶片”形态。 去除步骤可以暴露诸如晶体管栅极结构内的多晶硅栅极的临时元件。 一旦多晶硅栅极被暴露,可以采用其它工艺来产生具有期望特性的晶体管栅极。