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1. 发明申请

US20060134916A1 Poly open polish process 有权
标题翻译：多孔开放抛光工艺
公开(公告)号：US20060134916A1
公开(公告)日：2006-06-22
申请号：US11015151
申请日：2004-12-17
申请人： Matthew Prince , Francis Tambwe , Chris Barns
发明人： Matthew Prince , Francis Tambwe , Chris Barns
IPC分类号： H01L21/8234 , H01L21/461
CPC分类号： H01L21/31053 , H01L29/6659 , H01L29/7833
摘要： A method of fabricating microelectronic structure using at least two material removal steps, such as for in a poly open polish process, is disclosed. In one embodiment, the first removal step may be chemical mechanical polishing (CMP) step utilizing a slurry with high selectivity to an interlevel dielectric layer used relative to an etch stop layer abutting a transistor gate. This allows the first CMP step to stop after contacting the etch stop layer, which results in substantially uniform “within die”, “within wafer”, and “wafer to wafer” topography. The removal step may expose a temporary component, such as a polysilicon gate within the transistor gate structure. Once the polysilicon gate is exposed other processes may be employed to produce a transistor gate having desired properties.
摘要翻译：公开了一种使用至少两种材料去除步骤制造微电子结构的方法，例如在多孔开式抛光工艺中。在一个实施例中，第一去除步骤可以是利用相对于邻接晶体管栅极的蚀刻停止层使用的层间介电层具有高选择性的浆料的化学机械抛光（CMP）步骤。这允许第一CMP步骤在接触蚀刻停止层之后停止，这导致基本上均匀的“在晶片内”，“在晶片内”和“晶片到晶片”形态。去除步骤可以暴露诸如晶体管栅极结构内的多晶硅栅极的临时元件。一旦多晶硅栅极被暴露，可以采用其它工艺来产生具有期望特性的晶体管栅极。

2. 发明申请

US20060135046A1 Multi-platen multi-slurry chemical mechanical polishing process 失效
公开(公告)号：US20060135046A1
公开(公告)日：2006-06-22
申请号：US11014889
申请日：2004-12-17
申请人： Matthew Prince , Mansour Moinpour , Francis Tambwe , Gary Ding
发明人： Matthew Prince , Mansour Moinpour , Francis Tambwe , Gary Ding
IPC分类号： B24B7/30
CPC分类号： H01L21/31053 , B24B27/0076 , B24B37/042
摘要： A multi-platen, multi-slurry chemical mechanical polishing method comprises providing a substrate having a surface that includes at least one nitride structure and an oxide layer atop the nitride structure, performing a first CMP process on the substrate using a first platen with a silica based slurry to remove a bulk portion of the oxide layer without exposing the nitride structure, performing a second CMP process on the substrate using a second platen with a ceria based slurry to remove a residual portion of the oxide layer and to expose at least a portion of the nitride structure, and performing a third CMP process on the substrate using the first platen with a silica based slurry to remove at least one defect caused by the ceria based slurry.

3. 发明申请

US20070077765A1 Etch stop and hard mask film property matching to enable improved replacement metal gate process 有权
标题翻译：蚀刻停止和硬掩模膜性能匹配，以改进替换金属浇口工艺
公开(公告)号：US20070077765A1
公开(公告)日：2007-04-05
申请号：US11240839
申请日：2005-09-30
申请人： Matthew Prince , Chris Barns , Justin Brask
发明人： Matthew Prince , Chris Barns , Justin Brask
IPC分类号： H01L21/311
CPC分类号： H01L21/31111 , H01L29/66545 , Y10S438/926
摘要： A method including forming a hard mask and an etch stop layer over a sacrificial material patterned as a gate electrode, wherein a material for the hard mask and a material for the etch stop layer are selected to have a similar stress property; removing the material for the hard mask and the material for the etch stop layer sufficient to expose the sacrificial material; replacing the sacrificial material with another material. A system including a computing device including a microprocessor, the microprocessor including a plurality of transistor devices, at least one of the plurality of transistor devices including a gate electrode formed on a substrate surface; a discontinuous etch stop layer conformally formed on the substrate surface and adjacent side wall surfaces of the gate electrode; and a dielectric material conformally formed over the etch stop layer.
摘要翻译：一种方法，包括在图案化为栅电极的牺牲材料上形成硬掩模和蚀刻停止层，其中用于硬掩模的材料和用于蚀刻停止层的材料被选择为具有类似的应力特性; 去除用于硬掩模的材料和足以暴露牺牲材料的用于蚀刻停止层的材料; 用另一种材料代替牺牲材料。一种包括包括微处理器的计算设备的系统，所述微处理器包括多个晶体管器件，所述多个晶体管器件中的至少一个晶体管器件包括形成在衬底表面上的栅电极; 保形地形成在栅电极的基板表面和相邻的侧壁表面上的不连续的蚀刻停止层; 以及保形地形成在蚀刻停止层上的电介质材料。

4. 发明申请

US20050246344A1 Method and system for a reliable distributed category-specific do-not-contact list 有权
标题翻译：可靠的分布式特定类别的不联系人列表的方法和系统
公开(公告)号：US20050246344A1
公开(公告)日：2005-11-03
申请号：US10835696
申请日：2004-04-29
申请人： Arthur Keller , Lee Holloway , John Rodrigues , Dat Nguyen , Thomas Belote , Matthew Prince
发明人： Arthur Keller , Lee Holloway , John Rodrigues , Dat Nguyen , Thomas Belote , Matthew Prince
IPC分类号： G06F7/00 , G06Q30/00 , H04L12/58
CPC分类号： H04L51/12 , G06Q30/02
摘要： A computer implemented method comprising receiving a list of one or more contact points from a sender and comparing the list of one or more contact points to a satellite server's do-not-contact list. Any contact point on the list of one or more contact points that appears on the satellite server's do-not-contact list is reported to the sender. The satellite server's do-not-contact list is generated from a do-not-contact list distributed by a master server. A registrant registers with the master server to provide a registrant contact point to be on the do-not-contact list to be distributed by the master server. The contact points in the registry may be organized in a hierarchy with preferences at one or more levels.
摘要翻译：一种计算机实现的方法，包括从发送者接收一个或多个接触点的列表，并将一个或多个接触点的列表与卫星服务器的不接触列表进行比较。在卫星服务器的不联络人列表上显示的一个或多个联络点的列表上的任何联络点都会向发件人报告。卫星服务器的不接触列表是由主服务器分发的不联络列表生成的。注册人向主服务器注册，以向主服务器分发的不联系人列表提供注册人联系人。注册表中的联系点可以组织在具有一个或多个级别的偏好的层次结构中。

5. 发明申请

US20050164609A1 Reducing wafer defects from chemical mechanical polishing 审中-公开
标题翻译：从化学机械抛光中减少晶圆缺陷
公开(公告)号：US20050164609A1
公开(公告)日：2005-07-28
申请号：US10762849
申请日：2004-01-22
申请人： Matthew Prince , Shaestagir Chowdhury , Brian Weselak , Jim Xu
发明人： Matthew Prince , Shaestagir Chowdhury , Brian Weselak , Jim Xu
IPC分类号： B24B1/00 , H01L21/321
CPC分类号： H01L21/3212
摘要： Tantalum barrier layer chemical mechanical polishing may be improved by using suitably aged slurries. Slurries that are older than fifty days from their manufacture date result in significantly lower occurrences of defects.
摘要翻译：通过使用适当老化的浆料可以改善钽阻隔层化学机械抛光。从制造日期起超过五十天的浆料导致缺陷发生率显着降低。

6. 发明授权

US6087733A Sacrificial erosion control features for chemical-mechanical polishing process 失效
标题翻译：用于化学机械抛光工艺的牺牲侵蚀控制功能
公开(公告)号：US6087733A
公开(公告)日：2000-07-11
申请号：US94541
申请日：1998-06-12
申请人： Michael A. Maxim , Michael Kocsis , Ning Hsieh , Matthew Prince , Kenneth C. Cadien
发明人： Michael A. Maxim , Michael Kocsis , Ning Hsieh , Matthew Prince , Kenneth C. Cadien
IPC分类号： H01L21/321 , H01L21/768 , H01L23/544 , H01L21/301 , H01L21/302 , H01L21/76
CPC分类号： H01L23/544 , H01L21/3212 , H01L21/7684 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002
摘要： A method and apparatus for compensating for the effects of nonuniform planarization in chemical-mechanical polishing (CMP) such as the erosion occurring from the removal of titanium nitride/tungsten films is disclosed. In the context of alignment marks, dummy marks are disposed on both sides of the actual alignment marks providing a similar feature density as the alignment marks. During the CMP, the dummy marks reside in the area of nonuniform erosion, leaving the actual marks in an area of uniform erosion. The present invention may also be used to control underlayer erosion variations in the high feature density device areas adjacent to the low feature density open areas by providing dummy features in the low feature density areas.
摘要翻译：公开了一种用于补偿化学机械抛光（CMP）中不均匀平面化的影响的方法和装置，例如从去除氮化钛/钨膜而发生的侵蚀。在对准标记的上下文中，虚拟标记设置在实际对准标记的两侧，提供与对准标记相似的特征密度。在CMP期间，虚拟标记位于不均匀侵蚀的区域，留下实际痕迹在均匀侵蚀的区域。本发明还可以用于通过在低特征密度区域中提供虚拟特征来控制与低特征密度开放区域相邻的高特征密度装置区域中的底层侵蚀变化。

7. 发明申请

US20050170750A1 Polish pad to change polish rate on wafer by adjusting groove width and density 审中-公开
标题翻译：抛光垫通过调节槽宽度和密度来改变晶片上的抛光速率
公开(公告)号：US20050170750A1
公开(公告)日：2005-08-04
申请号：US11089738
申请日：2005-03-24
申请人： Ebrahim Andideh , Matthew Prince
发明人： Ebrahim Andideh , Matthew Prince
IPC分类号： B24B1/00 , B24B7/19 , B24B37/26 , H01L21/461 , B24B49/00
CPC分类号： B24B37/26
摘要： The present invention describes a method for creating a differential polish rate across a semiconductor wafer. The profile or topography of the semiconductor wafer is determined by locating the high points and low points of the wafer profile. The groove pattern of a polish pad is then adjusted to optimize the polish rate with respect to the particular wafer profile. By increasing the groove depth, width, and/or density of the groove pattern of the polish pad the polish rate may be increased in the areas that correspond to the high points of the wafer profile. By decreasing the groove depth, width, and/or density of the groove pattern of the polish pad the polish rate may be decreased in the areas that correspond to the low points of the wafer profile. A combination of these effects may be desirable in order to stabilize the polish rate across the wafer surface in order to improve the planarization of the polishing process.
摘要翻译：本发明描述了一种用于在半导体晶片上产生差分抛光速率的方法。通过定位晶片轮廓的高点和低点来确定半导体晶片的轮廓或形貌。然后调整抛光垫的凹槽图案以优化相对于特定晶片轮廓的抛光速率。通过增加抛光垫的凹槽图案的凹槽深度，宽度和/或密度，可以在对应于晶片轮廓的高点的区域中增加抛光速率。通过减小抛光垫的凹槽图案的凹槽深度，宽度和/或密度，在对应于晶片轮廓的低点的区域中抛光速率可能会降低。为了稳定晶片表面的抛光速率，为了改善抛光工艺的平坦化，可能需要这些效果的组合。

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