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1. 发明申请

US20060141222A1 Introducing nanotubes in trenches and structures formed thereby 失效
标题翻译：在由此形成的沟槽和结构中引入纳米管
公开(公告)号：US20060141222A1
公开(公告)日：2006-06-29
申请号：US11026320
申请日：2004-12-29
申请人： Paul Fischer , Anne Miller , Kenneth Cadien , Chris Barns
发明人： Paul Fischer , Anne Miller , Kenneth Cadien , Chris Barns
IPC分类号： B32B3/00
CPC分类号： B82Y10/00 , B82Y30/00 , H01L51/0012 , H01L51/0048 , H01L51/0052 , Y10S977/72 , Y10T428/24562 , Y10T428/24612 , Y10T428/24744
摘要： Methods of forming a microelectronic structure are described. Embodiments of those methods include providing a substrate comprising at least one opening, and then applying a nanotube slurry comprising at least one nanotube to the substrate, wherein the at least one nanotube is substantially placed within the at least one opening.
摘要翻译：描述形成微电子结构的方法。这些方法的实施方案包括提供包含至少一个开口的基底，然后将包含至少一个纳米管的纳米管浆料施加到所述基底，其中所述至少一个纳米管基本上放置在所述至少一个开口内。

2. 发明申请

US20060046523A1 Facilitating removal of sacrificial layers to form replacement metal gates 审中-公开
标题翻译：有助于去除牺牲层以形成更换金属门
公开(公告)号：US20060046523A1
公开(公告)日：2006-03-02
申请号：US10925458
申请日：2004-08-25
申请人： Jack Kavalieros , Justin Brask , Mark Doczy , Chris Barns , Matthew Metz , Suman Datta , Robert Chau , Matt Prince , Anne Miller , Mark Buehler
发明人： Jack Kavalieros , Justin Brask , Mark Doczy , Chris Barns , Matthew Metz , Suman Datta , Robert Chau , Matt Prince , Anne Miller , Mark Buehler
IPC分类号： H01L21/76
CPC分类号： H01L29/517 , H01L21/28079 , H01L21/28185 , H01L21/28194 , H01L21/823842 , H01L29/495 , H01L29/66545
摘要： Replacement metal gates may be formed by removing a polysilicon layer from a gate structure. The gate structure may be formed by patterning the polysilicon layer and depositing a spacer layer over the gate structure such that the spacer layer has a first polish rate. The spacer layer is then etched to form a sidewall spacer. An interlayer dielectric is applied over the gate structure with the sidewall spacer. The interlayer dielectric has a second polish rate higher than the first polish rate. In one embodiment, the interlayer dielectric has a lower polish rate than that of oxide.
摘要翻译：可以通过从栅极结构去除多晶硅层来形成替代金属栅极。栅极结构可以通过图案化多晶硅层并在栅极结构上沉积间隔层形成，使得间隔层具有第一抛光速率。然后对间隔层进行蚀刻以形成侧壁间隔物。在栅极结构上用侧壁间隔物施加层间电介质。层间电介质具有比第一抛光速率高的第二抛光速率。在一个实施例中，层间电介质具有比氧化物更低的抛光速率。

3. 发明申请

US20060008968A1 Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode 有权
标题翻译：制造具有高k栅极电介质层和金属栅电极的半导体器件的方法
公开(公告)号：US20060008968A1
公开(公告)日：2006-01-12
申请号：US10885958
申请日：2004-07-06
申请人： Justin Brask , Chris Barns , Mark Doczy , Uday Shah , Jack Kavalieros , Matthew Metz , Suman Datta , Anne Miller , Robert Chau
发明人： Justin Brask , Chris Barns , Mark Doczy , Uday Shah , Jack Kavalieros , Matthew Metz , Suman Datta , Anne Miller , Robert Chau
IPC分类号： H01L21/8238
CPC分类号： H01L29/66545 , H01L21/28185 , H01L21/28194 , H01L21/28229 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L21/823857 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, forming a trench within the dielectric layer, and forming a high-k gate dielectric layer within the trench. After forming a first metal layer on the high-k gate dielectric layer, a second metal layer is formed on the first metal layer. At least part of the second metal layer is removed from above the dielectric layer using a polishing step, and additional material is removed from above the dielectric layer using an etch step.
摘要翻译：描述制造半导体器件的方法。该方法包括在衬底上形成电介质层，在电介质层内形成沟槽，并在沟槽内形成高k栅介质层。在高k栅介质层上形成第一金属层之后，在第一金属层上形成第二金属层。使用抛光步骤从电介质层上方去除第二金属层的至少一部分，并且使用蚀刻步骤从电介质层上方除去附加材料。

4. 发明申请

US20050070093A1 Sacrificial dielectric planarization layer 失效
公开(公告)号：US20050070093A1
公开(公告)日：2005-03-31
申请号：US10674579
申请日：2003-09-29
申请人： Chris Barns , Kevin O'Brien , Anne Miller
发明人： Chris Barns , Kevin O'Brien , Anne Miller
IPC分类号： H01L21/3105 , H01L21/311 , H01L21/321 , H01L21/4763 , H01L21/768 , H01L21/8238
CPC分类号： H01L21/7684 , H01L21/31053 , H01L21/31144 , H01L21/3212
摘要： A method of forming a microelectronic structure and its associated structures is described. In one embodiment, a substrate is provided with a sacrificial layer disposed on a hard mask layer, and a metal layer disposed in a trench of the substrate and on the sacrificial layer. The metal layer is then removed at a first removal rate wherein a dishing is induced on a top surface of the metal layer until the sacrificial layer is exposed, and simultaneously removing the metal layer and the sacrificial layer at a second removal rate without substantially removing the hard mask.

5. 发明申请

US20050070061A1 Sacrificial dielectric planarization layer 失效
标题翻译：牺牲电介质平坦化层
公开(公告)号：US20050070061A1
公开(公告)日：2005-03-31
申请号：US10963839
申请日：2004-10-12
申请人： Chris Barns , Kevin O'Brien , Anne Miller
发明人： Chris Barns , Kevin O'Brien , Anne Miller
IPC分类号： H01L21/3105 , H01L21/311 , H01L21/321 , H01L21/4763 , H01L21/768 , H01L21/8238
CPC分类号： H01L21/7684 , H01L21/31053 , H01L21/31144 , H01L21/3212
摘要： A method of forming a microelectronic structure and its associated structures is described. That method comprises providing a substrate comprising a sacrificial layer disposed on a hard mask layer, and a metal layer disposed in a trench of the substrate and on the sacrificial layer, removing the metal layer at a first removal rate wherein a dishing is induced on a top surface of the metal layer until the sacrificial layer is exposed, and simultaneously removing the metal layer and the sacrificial layer at a second removal rate without substantially removing the hard mask.
摘要翻译：描述了形成微电子结构及其相关结构的方法。该方法包括提供包括设置在硬掩模层上的牺牲层的衬底和设置在衬底的沟槽中和在牺牲层上的金属层，以第一去除速率移除金属层，其中在直到牺牲层被暴露为止，同时以第二去除速率去除金属层和牺牲层而基本上不去除硬掩模。

6. 发明申请

US20060065633A1 Semiconductor substrate polishing methods and equipment 有权
公开(公告)号：US20060065633A1
公开(公告)日：2006-03-30
申请号：US10952655
申请日：2004-09-28
申请人： Paul Fischer , Chris Barns
发明人： Paul Fischer , Chris Barns
IPC分类号： C03C15/00 , H01L21/306 , C23F1/00 , B44C1/22
CPC分类号： H01L21/7684 , B24B37/042 , B24B37/046 , C25F3/02 , H01L21/32115 , H01L21/32125
摘要： According to one aspect of the present invention, a method of electrochemically polishing a semiconductor substrate may be provided. A semiconductor substrate processing fluid, having a plurality of abrasive particles therein, may be placed between the surface of the semiconductor substrate and the polish head. The polish head may be moved relative to the surface of the semiconductor substrate to cause the abrasive particles to polish the surface of the semiconductor substrate. According to a second aspect of the present invention, a method for electro-polishing a semiconductor substrate may be provided. A semiconductor substrate may be placed in an electrolytic solution. A surface of the semiconductor substrate may be contacted with at least one conductive member. A voltage may be applied across the electrolytic solution and the at least one conductive member. The at least one conductive member may be moved across the surface of the semiconductor substrate.

7. 发明申请

US20060272773A1 Semiconductor substrate polishing methods and equipment 审中-公开
标题翻译：半导体衬底抛光方法和设备
公开(公告)号：US20060272773A1
公开(公告)日：2006-12-07
申请号：US11506316
申请日：2006-08-17
申请人： Paul Fischer , Chris Barns
发明人： Paul Fischer , Chris Barns
IPC分类号： H01L21/306
CPC分类号： H01L21/7684 , B24B37/042 , B24B37/046 , C25F3/02 , H01L21/32115 , H01L21/32125
摘要： According to one aspect of the present invention, a method of electrochemically polishing a semiconductor substrate may be provided. A semiconductor substrate processing fluid, having a plurality of abrasive particles therein, may be placed between the surface of the semiconductor substrate and the polish head. The polish head may be moved relative to the surface of the semiconductor substrate to cause the abrasive particles to polish the surface of the semiconductor substrate. According to a second aspect of the present invention, a method for electro-polishing a semiconductor substrate may be provided. A semiconductor substrate may be placed in an electrolytic solution. A surface of the semiconductor substrate may be contacted with at least one conductive member. A voltage may be applied across the electrolytic solution and the at least one conductive member. The at least one conductive member may be moved across the surface of the semiconductor substrate.
摘要翻译：根据本发明的一个方面，可以提供一种电化学抛光半导体衬底的方法。可以在半导体衬底的表面和抛光头之间放置其中具有多个磨料颗粒的半导体衬底处理流体。抛光头可以相对于半导体衬底的表面移动，以使研磨颗粒抛光半导体衬底的表面。根据本发明的第二方面，可以提供一种用于电抛光半导体衬底的方法。可以将半导体衬底放置在电解液中。半导体衬底的表面可以与至少一个导电构件接触。可以在电解液和至少一个导电构件之间施加电压。至少一个导电构件可以跨过半导体衬底的表面移动。

8. 发明申请

US20070037372A1 Planarizing a semiconductor structure to form replacement metal gates 审中-公开
标题翻译：平面化半导体结构以形成替换金属栅极
公开(公告)号：US20070037372A1
公开(公告)日：2007-02-15
申请号：US11581183
申请日：2006-10-13
申请人： Jack Kavalieros , Justin Brask , Mark Doczy , Uday Shah , Chris Barns , Matthew Metz , Suman Datta , Robert Chau
发明人： Jack Kavalieros , Justin Brask , Mark Doczy , Uday Shah , Chris Barns , Matthew Metz , Suman Datta , Robert Chau
IPC分类号： H01L21/3205
CPC分类号： H01L21/28194 , H01L21/28079 , H01L21/28088 , H01L21/31111 , H01L21/32134 , H01L21/823807 , H01L21/823842 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/7843
摘要： A sacrificial gate structure, including nitride and fill layers, may be replaced with a metal gate electrode. The metal gate electrode may again be covered with a nitride layer covered by a fill layer. The replacement of the nitride and fill layers may reintroduce strain and provide an etch stop.
摘要翻译：包括氮化物和填充层的牺牲栅极结构可以被金属栅电极代替。金属栅电极可以再次被填充层覆盖的氮化物层覆盖。氮化物和填充层的替换可以重新引入应变并提供蚀刻停止。

9. 发明申请

US20050139928A1 Methods for integrating replacement metal gate structures 有权
标题翻译：集成替代金属门结构的方法
公开(公告)号：US20050139928A1
公开(公告)日：2005-06-30
申请号：US10748383
申请日：2003-12-29
申请人： Jack Kavalieros , Justin Brask , Mark Doczy , Scott Hareland , Matthew Metz , Chris Barns , Robert Chau
发明人： Jack Kavalieros , Justin Brask , Mark Doczy , Scott Hareland , Matthew Metz , Chris Barns , Robert Chau
IPC分类号： H01L21/8238 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/517 , H01L21/823842 , H01L29/495 , H01L29/66545 , Y10S438/926
摘要： Methods and associated structures of forming a microelectronic device are described. Those methods comprise providing a substrate comprising a first transistor structure comprising an n-type gate material and second transistor structure comprising a p-type gate material, selectively removing the n-type gate material to form a recess in the first gate structure, and then filling the recess with an n-type metal gate material.
摘要翻译：描述形成微电子器件的方法和相关结构。这些方法包括提供包括包括n型栅极材料的第一晶体管结构和包括p型栅极材料的第二晶体管结构的衬底，选择性地去除n型栅极材料以在第一栅极结构中形成凹陷，然后用n型金属栅极材料填充凹部。

10. 发明申请

US20070077765A1 Etch stop and hard mask film property matching to enable improved replacement metal gate process 有权
标题翻译：蚀刻停止和硬掩模膜性能匹配，以改进替换金属浇口工艺
公开(公告)号：US20070077765A1
公开(公告)日：2007-04-05
申请号：US11240839
申请日：2005-09-30
申请人： Matthew Prince , Chris Barns , Justin Brask
发明人： Matthew Prince , Chris Barns , Justin Brask
IPC分类号： H01L21/311
CPC分类号： H01L21/31111 , H01L29/66545 , Y10S438/926
摘要： A method including forming a hard mask and an etch stop layer over a sacrificial material patterned as a gate electrode, wherein a material for the hard mask and a material for the etch stop layer are selected to have a similar stress property; removing the material for the hard mask and the material for the etch stop layer sufficient to expose the sacrificial material; replacing the sacrificial material with another material. A system including a computing device including a microprocessor, the microprocessor including a plurality of transistor devices, at least one of the plurality of transistor devices including a gate electrode formed on a substrate surface; a discontinuous etch stop layer conformally formed on the substrate surface and adjacent side wall surfaces of the gate electrode; and a dielectric material conformally formed over the etch stop layer.
摘要翻译：一种方法，包括在图案化为栅电极的牺牲材料上形成硬掩模和蚀刻停止层，其中用于硬掩模的材料和用于蚀刻停止层的材料被选择为具有类似的应力特性; 去除用于硬掩模的材料和足以暴露牺牲材料的用于蚀刻停止层的材料; 用另一种材料代替牺牲材料。一种包括包括微处理器的计算设备的系统，所述微处理器包括多个晶体管器件，所述多个晶体管器件中的至少一个晶体管器件包括形成在衬底表面上的栅电极; 保形地形成在栅电极的基板表面和相邻的侧壁表面上的不连续的蚀刻停止层; 以及保形地形成在蚀刻停止层上的电介质材料。

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