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31. 发明申请

US20070264772A1 METHOD FOR FABRICATING RECESSED GATE MOS TRANSISTOR DEVICE 有权
标题翻译：用于制造接收栅极MOS晶体管器件的方法
公开(公告)号：US20070264772A1
公开(公告)日：2007-11-15
申请号：US11685756
申请日：2007-03-13
申请人： Yu-Pi Lee , Shian-Jyh Lin , Jar-Ming Ho
发明人： Yu-Pi Lee , Shian-Jyh Lin , Jar-Ming Ho
IPC分类号： H01L21/8242
CPC分类号： H01L29/66621 , H01L21/26586 , H01L21/28061 , H01L27/10823 , H01L27/10829 , H01L27/10876 , H01L27/10891 , H01L29/66545
摘要： A method of fabricating self-aligned gate trench utilizing trench top oxide (TTO) poly spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. A plurality of trench capacitors are embedded in a memory array region of the semiconductor substrate. Each of the trench capacitors has a TTO that extrudes from a main surface of the semiconductor substrate. Poly spacers are formed on two opposite sides of the extruding TTO and are used, after oxidized, as an etching hard mask for etching a recessed gate trench in close proximity to the trench capacitor.
摘要翻译：公开了一种使用沟槽顶部氧化物（TTO）聚合间隔物制造自对准栅极沟槽的方法。提供其上具有衬垫氧化物层和衬垫氮化物层的半导体衬底。多个沟槽电容器嵌入在半导体衬底的存储器阵列区域中。每个沟槽电容器具有从半导体衬底的主表面挤出的TTO。聚合物间隔物形成在挤出TTO的两个相对侧上，并且在氧化后用作蚀刻硬掩模，用于蚀刻紧邻沟槽电容器的凹陷栅极沟槽。

32. 发明授权

US07160804B2 Method of fabricating MOS transistor by millisecond anneal 有权
标题翻译：通过毫秒退火制造MOS晶体管的方法
公开(公告)号：US07160804B2
公开(公告)日：2007-01-09
申请号：US11174750
申请日：2005-07-05
申请人： Shian-Jyh Lin , Sheng-Tsung Chen , Neng-Tai Shih , Chien-Chang Huang , Chien-Jung Yang , Yi-Jung Chen
发明人： Shian-Jyh Lin , Sheng-Tsung Chen , Neng-Tai Shih , Chien-Chang Huang , Chien-Jung Yang , Yi-Jung Chen
IPC分类号： H01L21/4763
CPC分类号： H01L29/6659 , H01L21/324 , H01L29/7833
摘要： A method of fabricating a MOS transistor by millisecond annealing. A semiconductor substrate with a gate stack comprising a gate electrode overlying a gate dielectric layer on a top surface of a semiconductor substrate is provided. At least one implanting process is performed to form two doped regions on opposite sides of the gate electrode. Millisecond annealing activates dopants in the doped regions. The millisecond anneal includes rapid heating and rapid cooling within 1 to 50 milliseconds.
摘要翻译：一种通过毫秒退火制造MOS晶体管的方法。提供了具有栅叠层的半导体衬底，其包括覆盖半导体衬底的顶表面上的栅介质层的栅电极。执行至少一个注入工艺以在栅电极的相对侧上形成两个掺杂区域。毫秒退火激活掺杂区中的掺杂剂。毫秒退火包括快速加热和1至50毫秒内的快速冷却。

33. 发明申请

US20050245040A1 Method for forming deep trench capacitor with liquid phase deposition oxide as collar oxide 审中-公开
标题翻译：用作为环氧化物的液相沉积氧化物形成深沟槽电容器的方法
公开(公告)号：US20050245040A1
公开(公告)日：2005-11-03
申请号：US11039843
申请日：2005-01-24
申请人： Sam Liao , Shian-Jyh Lin , Chia-Sheng Yu
发明人： Sam Liao , Shian-Jyh Lin , Chia-Sheng Yu
IPC分类号： H01L21/334 , H01L21/8242 , H01L29/94
CPC分类号： H01L27/1087 , H01L29/66181 , H01L29/945
摘要： A method for forming a deep trench capacitor mainly utilizes a liquid phase deposition (LPD) oxide to form a collar oxide layer in the trench, followed by forming a conductive layer serving as an upper electrode of the deep trench capacitor, thereby avoiding collar oxide residue in the conductive layer and thus forming good electrical connection. And, the method of the present invention does not need a dry etch to remove the unnecessary collar oxide layer such that the process can be simplified.
摘要翻译：形成深沟槽电容器的方法主要利用液相沉积（LPD）氧化物在沟槽中形成环状氧化物层，随后形成用作深沟槽电容器的上电极的导电层，从而避免环氧化物残留物在导电层中，从而形成良好的电连接。而且，本发明的方法不需要干蚀刻来去除不需要的环形氧化物层，从而可以简化该方法。

34. 发明申请

US20050239282A1 Method for forming self-aligned contact in semiconductor device 有权
标题翻译：在半导体器件中形成自对准接触的方法
公开(公告)号：US20050239282A1
公开(公告)日：2005-10-27
申请号：US10940772
申请日：2004-09-15
申请人： Meng-Hung Chen , Shian-Jyh Lin , Chia-Sheng Yu
发明人： Meng-Hung Chen , Shian-Jyh Lin , Chia-Sheng Yu
IPC分类号： H01L21/4763 , H01L21/60
CPC分类号： H01L21/76897
摘要： A method for forming a self-aligned contact on a semiconductor substrate provided with a plurality of field-effect transistors. The method comprises the steps of forming a first insulating layer comprising a nitride along a profile of a gate structure and a junction region, forming a temporary layer comprising a doped oxide on the first insulating layer, removing a portion of the temporary layer by performing a selective etch of the oxide with a mask while leaving a plug portion of the temporary layer over the junction region, forming a second insulating layer comprising an undoped oxide in a region where the portion of the temporary layer is removed, removing the plug portion by performing a selective etch of the undoped oxide to form a contact hole, removing a portion of the first insulating layer at a bottom of the contact hole, and forming a conductive contact in the contact hole.
摘要翻译：一种用于在设置有多个场效应晶体管的半导体衬底上形成自对准接触的方法。该方法包括以下步骤：沿着栅极结构和结区的轮廓形成包括氮化物的第一绝缘层，在第一绝缘层上形成包括掺杂氧化物的临时层，通过执行临时层去除一部分临时层用掩模选择性地蚀刻氧化物，同时将临时层的插塞部分留在接合区域上，形成第二绝缘层，该第二绝缘层包括去除部分临时层的区域中的未掺杂的氧化物，通过执行对未掺杂的氧化物进行选择性蚀刻以形成接触孔，在接触孔的底部除去第一绝缘层的一部分，以及在接触孔中形成导电接触。

35. 发明申请

US20050221616A1 3-stage method for forming deep trench structure and deep trench capacitor 有权
标题翻译：形成深沟槽结构和深沟槽电容器的3阶段方法
公开(公告)号：US20050221616A1
公开(公告)日：2005-10-06
申请号：US10816820
申请日：2004-04-05
申请人： Meng-Hung Chen , Shian-Jyh Lin
发明人： Meng-Hung Chen , Shian-Jyh Lin
IPC分类号： B44C1/22 , H01L21/308 , H01L21/311 , H01L21/334 , H01L21/8242
CPC分类号： H01L29/66181 , H01L21/3081 , H01L27/1087
摘要： A method for forming a deep trench structure comprises the steps of providing a silicon substrate; forming a mask layer of a predetermined pattern on the silicon substrate to expose a portion of the silicon substrate; forming a first trench in the exposed portion of the silicon substrate, the first trench having a first depth; forming a nitride layer on the surfaces of the whole structure; forming a second trench in the first trench downward, the second trench having a second depth greater than the first depth; forming another nitride layer on the surfaces of the whole structure; and forming a third trench in the second trench downward, the third trench having a third depth greater than the second depth. The method of the present invention can make the whole trench have better etch uniformity, thereby obtaining good electrical performance.
摘要翻译：形成深沟槽结构的方法包括以下步骤：提供硅衬底; 在所述硅衬底上形成预定图案的掩模层以暴露所述硅衬底的一部分; 在所述硅衬底的暴露部分中形成第一沟槽，所述第一沟槽具有第一深度; 在整个结构的表面上形成氮化物层; 在所述第一沟槽中形成第二沟槽，所述第二沟槽具有大于所述第一深度的第二深度; 在整个结构的表面上形成另一个氮化物层; 以及在所述第二沟槽中向下形成第三沟槽，所述第三沟槽的第三深度大于所述第二深度。本发明的方法可以使整个沟槽具有更好的蚀刻均匀性，从而获得良好的电性能。

36. 发明申请

US20050221560A1 Method of forming a vertical memory device with a rectangular trench 审中-公开
标题翻译：形成具有矩形沟槽的垂直存储器件的方法
公开(公告)号：US20050221560A1
公开(公告)日：2005-10-06
申请号：US11139450
申请日：2005-05-27
申请人： Yu-Sheng Shu , Yuan-Hsun Wu , Chung-Yuan Lee , Shian-Jyh Lin
发明人： Yu-Sheng Shu , Yuan-Hsun Wu , Chung-Yuan Lee , Shian-Jyh Lin
IPC分类号： G03C5/00 , G03F1/00 , G03F9/00 , H01L21/027 , H01L21/308 , H01L21/336 , H01L21/76 , H01L21/8242 , H01L27/02
CPC分类号： H01L27/1087 , H01L21/3083 , H01L27/0207 , H01L27/10864
摘要： A method of forming a vertical memory device with a rectangular trench. First, a substrate covered by a photoresist layer is provided. Next, the photoresist layer is defined by a mask to form a rectangular opening, wherein the mask has two rectangular transparent patterns arranged with a predetermined interval. Next, the substrate is etched using the defined photoresist layer as a mask to form a single rectangular trench and the photoresist layer is then removed. Finally, a trench capacitor and a vertical transistor are successively formed in the rectangular trench to finish the vertical memory device.
摘要翻译：一种形成具有矩形沟槽的垂直存储器件的方法。首先，提供由光致抗蚀剂层覆盖的基板。接下来，通过掩模限定光致抗蚀剂层以形成矩形开口，其中掩模具有以预定间隔布置的两个矩形透明图案。接下来，使用限定的光致抗蚀剂层作为掩模来蚀刻基板以形成单个矩形沟槽，然后除去光致抗蚀剂层。最后，在矩形沟槽中依次形成沟槽电容器和垂直晶体管，以完成垂直存储器件。

37. 发明申请

US20050167721A1 Memory cell with a vertical transistor and fabrication method thereof 审中-公开
标题翻译：具有垂直晶体管的存储单元及其制造方法
公开(公告)号：US20050167721A1
公开(公告)日：2005-08-04
申请号：US10845909
申请日：2004-05-14
申请人： Shian-Jyh Lin , Yu-Sheng Hsu
发明人： Shian-Jyh Lin , Yu-Sheng Hsu
IPC分类号： H01L21/334 , H01L21/76 , H01L21/8242 , H01L27/108 , H01L29/732
CPC分类号： H01L29/66181 , H01L27/10841 , H01L27/10867
摘要： A memory cell with a vertical transistor has a semiconductor silicon substrate with a deep trench, in which the deep trench has a first sidewall region and a second sidewall region. A first insulating layer is formed overlying the first sidewall region. A second insulating layer is formed overlying the second sidewall region, in which the thickness of the first insulating layer is larger than the thickness of the second insulating layer. A gate electrode layer is sandwiched between the first insulating layer and the second insulating layer. A buried strap out-diffusion region is formed in the substrate adjacent to the second sidewall region, in which the buried strap out-diffusion region is located near the lower portion of the second insulating layer.
摘要翻译：具有垂直晶体管的存储单元具有深沟槽的半导体硅衬底，其中深沟槽具有第一侧壁区域和第二侧壁区域。第一绝缘层形成在第一侧壁区域的上方。第二绝缘层形成为覆盖第二侧壁区域，其中第一绝缘层的厚度大于第二绝缘层的厚度。栅电极层夹在第一绝缘层和第二绝缘层之间。掩埋带外扩散区域形成在邻近第二侧壁区域的衬底中，其中掩埋带外延扩散区域位于第二绝缘层的下部附近。

38. 发明申请

US20050130066A1 Method of forming single sided conductor and semiconductor device having the same 审中-公开
标题翻译：形成单面导体的方法和具有该单面导体的半导体器件
公开(公告)号：US20050130066A1
公开(公告)日：2005-06-16
申请号：US10731133
申请日：2003-12-10
申请人： Chin-Te Kuo , Jeng Lin , Shian-Jyh Lin , Tsan Lu
发明人： Chin-Te Kuo , Jeng Lin , Shian-Jyh Lin , Tsan Lu
IPC分类号： G03F7/00 , H01L21/32 , H01L21/768 , H01L21/8242
CPC分类号： H01L27/10867 , H01L21/32 , H01L21/76831 , H01L21/76877
摘要： A method of forming a single sided conductor and a semiconductor device having the same is provided. The method includes providing a substrate having an opening. The opening exposes a sidewall and an opening base surface. A tilted mask layer is formed in the opening. The tilted mask layer exposes the sidewall and a portion of the opening base surface. A dielectric layer is formed on the exposed sidewall and the exposed opening base surface. Then, the tilted mask layer is removed, and a conductive layer is formed over the substrate.
摘要翻译：提供了形成单面导体的方法和具有该单面导体的半导体器件。该方法包括提供具有开口的基底。开口露出侧壁和开口底面。在开口中形成倾斜的掩模层。倾斜的掩模层暴露侧壁和开口底面的一部分。在暴露的侧壁和暴露的开口基底表面上形成介电层。然后，去除倾斜的掩模层，并且在衬底上形成导电层。

39. 发明申请

US20050101141A1 Method of forming conductive stud on vertical memory device 有权
标题翻译：在垂直存储设备上形成导电螺柱的方法
公开(公告)号：US20050101141A1
公开(公告)日：2005-05-12
申请号：US10704911
申请日：2003-11-12
申请人： Shian-Jyh Lin , Chia-Sheng Yu , Wen-Sung Tsou
发明人： Shian-Jyh Lin , Chia-Sheng Yu , Wen-Sung Tsou
IPC分类号： H01L21/44 , H01L21/461 , H01L21/768 , H01L21/8242
CPC分类号： H01L21/7684 , H01L21/76877 , H01L27/10864 , H01L27/10876 , H01L27/10891
摘要： A method of forming a conductive stud is provided. The method includes providing a substrate which has an upper surface and an opening. The opening exposes a portion of a vertical memory device. A conductive layer is formed over the substrate to fill the opening. A chemical mechanical polishing is performed on the conductive layer to form a conductive stud having an upper surface substantially lower than the upper surface of the substrate.
摘要翻译：提供一种形成导电柱的方法。该方法包括提供具有上表面和开口的基底。开口暴露垂直存储器件的一部分。导电层形成在衬底上以填充开口。在导电层上进行化学机械抛光以形成具有基本上低于衬底的上表面的上表面的导电柱。

40. 发明授权

US06821843B1 Fabrication method for an array area and a support area of a dynamic random access memory 有权
标题翻译：动态随机存取存储器的阵列区域和支持区域的制作方法
公开(公告)号：US06821843B1
公开(公告)日：2004-11-23
申请号：US10847562
申请日：2004-05-17
申请人： Sheng-Tsong Chen , Shian-Jyh Lin , Ming-Cheng Chang
发明人： Sheng-Tsong Chen , Shian-Jyh Lin , Ming-Cheng Chang
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10876 , H01L29/66181
摘要： A fabrication method for a DRAM cell with dual driving voltages and a vertical transistor. Liquid phase deposition (LPD) is used to integrate an array area process and a support area process in order to simplify steps.
摘要翻译：一种具有双驱动电压的DRAM单元和垂直晶体管的制造方法。液相沉积（LPD）用于集成阵列区域过程和支持区域过程，以简化步骤。

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