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1. 发明申请

US20050239282A1 Method for forming self-aligned contact in semiconductor device 有权
标题翻译：在半导体器件中形成自对准接触的方法
公开(公告)号：US20050239282A1
公开(公告)日：2005-10-27
申请号：US10940772
申请日：2004-09-15
申请人： Meng-Hung Chen , Shian-Jyh Lin , Chia-Sheng Yu
发明人： Meng-Hung Chen , Shian-Jyh Lin , Chia-Sheng Yu
IPC分类号： H01L21/4763 , H01L21/60
CPC分类号： H01L21/76897
摘要： A method for forming a self-aligned contact on a semiconductor substrate provided with a plurality of field-effect transistors. The method comprises the steps of forming a first insulating layer comprising a nitride along a profile of a gate structure and a junction region, forming a temporary layer comprising a doped oxide on the first insulating layer, removing a portion of the temporary layer by performing a selective etch of the oxide with a mask while leaving a plug portion of the temporary layer over the junction region, forming a second insulating layer comprising an undoped oxide in a region where the portion of the temporary layer is removed, removing the plug portion by performing a selective etch of the undoped oxide to form a contact hole, removing a portion of the first insulating layer at a bottom of the contact hole, and forming a conductive contact in the contact hole.
摘要翻译：一种用于在设置有多个场效应晶体管的半导体衬底上形成自对准接触的方法。该方法包括以下步骤：沿着栅极结构和结区的轮廓形成包括氮化物的第一绝缘层，在第一绝缘层上形成包括掺杂氧化物的临时层，通过执行临时层去除一部分临时层用掩模选择性地蚀刻氧化物，同时将临时层的插塞部分留在接合区域上，形成第二绝缘层，该第二绝缘层包括去除部分临时层的区域中的未掺杂的氧化物，通过执行对未掺杂的氧化物进行选择性蚀刻以形成接触孔，在接触孔的底部除去第一绝缘层的一部分，以及在接触孔中形成导电接触。

2. 发明申请

US20050221616A1 3-stage method for forming deep trench structure and deep trench capacitor 有权
标题翻译：形成深沟槽结构和深沟槽电容器的3阶段方法
公开(公告)号：US20050221616A1
公开(公告)日：2005-10-06
申请号：US10816820
申请日：2004-04-05
申请人： Meng-Hung Chen , Shian-Jyh Lin
发明人： Meng-Hung Chen , Shian-Jyh Lin
IPC分类号： B44C1/22 , H01L21/308 , H01L21/311 , H01L21/334 , H01L21/8242
CPC分类号： H01L29/66181 , H01L21/3081 , H01L27/1087
摘要： A method for forming a deep trench structure comprises the steps of providing a silicon substrate; forming a mask layer of a predetermined pattern on the silicon substrate to expose a portion of the silicon substrate; forming a first trench in the exposed portion of the silicon substrate, the first trench having a first depth; forming a nitride layer on the surfaces of the whole structure; forming a second trench in the first trench downward, the second trench having a second depth greater than the first depth; forming another nitride layer on the surfaces of the whole structure; and forming a third trench in the second trench downward, the third trench having a third depth greater than the second depth. The method of the present invention can make the whole trench have better etch uniformity, thereby obtaining good electrical performance.
摘要翻译：形成深沟槽结构的方法包括以下步骤：提供硅衬底; 在所述硅衬底上形成预定图案的掩模层以暴露所述硅衬底的一部分; 在所述硅衬底的暴露部分中形成第一沟槽，所述第一沟槽具有第一深度; 在整个结构的表面上形成氮化物层; 在所述第一沟槽中形成第二沟槽，所述第二沟槽具有大于所述第一深度的第二深度; 在整个结构的表面上形成另一个氮化物层; 以及在所述第二沟槽中向下形成第三沟槽，所述第三沟槽的第三深度大于所述第二深度。本发明的方法可以使整个沟槽具有更好的蚀刻均匀性，从而获得良好的电性能。

3. 发明授权

US08044449B2 Memory device with a length-controllable channel 有权
标题翻译：具有长度可控通道的存储器
公开(公告)号：US08044449B2
公开(公告)日：2011-10-25
申请号：US12183021
申请日：2008-07-30
申请人： Shian-Jyh Lin , Hung-Chang Liao , Meng-Hung Chen , Chung-Yuan Lee , Pei-Ing Lee
发明人： Shian-Jyh Lin , Hung-Chang Liao , Meng-Hung Chen , Chung-Yuan Lee , Pei-Ing Lee
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A memory device is provided. The memory device includes a substrate, a trench having an upper portion and a lower portion formed in the substrate, a trench capacitor formed in the lower portion of the trench, a collar dielectric layer formed on a sidewall of the trench capacitor and extending away from a top surface of the substrate, a first doping region formed on a side of the upper portion of the trench in the substrate for serving as source/drain, a conductive layer formed in the trench and electrically connected to the first doping region, a top dielectric layer formed on conductive layer, a gate formed on the top dielectric layer, an epitaxy layer formed on both sides of the gate and on the substrate and a second doping area formed on a top of the epitaxy layer for serving as source/drain.
摘要翻译：提供存储器件。存储器件包括衬底，具有形成在衬底中的上部和下部的沟槽，形成在沟槽的下部的沟槽电容器，形成在沟槽电容器的侧壁上并且远离衬底的顶表面，形成在衬底中用作源极/漏极的沟槽的上部侧的第一掺杂区域，形成在沟槽中并电连接到第一掺杂区域的导电层，顶部形成在导电层上的电介质层，形成在顶部电介质层上的栅极，形成在栅极两侧和衬底上的外延层，以及形成在外延层的顶部上用作源极/漏极的第二掺杂区域。

4. 发明授权

US07449382B2 Memory device and fabrication method thereof 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US07449382B2
公开(公告)日：2008-11-11
申请号：US11441313
申请日：2006-05-24
申请人： Meng-Hung Chen , Shian-Jyh Lin , Neng-Tai Shih
发明人： Meng-Hung Chen , Shian-Jyh Lin , Neng-Tai Shih
IPC分类号： H01L21/8242
CPC分类号： H01L21/84 , H01L27/0207 , H01L27/10841 , H01L27/10876 , H01L29/42392
摘要： A memory device is disclosed. A substrate is provided. A plurality of pillars is disposed on the substrate. Each pillar has a plurality of epitaxial layers, has a first sidewall and a second sidewall. A trench is formed between the pillars. A common bottom electrode is disposed in a lower portion of the trench and surrounded by a node dielectric layer. A first insulating layer is disposed on the common bottom electrode inside the trench. A plurality of gate structures is disposed on the first sidewall and inside the trench. A second insulating layer is disposed inside the trench and adjacent to the gate structures. A third insulating layer, body line, and fourth insulating layer are respectively disposed on the substrate and located between the second insulating layer and the second sidewall.
摘要翻译：公开了一种存储器件。提供基板。多个支柱设置在基板上。每个柱具有多个外延层，具有第一侧壁和第二侧壁。在支柱之间形成沟槽。公共底电极设置在沟槽的下部并被节点电介质层包围。第一绝缘层设置在沟槽内的公共底部电极上。多个栅极结构设置在第一侧壁和沟槽内。第二绝缘层设置在沟槽内并与栅极结构相邻。第三绝缘层，体线和第四绝缘层分别设置在基板上并且位于第二绝缘层和第二侧壁之间。

5. 发明授权

US06767786B1 Method for forming bottle trenches by liquid phase oxide deposition 有权
标题翻译：通过液相氧化物沉积形成瓶槽的方法
公开(公告)号：US06767786B1
公开(公告)日：2004-07-27
申请号：US10413229
申请日：2003-04-14
申请人： Shian-Jyh Lin , Meng-Hung Chen , Chung-Yuan Lee
发明人： Shian-Jyh Lin , Meng-Hung Chen , Chung-Yuan Lee
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L29/66181
摘要： Method for forming bottle trenches by liquid phase oxide deposition. The method includes the steps of providing a substrate having a pad layer formed thereon, and a trench formed in a predetermined position; forming a masking layer at the bottom part of the trench; using liquid phase deposition (LPD) to form an LPD oxide layer on the sidewalls of the trench; removing the masking layer to expose the bottom part of the trench; subjecting the LPD oxide layer to annealing; and etching the bottom part of the trench not covered by the LPD oxide layer to form a bottle trench.
摘要翻译：通过液相氧化物沉积形成瓶槽的方法。该方法包括提供其上形成有衬垫层的衬底和形成在预定位置的沟槽的步骤; 在沟槽的底部形成掩模层; 使用液相沉积（LPD）在沟槽的侧壁上形成LPD氧化物层; 去除掩模层以暴露沟槽的底部; 对LPD氧化物层进行退火; 并且蚀刻未被LPD氧化物层覆盖的沟槽的底部以形成瓶沟槽。

6. 发明申请

US20070166914A1 Memory device and fabrication method thereof 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20070166914A1
公开(公告)日：2007-07-19
申请号：US11441313
申请日：2006-05-24
申请人： Meng-Hung Chen , Shian-Jyh Lin , Neng-Tai Shih
发明人： Meng-Hung Chen , Shian-Jyh Lin , Neng-Tai Shih
IPC分类号： H01L21/8242
CPC分类号： H01L21/84 , H01L27/0207 , H01L27/10841 , H01L27/10876 , H01L29/42392
摘要： A memory device is disclosed. A substrate is provided. A plurality of pillars is disposed on the substrate. Each pillar has a plurality of epitaxial layers, has a first sidewall and a second sidewall. A trench is formed between the pillars. A common bottom electrode is disposed in a lower portion of the trench and surrounded by a node dielectric layer. A first insulating layer is disposed on the common bottom electrode inside the trench. A plurality of gate structures is disposed on the first sidewall and inside the trench. A second insulating layer is disposed inside the trench and adjacent to the gate structures. A third insulating layer, body line, and fourth insulating layer are respectively disposed on the substrate and located between the second insulating layer and the second sidewall.
摘要翻译：公开了一种存储器件。提供基板。多个支柱设置在基板上。每个柱具有多个外延层，具有第一侧壁和第二侧壁。在支柱之间形成沟槽。公共底电极设置在沟槽的下部并被节点电介质层包围。第一绝缘层设置在沟槽内的公共底部电极上。多个栅极结构设置在第一侧壁和沟槽内。第二绝缘层设置在沟槽内并与栅极结构相邻。第三绝缘层，体线和第四绝缘层分别设置在基板上并且位于第二绝缘层和第二侧壁之间。

7. 发明授权

US07094672B2 Method for forming self-aligned contact in semiconductor device 有权
标题翻译：在半导体器件中形成自对准接触的方法
公开(公告)号：US07094672B2
公开(公告)日：2006-08-22
申请号：US10940772
申请日：2004-09-15
申请人： Meng-Hung Chen , Shian-Jyh Lin , Chia-Sheng Yu
发明人： Meng-Hung Chen , Shian-Jyh Lin , Chia-Sheng Yu
IPC分类号： H01L21/4763
CPC分类号： H01L21/76897
摘要： A method for forming a self-aligned contact on a semiconductor substrate provided with a plurality of field-effect transistors. The method includes the steps of forming a first insulating layer that includes a nitride along a profile of a gate structure and a junction region, forming a temporary layer that has a doped oxide on the first insulting layer, removing a portion of the temporary layer by performing a selective etch of the oxide with a mask while leaving a plug portion of the temporary layer over the junction region, forming a second insulting layer that has an undoped oxide in a region where the portion of the temporary layer is removed, removing the plug portion by performing a selective etch of the undoped oxide to form a contact hole, removing a portion of the first insulating layer at a bottom of the contact hole, and forming a conductive contact ins the contact hole.
摘要翻译：一种用于在设置有多个场效应晶体管的半导体衬底上形成自对准接触的方法。该方法包括以下步骤：沿栅极结构和结区域的轮廓形成包括氮化物的第一绝缘层，在第一绝缘层上形成具有掺杂氧化物的临时层，通过以下步骤除去临时层的一部分：用掩模进行氧化物的选择性蚀刻，同时将临时层的插塞部分留在接合区域上，形成在临时层的部分被去除的区域中具有未掺杂氧化物的第二绝缘层，去除插塞通过对未掺杂的氧化物进行选择性蚀刻以形成接触孔，在接触孔的底部除去第一绝缘层的一部分，以及在接触孔中形成导电接触。

8. 发明授权

US07094658B2 3-stage method for forming deep trench structure and deep trench capacitor 有权
标题翻译：形成深沟槽结构和深沟槽电容器的3阶段方法
公开(公告)号：US07094658B2
公开(公告)日：2006-08-22
申请号：US10816820
申请日：2004-04-05
申请人： Meng-Hung Chen , Shian-Jyh Lin
发明人： Meng-Hung Chen , Shian-Jyh Lin
IPC分类号： H01L21/20
CPC分类号： H01L29/66181 , H01L21/3081 , H01L27/1087
摘要： A method for forming a deep trench structure comprises the steps of providing a silicon substrate; forming a mask layer of a predetermined pattern on the silicon substrate to expose a portion of the silicon substrate; forming a first trench in the exposed portion of the silicon substrate, the first trench having a first depth; forming a nitride layer on the surfaces of the whole structure; forming a second trench in the first trench downward, the second trench having a second depth greater than the first depth; forming another nitride layer on the surfaces of the whole structure; and forming a third trench in the second trench downward, the third trench having a third depth greater than the second depth. The method of the present invention can make the whole trench have better etch uniformity, thereby obtaining good electrical performance.
摘要翻译：形成深沟槽结构的方法包括以下步骤：提供硅衬底; 在所述硅衬底上形成预定图案的掩模层以暴露所述硅衬底的一部分; 在所述硅衬底的暴露部分中形成第一沟槽，所述第一沟槽具有第一深度; 在整个结构的表面上形成氮化物层; 在所述第一沟槽中形成第二沟槽，所述第二沟槽具有大于所述第一深度的第二深度; 在整个结构的表面上形成另一个氮化物层; 以及在所述第二沟槽中向下形成第三沟槽，所述第三沟槽的第三深度大于所述第二深度。本发明的方法可以使整个沟槽具有更好的蚀刻均匀性，从而获得良好的电性能。

9. 发明申请

US20050272236A1 METHOD FOR FORMING BIT LINE CONTACT HOLE/CONTACT STRUCTURE 有权
标题翻译：形成位线接触孔/接触结构的方法
公开(公告)号：US20050272236A1
公开(公告)日：2005-12-08
申请号：US10862570
申请日：2004-06-08
申请人： Meng-Hung Chen , Chia-Sheng Yu
发明人： Meng-Hung Chen , Chia-Sheng Yu
IPC分类号： H01L21/44 , H01L21/60 , H01L21/8242
CPC分类号： H01L21/76897 , H01L27/10888 , H01L27/10891
摘要： Disclosed is a method for forming a bit line contact hole/contact structure. The method of the present invention comprises steps of providing a substrate; forming a pluarality of word line structures on the substrate; forming a doped dielectric layer on the substrate having the word line structures formed thereon; defining a position for forming a bit line contact hole; removing the doped dielectric layer other than the portion at the position for forming the bit line contact hole; forming a non-doped dielectric layer on the substrate having the word line structures and residual doped dielectric layer formed thereon; removing the residual doped dielectric layer by using an etchant with a high selectivity for doped dielectric layer/non-doped dielectric layer to form a bit line contact hole; and filling the bit line contact hole with conductive material for form a bit line contact structure.
摘要翻译：公开了一种形成位线接触孔/接触结构的方法。本发明的方法包括提供基底的步骤; 在衬底上形成字线结构的一个重要原因; 在其上形成有字线结构的衬底上形成掺杂介质层; 限定用于形成位线接触孔的位置; 除去除了用于形成位线接触孔的位置处的部分之外的掺杂电介质层; 在其上形成有字线结构和残留掺杂介电层的衬底上形成非掺杂电介质层; 通过使用对掺杂介质层/非掺杂介质层具有高选择性的蚀刻剂来去除残余掺杂介电层，以形成位线接触孔; 并用导电材料填充位线接触孔，形成位线接触结构。

10. 发明授权

US07084057B2 Bit line contact structure and fabrication method thereof 有权
标题翻译：位线接触结构及其制造方法
公开(公告)号：US07084057B2
公开(公告)日：2006-08-01
申请号：US11019339
申请日：2004-12-21
申请人： Meng-Hung Chen
发明人： Meng-Hung Chen
IPC分类号： H03L21/4763
CPC分类号： H01L21/76897 , H01L21/76829 , H01L23/485 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： A bit line contact structure and fabrication method thereof. The method includes providing a substrate having a transistor, with a gate electrode, drain region, and source region, on the substrate, blanketly forming a first dielectric layer on the transistor using spin coating, and patterning the first dielectric layer, forming a via exposing the drain region.
摘要翻译：一种位线接触结构及其制造方法。该方法包括在衬底上提供具有晶体管，栅极，漏极区和源极区的衬底，在旋转涂层上在晶体管上覆盖地形成第一介电层，并对第一介电层进行构图，形成通孔露出漏极区域。

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