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1. 发明授权

US07449382B2 Memory device and fabrication method thereof 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US07449382B2
公开(公告)日：2008-11-11
申请号：US11441313
申请日：2006-05-24
申请人： Meng-Hung Chen , Shian-Jyh Lin , Neng-Tai Shih
发明人： Meng-Hung Chen , Shian-Jyh Lin , Neng-Tai Shih
IPC分类号： H01L21/8242
CPC分类号： H01L21/84 , H01L27/0207 , H01L27/10841 , H01L27/10876 , H01L29/42392
摘要： A memory device is disclosed. A substrate is provided. A plurality of pillars is disposed on the substrate. Each pillar has a plurality of epitaxial layers, has a first sidewall and a second sidewall. A trench is formed between the pillars. A common bottom electrode is disposed in a lower portion of the trench and surrounded by a node dielectric layer. A first insulating layer is disposed on the common bottom electrode inside the trench. A plurality of gate structures is disposed on the first sidewall and inside the trench. A second insulating layer is disposed inside the trench and adjacent to the gate structures. A third insulating layer, body line, and fourth insulating layer are respectively disposed on the substrate and located between the second insulating layer and the second sidewall.
摘要翻译：公开了一种存储器件。提供基板。多个支柱设置在基板上。每个柱具有多个外延层，具有第一侧壁和第二侧壁。在支柱之间形成沟槽。公共底电极设置在沟槽的下部并被节点电介质层包围。第一绝缘层设置在沟槽内的公共底部电极上。多个栅极结构设置在第一侧壁和沟槽内。第二绝缘层设置在沟槽内并与栅极结构相邻。第三绝缘层，体线和第四绝缘层分别设置在基板上并且位于第二绝缘层和第二侧壁之间。

2. 发明申请

US20080268590A1 METHOD FOR FORMING A SEMICONDUCTOR DEVICE WITH A SINGLE-SIDED BURIED STRAP 有权
标题翻译：用单面印刷带形成半导体器件的方法
公开(公告)号：US20080268590A1
公开(公告)日：2008-10-30
申请号：US12035542
申请日：2008-02-22
申请人： Neng-Tai SHIH , Ming-Cheng CHANG
发明人： Neng-Tai SHIH , Ming-Cheng CHANG
IPC分类号： H01L21/8242
CPC分类号： H01L27/10867
摘要： A method for forming a semiconductor device with a single-sided buried strap is provided. The method includes the steps of providing a substrate with a trench, forming a semiconductor component in a lower portion of the trench to expose a higher portion of the trench, forming a first dielectric layer on a sidewall of the higher portion of the trench, forming a first conductive layer in the trench and adjacent to the first dielectric layer, forming a second dielectric layer on the first dielectric layer and the first conductive layer, forming a plurality of gate structures on the substrate, wherein one of the gate structures on the second dielectric layer is offset for a distance from the second dielectric layer, removing a portion of the second dielectric layer and a portion of the first dielectric layer to form an opening by using the gate structure as a mask, and forming a second conductive layer in the opening to electrically couple to the first conductive layer, whereby the semiconductor device with the single sided buried strap is formed.
摘要翻译：提供一种用于形成具有单面埋入带的半导体器件的方法。该方法包括以下步骤：提供具有沟槽的衬底，在沟槽的下部形成半导体部件以暴露沟槽的较高部分，在沟槽的较高部分的侧壁上形成第一电介质层，形成在所述沟槽中并与所述第一电介质层相邻的第一导电层，在所述第一介电层和所述第一导电层上形成第二电介质层，在所述衬底上形成多个栅极结构，其中所述第二导电层中的所述栅极结构之一电介质层与第二电介质层偏移一定距离，通过使用栅极结构作为掩模去除第二电介质层的一部分和第一介电层的一部分以形成开口，并且在第二介电层中形成第二导电层开口以电耦合到第一导电层，由此形成具有单面掩埋带的半导体器件。

3. 发明授权

US07408215B2 Dynamic random access memory 有权
标题翻译：动态随机存取存储器
公开(公告)号：US07408215B2
公开(公告)日：2008-08-05
申请号：US11696160
申请日：2007-04-03
申请人： Ming-Cheng Chang , Neng-Tai Shih
发明人： Ming-Cheng Chang , Neng-Tai Shih
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10841 , H01L27/0207 , H01L27/1087 , H01L27/10876
摘要： A DRAM structure on a silicon substrate has an active area, gate conductors, deep trench capacitors, and vertical transistors. The deep trench capacitors are formed at intersections of the active area and the gate conductors, and each deep trench capacitor is coupled electrically to the corresponding vertical transistor to form a memory cell. The transistor includes a gate, a source in a lateral side of the gate, and a drain in another lateral side of the gate The depth of the drain is different from the depth of the source.
摘要翻译：硅衬底上的DRAM结构具有有源区，栅极导体，深沟槽电容器和垂直晶体管。深沟槽电容器形成在有源区和栅极导体的交点处，并且每个深沟槽电容器电耦合到相应的垂直晶体管以形成存储单元。晶体管包括栅极，栅极的侧面中的源极和栅极的另一侧面中的漏极漏极的深度不同于源极的深度。

4. 发明申请

US20060094178A1 Method of fabricating MOS transistor by millisecond anneal 有权
标题翻译：通过毫秒退火制造MOS晶体管的方法
公开(公告)号：US20060094178A1
公开(公告)日：2006-05-04
申请号：US11174750
申请日：2005-07-05
申请人： Shian-Jyh Lin , Sheng-Tsung Chen , Neng-Tai Shih , Chien-Chang Huang , Chien-Jung Yang , Yi-Jung Chen
发明人： Shian-Jyh Lin , Sheng-Tsung Chen , Neng-Tai Shih , Chien-Chang Huang , Chien-Jung Yang , Yi-Jung Chen
IPC分类号： H01L21/8234
CPC分类号： H01L29/6659 , H01L21/324 , H01L29/7833
摘要： A method of fabricating a MOS transistor by millisecond annealing. A semiconductor substrate with a gate stack comprising a gate electrode overlying a gate dielectric layer on a top surface of a semiconductor substrate is provided. At least one implanting process is performed to form two doped regions on opposite sides of the gate electrode. Millisecond annealing activates dopants in the doped regions. The millisecond anneal includes rapid heating and rapid cooling within 1 to 50 milliseconds.
摘要翻译：一种通过毫秒退火制造MOS晶体管的方法。提供了具有栅叠层的半导体衬底，其包括覆盖半导体衬底的顶表面上的栅介质层的栅电极。执行至少一个注入工艺以在栅电极的相对侧上形成两个掺杂区域。毫秒退火激活掺杂区中的掺杂剂。毫秒退火包括快速加热和1至50毫秒内的快速冷却。

5. 发明申请

US20050016948A1 Method for fabricating trench isolations with high aspect ratio 有权
公开(公告)号：US20050016948A1
公开(公告)日：2005-01-27
申请号：US10690999
申请日：2003-10-22
申请人： Sheng-Wei Yang , Neng-Tai Shih , Wen-Sheng Liao , Chih-How Chang
发明人： Sheng-Wei Yang , Neng-Tai Shih , Wen-Sheng Liao , Chih-How Chang
IPC分类号： H01L21/3105 , H01L21/311 , H01L21/316 , H01L21/762
CPC分类号： H01L21/76224 , H01L21/31053 , H01L21/31116 , H01L21/31612 , H01L21/76232
摘要： A method of fabricating a trench isolation with high aspect ratio. The method comprises the steps of: providing a substrate with a trench; depositing a first isolation layer filling the trench by low pressure chemical vapor deposition; etching the first isolation layer so that its surface is lowered to the opening of the trench; depositing a second isolation layer to fill the trench without voids by high density plasma chemical vapor deposition and achieving global planarization by chemical-mechanical polishing then providing a rapidly annealing procedure. Accordingly, the present invention achieves void-free trench isolation with high aspect ratio.

6. 发明申请

US20100072449A1 RRAM WITH IMPROVED RESISTANCE TRANSFORMATION CHARACTERISTIC AND METHOD OF MAKING THE SAME 有权
标题翻译：具有改进的电阻变换特性的RRAM及其制造方法
公开(公告)号：US20100072449A1
公开(公告)日：2010-03-25
申请号：US12324841
申请日：2008-11-27
申请人： Chun-I Hsieh , Chang-Rong Wu , Neng-Tai Shih , Kou-Chen Liu
发明人： Chun-I Hsieh , Chang-Rong Wu , Neng-Tai Shih , Kou-Chen Liu
IPC分类号： H01L21/04 , H01L45/00
CPC分类号： H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/16
摘要： A method for fabricating an RRAM is provided. First, a bottom electrode is formed. A resistive layer is formed on the bottom electrode. A top electrode is then formed on the resistive layer, wherein the top electrode is selected from the group consisting of indium tin oxide (ITO) and indium zinc oxide (IZO). Finally, the top electrode is irradiated with UV light.
摘要翻译：提供了一种制造RRAM的方法。首先，形成底部电极。电阻层形成在底部电极上。然后在电阻层上形成顶部电极，其中顶部电极选自氧化铟锡（ITO）和氧化铟锌（IZO）。最后，用紫外光照射顶部电极。

7. 发明授权

US07160804B2 Method of fabricating MOS transistor by millisecond anneal 有权
标题翻译：通过毫秒退火制造MOS晶体管的方法
公开(公告)号：US07160804B2
公开(公告)日：2007-01-09
申请号：US11174750
申请日：2005-07-05
申请人： Shian-Jyh Lin , Sheng-Tsung Chen , Neng-Tai Shih , Chien-Chang Huang , Chien-Jung Yang , Yi-Jung Chen
发明人： Shian-Jyh Lin , Sheng-Tsung Chen , Neng-Tai Shih , Chien-Chang Huang , Chien-Jung Yang , Yi-Jung Chen
IPC分类号： H01L21/4763
CPC分类号： H01L29/6659 , H01L21/324 , H01L29/7833
摘要： A method of fabricating a MOS transistor by millisecond annealing. A semiconductor substrate with a gate stack comprising a gate electrode overlying a gate dielectric layer on a top surface of a semiconductor substrate is provided. At least one implanting process is performed to form two doped regions on opposite sides of the gate electrode. Millisecond annealing activates dopants in the doped regions. The millisecond anneal includes rapid heating and rapid cooling within 1 to 50 milliseconds.
摘要翻译：一种通过毫秒退火制造MOS晶体管的方法。提供了具有栅叠层的半导体衬底，其包括覆盖半导体衬底的顶表面上的栅介质层的栅电极。执行至少一个注入工艺以在栅电极的相对侧上形成两个掺杂区域。毫秒退火激活掺杂区中的掺杂剂。毫秒退火包括快速加热和1至50毫秒内的快速冷却。

8. 发明申请

US20050124111A1 Method for forming a self-aligned buried strap in a vertical memory cell 有权
公开(公告)号：US20050124111A1
公开(公告)日：2005-06-09
申请号：US10846321
申请日：2004-05-14
申请人： Cheng-Chih Huang , Sheng-Wei Yang , Neng-Tai Shih , Chen-Chou Huang
发明人： Cheng-Chih Huang , Sheng-Wei Yang , Neng-Tai Shih , Chen-Chou Huang
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/8238 , H01L21/20 , H01L21/8234 , H01L21/8244
CPC分类号： H01L28/40 , H01L27/10864 , H01L27/10867
摘要： A method for forming a self-aligned buried strap in a vertical memory cell. A semiconductor substrate with a trench is provided. A collar dielectric layer is conformally formed on the trench bottom portion, and the trench is filled with a conducting layer. The collar dielectric layer is etched below the level of the surface of the conducting layer to form a groove between the conducting layer and the trench. The groove is filled with a doped conducting layer. The dopant in the doped conducting layer is diffused to the semiconductor substrate in an ion diffusion area as a buried strap. The conducting layer and the doped conducting layer are etched below the ion diffusion area. A top trench insulating layer is formed on the bottom of the trench, wherein the top trench insulating layer is lower than the ion diffusion area.

9. 发明授权

US08487290B2 RRAM with improved resistance transformation characteristic and method of making the same 有权
标题翻译： RRAM具有改进的电阻变换特性及其制造方法
公开(公告)号：US08487290B2
公开(公告)日：2013-07-16
申请号：US12324841
申请日：2008-11-27
申请人： Chun-I Hsieh , Chang-Rong Wu , Neng-Tai Shih , Kou-Chen Liu
发明人： Chun-I Hsieh , Chang-Rong Wu , Neng-Tai Shih , Kou-Chen Liu
IPC分类号： H01L47/00
CPC分类号： H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/16
摘要： A method for fabricating an RRAM is provided. First, a bottom electrode is formed. A resistive layer is formed on the bottom electrode. A top electrode is then formed on the resistive layer, wherein the top electrode is selected from the group consisting of indium tin oxide (ITO) and indium zinc oxide (IZO). Finally, the top electrode is irradiated with UV light.
摘要翻译：提供了一种制造RRAM的方法。首先，形成底部电极。电阻层形成在底部电极上。然后在电阻层上形成顶部电极，其中顶部电极选自氧化铟锡（ITO）和氧化铟锌（IZO）。最后，用紫外光照射顶部电极。

10. 发明授权

US07993985B2 Method for forming a semiconductor device with a single-sided buried strap 有权
标题翻译：用单面埋置带形成半导体器件的方法
公开(公告)号：US07993985B2
公开(公告)日：2011-08-09
申请号：US12035542
申请日：2008-02-22
申请人： Neng-Tai Shih , Ming-Cheng Chang
发明人： Neng-Tai Shih , Ming-Cheng Chang
IPC分类号： H01L21/335
CPC分类号： H01L27/10867
摘要： A method for forming a semiconductor device with a single-sided buried strap is provided. The method includes the steps of providing a substrate with a trench, forming a semiconductor component in a lower portion of the trench to expose a higher portion of the trench, forming a first dielectric layer on a sidewall of the higher portion of the trench, forming a first conductive layer in the trench and adjacent to the first dielectric layer, forming a second dielectric layer on the first dielectric layer and the first conductive layer, forming a plurality of gate structures on the substrate, wherein one of the gate structures on the second dielectric layer is offset for a distance from the second dielectric layer, removing a portion of the second dielectric layer and a portion of the first dielectric layer to form an opening by using the gate structure as a mask, and forming a second conductive layer in the opening to electrically couple to the first conductive layer, whereby the semiconductor device with the single sided buried strap is formed.
摘要翻译：提供一种用于形成具有单面埋入带的半导体器件的方法。该方法包括以下步骤：提供具有沟槽的衬底，在沟槽的下部形成半导体部件以暴露沟槽的较高部分，在沟槽的较高部分的侧壁上形成第一电介质层，形成在所述沟槽中并与所述第一电介质层相邻的第一导电层，在所述第一介电层和所述第一导电层上形成第二电介质层，在所述衬底上形成多个栅极结构，其中所述第二导电层中的所述栅极结构之一电介质层与第二电介质层偏移一定距离，通过使用栅极结构作为掩模去除第二电介质层的一部分和第一介电层的一部分以形成开口，并且在第二介电层中形成第二导电层开口以电耦合到第一导电层，由此形成具有单面掩埋带的半导体器件。

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